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src include/opcode/ChangeLog include/opcode/mi ...
- From: rsandifo at sources dot redhat dot com
- To: binutils-cvs at sources dot redhat dot com
- Date: 30 Sep 2002 11:58:10 -0000
- Subject: src include/opcode/ChangeLog include/opcode/mi ...
CVSROOT: /cvs/src
Module name: src
Changes by: rsandifo@sources.redhat.com 2002-09-30 04:58:10
Modified files:
include/opcode : ChangeLog mips.h
opcodes : ChangeLog mips-dis.c mips-opc.c
Log message:
[include/opcode/]
* mips.h: Update comment for new opcodes.
(OP_MASK_VECBYTE, OP_SH_VECBYTE): New.
(OP_MASK_VECALIGN, OP_SH_VECALIGN): New.
(INSN_4111, INSN_4120, INSN_5400, INSN_5500): New.
(CPU_VR4120, CPU_VR5400, CPU_VR5500): New.
(OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags.
Don't match CPU_R4111 with INSN_4100.
[opcodes/]
* mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'.
(mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400
and bfd_mach_mips5500.
* mips-opc.c (V1): Include INSN_4111 and INSN_4120.
(N411, N412, N5, N54, N55): New convenience defines.
(mips_builtin_opcodes): Add vr4120, vr5400 and vr5500 opcodes.
Change dmadd16 and madd16 from V1 to N411.
Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/include/opcode/ChangeLog.diff?cvsroot=src&r1=1.176&r2=1.177
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/include/opcode/mips.h.diff?cvsroot=src&r1=1.28&r2=1.29
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.491&r2=1.492
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/mips-dis.c.diff?cvsroot=src&r1=1.33&r2=1.34
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/mips-opc.c.diff?cvsroot=src&r1=1.38&r2=1.39