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src gas/testsuite/ChangeLog gas/testsuite/gas/ ...
- From: vapier at sourceware dot org
- To: binutils-cvs at sourceware dot org
- Date: 13 Feb 2011 18:54:49 -0000
- Subject: src gas/testsuite/ChangeLog gas/testsuite/gas/ ...
CVSROOT: /cvs/src
Module name: src
Changes by: vapier@sourceware.org 2011-02-13 18:54:49
Modified files:
gas/testsuite : ChangeLog
gas/testsuite/gas/bfin: arithmetic.d parallel.d parallel3.d
vector.d vector2.d
opcodes : ChangeLog bfin-dis.c
Log message:
opcodes: blackfin: fix decoding of dsp mult insns
When assigning to a register half, the mac0 part of the mult insn
was not decoding properly. It would always show a full dreg instead
of the dreg low half.
Once we fix the disassembler, we have to update a few of the gas
tests as their previous expected output was incorrect.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/ChangeLog.diff?cvsroot=src&r1=1.1851&r2=1.1852
http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/bfin/arithmetic.d.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/bfin/parallel.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/bfin/parallel3.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/bfin/vector.d.diff?cvsroot=src&r1=1.3&r2=1.4
http://sourceware.org/cgi-bin/cvsweb.cgi/src/gas/testsuite/gas/bfin/vector2.d.diff?cvsroot=src&r1=1.5&r2=1.6
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.1697&r2=1.1698
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/bfin-dis.c.diff?cvsroot=src&r1=1.34&r2=1.35