MIPS GAS PATCH: cop_interlocks

[Gavin Romig-Koch <gavin at cetus dot cygnus dot com>]

MIPSI - MIPSIII processors, in general, have a pipeline hazard 
that comes from the fact that the branch on coprocessor conditional
instruction reads the coprocessor conditional code one stage eariler
than "expected".  GAS is using the flag cop_interlocks to indicate
that the 4300 has interlocks to protected against this hazard.  My
understanding of the 4300 manual says that it doesn't have such an
interlock - it only has an interlock that protects against the FP load
delay slot hazard.  The patch below changes the use of cop_interlocks
to follow my understanding of the 4300.

I'm wondering if anyone can confirm or deny my understanding of the
situation?  If I'm correct, is this OK to commit?

     * config/tc-mips.c : Correct the usage of cop_interlocks.


Index: tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.9
diff -p -c -r1.9 tc-mips.c
*** tc-mips.c	2000/01/14 17:58:29	1.9
--- tc-mips.c	2000/02/26 19:00:18
***************
*** 1,5 ****
  /* tc-mips.c -- assemble code for a MIPS chip.
!    Copyright (C) 1993, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
     Contributed by the OSF and Ralph Campbell.
     Written by Keith Knowles and Ralph Campbell, working independently.
     Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
--- 1,5 ----
  /* tc-mips.c -- assemble code for a MIPS chip.
!    Copyright (C) 1993, 94, 95, 96, 97, 98, 1999, 2000 Free Software Foundation, Inc.
     Contributed by the OSF and Ralph Campbell.
     Written by Keith Knowles and Ralph Campbell, working independently.
     Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
*************** static int mips_32bitmode = 0;
*** 260,266 ****
     || mips_cpu == 3900)
  
  /* As with other "interlocks" this is used by hardware that has FP
!    (co-processor) interlocks.  */
  /* Itbl support may require additional care here. */
  #define cop_interlocks (mips_cpu == 4300                            \
  			)
--- 260,270 ----
     || mips_cpu == 3900)
  
  /* As with other "interlocks" this is used by hardware that has FP
!    (co-processor) interlocks. 
! 
!   The 4300 has interlocks that protect against the hazard of using
!   a floating point register before a previous load of that register
!   (from memory or from a GPR) is complete.  */
  /* Itbl support may require additional care here. */
  #define cop_interlocks (mips_cpu == 4300                            \
  			)
*************** append_insn (place, ip, address_expr, re
*** 1538,1545 ****
  	}
        else if (! mips_opts.mips16
  	       && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
! 	       && (prev_pinfo & INSN_WRITE_COND_CODE)
!                && ! cop_interlocks)
  	{
  	  /* The previous instruction sets the coprocessor condition
  	     codes, but does not require a general coprocessor delay
--- 1542,1548 ----
  	}
        else if (! mips_opts.mips16
  	       && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
! 	       && (prev_pinfo & INSN_WRITE_COND_CODE))
  	{
  	  /* The previous instruction sets the coprocessor condition
  	     codes, but does not require a general coprocessor delay
*************** mips_emit_delays (insns)
*** 2307,2317 ****
        nops = 0;
        if ((! mips_opts.mips16
  	   && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
! 	   && (! cop_interlocks
!                && (prev_insn.insn_mo->pinfo
!                    & (INSN_LOAD_COPROC_DELAY
!                       | INSN_COPROC_MOVE_DELAY
!                       | INSN_WRITE_COND_CODE))))
  	  || (! hilo_interlocks
  	      && (prev_insn.insn_mo->pinfo
  		  & (INSN_READ_LO
--- 2310,2321 ----
        nops = 0;
        if ((! mips_opts.mips16
  	   && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
! 	   && ! cop_interlocks
! 	   && (prev_insn.insn_mo->pinfo
! 	       & (INSN_LOAD_COPROC_DELAY|INSN_COPROC_MOVE_DELAY)))
! 	  || (! mips_opts.mips16
! 	      && mips_opts.isa < 4
! 	      && (prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
  	  || (! hilo_interlocks
  	      && (prev_insn.insn_mo->pinfo
  		  & (INSN_READ_LO
*************** mips_emit_delays (insns)
*** 2329,2336 ****
  	  ++nops;
  	  if ((! mips_opts.mips16
  	       && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
! 	       && (! cop_interlocks
!                    && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
  	      || (! hilo_interlocks
  		  && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
  		      || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
--- 2333,2339 ----
  	  ++nops;
  	  if ((! mips_opts.mips16
  	       && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
! 	       && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
  	      || (! hilo_interlocks
  		  && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
  		      || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
*************** mips_emit_delays (insns)
*** 2341,2348 ****
  	}
        else if ((! mips_opts.mips16
  		&& ISA_HAS_COPROC_DELAYS (mips_opts.isa)
! 		&& (! cop_interlocks
!                     && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
  	       || (! hilo_interlocks
  		   && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
  		       || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
--- 2344,2350 ----
  	}
        else if ((! mips_opts.mips16
  		&& ISA_HAS_COPROC_DELAYS (mips_opts.isa)
! 		&& prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
  	       || (! hilo_interlocks
  		   && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
  		       || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))