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patch for thumb disassembler allows conditional branch-always to be disassembled
- To: binutils at sourceware dot cygnus dot com
- Subject: patch for thumb disassembler allows conditional branch-always to be disassembled
- From: Thomas de Lellis <tdel at windriver dot com>
- Date: Tue, 28 Mar 2000 11:44:57 -0800
The thumb branch-always conditional branch instruction 0xde00
was not being disassembled.
This patch turns it from "undefined" into "b"...
Tom
=======================================================================
2000-03-28 Thomas de Lellis <tdel@windriver.com>
* arm-opc.h: 0xde00 thumb opcode now
disassembles to "b" (branch) instead of
"undefined". It's a conditional branch where
the condition is "always"...
=======================================================================
*** arm-opc.h@@/main/2 Mon Jun 7 10:28:02 1999
--- arm-opc.h Tue Mar 28 11:21:50 2000
*************** static struct thumb_opcode thumb_opcodes
*** 263,270 ****
{0xDB00, 0xFF00, "blt\t%0-7B"},
{0xDC00, 0xFF00, "bgt\t%0-7B"},
{0xDD00, 0xFF00, "ble\t%0-7B"},
/* format 17 */
- {0xDE00, 0xFF00, "undefined"},
{0xDF00, 0xFF00, "swi\t%0-7d"},
/* format 9 */
{0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},
--- 263,270 ----
{0xDB00, 0xFF00, "blt\t%0-7B"},
{0xDC00, 0xFF00, "bgt\t%0-7B"},
{0xDD00, 0xFF00, "ble\t%0-7B"},
+ {0xDE00, 0xFF00, "b\t%0-7B"},
/* format 17 */
{0xDF00, 0xFF00, "swi\t%0-7d"},
/* format 9 */
{0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},
FAIL ==================================================================
a.o: file format elf32-littlearm
Disassembly of section .text:
00000000 <x>:
0: 46c0 nop (mov r8,r8)
2: 46c0 nop (mov r8,r8)
4: 46c0 nop (mov r8,r8)
6: 46c0 nop (mov r8,r8)
00000008 <loop>:
8: 46c0 nop (mov r8,r8)
a: e7fd b 8 <loop>
c: defc undefined
PASS ==================================================================
a.o: file format elf32-littlearm
Disassembly of section .text:
00000000 <x>:
0: 46c0 nop (mov r8,r8)
2: 46c0 nop (mov r8,r8)
4: 46c0 nop (mov r8,r8)
6: 46c0 nop (mov r8,r8)
00000008 <loop>:
8: 46c0 nop (mov r8,r8)
a: e7fd b 8 <loop>
c: defc b 8 <loop>