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[patch] testsuite entry for gas MIPS32 instruction assembly
- To: binutils at sourceware dot cygnus dot com
- Subject: [patch] testsuite entry for gas MIPS32 instruction assembly
- From: cgd at sibyte dot com (Chris G. Demetriou)
- Date: 10 Oct 2000 16:20:54 -0700
Below is a patch which adds an entry to the GAS testsuite to verify
correct assembly of instructions added in MIPS32 (as described in the
MIPS32 4Kc manual and the IDE RC32364 manual). Apply it in
src/gas/testsuite.
This test does not currently pass because of some deficiencies in the
current source. I have patches to address those deficiencies and will
be supplying them in the near future, so I didn't setup_xfail it.
chris
===================================================================
2000-10-10 Chris Demetriou <cgd@sibyte.com>
* gas/mips/mips32.s, gas/mips/mips32.d: New files for MIPS32
instruction assembly test.
* gas/mips/mips.exp: Add the test mentioned above.
Index: gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.4
diff -c -r1.4 mips.exp
*** mips.exp 2000/05/11 01:55:11 1.4
--- mips.exp 2000/10/10 23:11:24
***************
*** 88,93 ****
--- 88,94 ----
run_dump_test "mips4100"
run_dump_test "lineno"
run_dump_test "sync"
+ run_dump_test "mips32"
# Make sure that -mcpu=FOO and -mFOO are equivalent. Assemble a file
# containing 4650-specific instructions with -m4650 and -mcpu=4650,
Index: gas/mips/mips32.d
===================================================================
RCS file: mips32.d
diff -N mips32.d
*** /dev/null Tue May 5 13:32:27 1998
--- mips32.d Tue Oct 10 16:11:24 2000
***************
*** 0 ****
--- 1,48 ----
+ #objdump: -dr --prefix-addresses --show-raw-insn
+ #name: MIPS MIPS32 instructions
+ #as: -mips32
+
+ # Check MIPS32 instruction assembly
+
+ .*: +file format elf.*mips.*
+
+ Disassembly of section .text:
+ 0+0000 <[^>]*> 70410821 clo \$at,\$v0
+ 0+0004 <[^>]*> 70831820 clz \$v1,\$a0
+ 0+0008 <[^>]*> 70a60000 mad \$a1,\$a2
+ 0+000c <[^>]*> 70e80001 madu \$a3,\$t0
+ 0+0010 <[^>]*> 712a0004 msub \$t1,\$t2
+ 0+0014 <[^>]*> 716c0005 msubu \$t3,\$t4
+ 0+0018 <[^>]*> 71cf6802 mul \$t5,\$t6,\$t7
+ 0+001c <[^>]*> ce040000 pref 0x4,0\(\$s0\)
+ 0+0020 <[^>]*> ce247fff pref 0x4,32767\(\$s1\)
+ 0+0024 <[^>]*> ce448000 pref 0x4,-32768\(\$s2\)
+ 0+0028 <[^>]*> 00000040 ssnop
+ 0+002c <[^>]*> 4900fff4 bc2f 0+0000 <text_label>
+ 0+0030 <[^>]*> 00000000 nop
+ 0+0034 <[^>]*> 4902fff2 bc2fl 0+0000 <text_label>
+ 0+0038 <[^>]*> 00000000 nop
+ 0+003c <[^>]*> 4901fff0 bc2t 0+0000 <text_label>
+ 0+0040 <[^>]*> 00000000 nop
+ 0+0044 <[^>]*> 4903ffee bc2tl 0+0000 <text_label>
+ 0+0048 <[^>]*> 00000000 nop
+ 0+004c <[^>]*> 48411000 cfc2 \$at,\$2
+ 0+0050 <[^>]*> 4b234567 c2 0x1234567
+ 0+0054 <[^>]*> 48c21800 ctc2 \$v0,\$3
+ 0+0058 <[^>]*> 48032000 mfc2 \$v1,\$4
+ 0+005c <[^>]*> 48042800 mfc2 \$a0,\$5
+ 0+0060 <[^>]*> 48053007 mfc2 \$a1,\$6,7
+ 0+0064 <[^>]*> 48863800 mtc2 \$a2,\$7
+ 0+0068 <[^>]*> 48874000 mtc2 \$a3,\$8
+ 0+006c <[^>]*> 48884807 mtc2 \$t0,\$9,7
+ 0+0070 <[^>]*> bc250000 cache 0x5,0\(\$at\)
+ 0+0074 <[^>]*> bc457fff cache 0x5,32767\(\$v0\)
+ 0+0078 <[^>]*> bc658000 cache 0x5,-32768\(\$v1\)
+ 0+007c <[^>]*> 42000018 eret
+ 0+0080 <[^>]*> 42000008 tlbp
+ 0+0084 <[^>]*> 42000001 tlbr
+ 0+0088 <[^>]*> 42000002 tlbwi
+ 0+008c <[^>]*> 42000006 tlbwr
+ 0+0090 <[^>]*> 42000020 wait
+ 0+0094 <[^>]*> 42000020 wait
+ 0+0098 <[^>]*> 4359e260 wait 0x56789
Index: gas/mips/mips32.s
===================================================================
RCS file: mips32.s
diff -N mips32.s
*** /dev/null Tue May 5 13:32:27 1998
--- mips32.s Tue Oct 10 16:11:24 2000
***************
*** 0 ****
--- 1,59 ----
+ # source file to test assembly of mips32 instructions
+
+ .set noreorder
+ .set noat
+
+ .globl text_label .text
+ text_label:
+
+ # unprivileged CPU instructions
+
+ clo $1, $2
+ clz $3, $4
+ madd $5, $6 # disassembles as mad ...
+ maddu $7, $8 # disassembles as madu ...
+ msub $9, $10
+ msubu $11, $12
+ mul $13, $14, $15
+ pref 4, ($16)
+ pref 4, 32767($17)
+ pref 4, -32768($18)
+ ssnop
+
+
+ # unprivileged coprocessor instructions.
+ # these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
+
+ bc2f text_label
+ nop
+ bc2fl text_label
+ nop
+ bc2t text_label
+ nop
+ bc2tl text_label
+ nop
+ # XXX other BCzCond encodings not currently expressable
+ cfc2 $1, $2
+ cop2 0x1234567 # disassembles as c2 ...
+ ctc2 $2, $3
+ mfc2 $3, $4
+ mfc2 $4, $5, 0 # disassembles without sel
+ mfc2 $5, $6, 7
+ mtc2 $6, $7
+ mtc2 $7, $8, 0 # disassembles without sel
+ mtc2 $8, $9, 7
+
+
+ # privileged instructions
+
+ cache 5, ($1)
+ cache 5, 32767($2)
+ cache 5, -32768($3)
+ eret
+ tlbp
+ tlbr
+ tlbwi
+ tlbwr
+ wait
+ wait 0 # disassembles without code
+ wait 0x56789