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[patch] addition of MIPS V and MIPS64 option recognition support
- To: binutils at sourceware dot cygnus dot com
- Subject: [patch] addition of MIPS V and MIPS64 option recognition support
- From: cgd at sibyte dot com (Chris G. Demetriou)
- Date: 13 Oct 2000 16:49:15 -0700
The patch below adds MIPS V (-mips5) and MIPS64 option recognition and
generic CPU support.
From consultation with several former SGI processor designers, I
understand that no MIPS V cpu was ever built, and given that it's
fairly unlikely that one will be since MIPS V is being, basically,
superseded by MIPS64 (which is a superset). As a consequence of this,
since binutils want a processor to with each ISA, i've used a "generic
mips5" as the processor type.
MIPS64, like MIPS32, is (or will be when silicon starts appearing 8-)
a standard ISA, meaning that there may well be vanilla implementations
which implement the standard ISA and that's it. So, for that, as with
my previous patch to the mips32 support, i've used "generic mips32" as
the processor type.
Unfortunately, I cannot at this time provide information about the
additional instructions provided as part of MIPS64 (NDA issues, that
will hopefully be solved soon), but rest assured that we have diffs
ready and waiting to add support for those and will submit them as
soon as possible. The goal here is to sync up as close as possible,
so it'll be easier to ship those diffs later. This'll be the last
wide-ranging diff until then (i hope 8-).
the patch below applies in 'src', and as usual the ChangeLogs are
broken out by directory (and hopefully conforming to the proper
ChangeLog format this time -- thanks dje 8-).
Verified to build with host sparc-solaris and targets mips-elf,
mips64-elf, and mips-linux and add no new failures.
chris
=============================================================================
ChangeLog for bfd:
2000-10-13 Chris Demetriou <cgd@sibyte.com>
* archures.c (bfd_mach_mips5_generic,
bfd_mach_mips64_generic): New definitions.
* bfd-in2.h (bfd_mach_mips5_generic, bfd_mach_mips64_generic):
Likewise.
* aoutx.h (NAME(aout,machine_type)): Add cases for
bfd_mach_mips5_generic and bfd_mach_mips64_generic.
* cpu_mips.c (I_mips5_generic, I_mips64_generic): New
definitions.
(arch_info_struct): Add entries for bfd_mach_mips5_generic and
bfd_mach_mips64_generic.
* elf32-mips.c (elf_mips_isa,
_bfd_mips_elf_print_private_bfd_data): Add cases for
E_MIPS_ARCH_5 and E_MIPS_ARCH_64.
(elf_mips_mach): Likewise. Also, add cses for
E_MIPS_MACH_MIPS5_GENERIC and E_MIPS_MACH_MIPS64_GENERIC.
(_bfd_mips_elf_final_write_processing): Add cases for
bfd_mach_mips5_generic and bfd_mach_mips64_generic.
ChangeLog for binutils:
2000-10-13 Chris Demetriou <cgd@sibyte.com>
* readelf.c (get_machine_flags): Add cases for E_MIPS_ARCH_5,
E_MIPS_ARCH_64, E_MIPS_MACH_MIPS5_GENERIC, and
E_MIPS_MACH_MIPS64_GENERIC.
ChangeLog for gas:
2000-10-13 Chris Demetriou <cgd@sibyte.com>
* tc-mips.c (ISA_HAS_64BIT_REGS): Add checks for ISA_MIPS5 and
ISA_MIPS64.
(md_longopts, OPTION_MIPS5, OPTION_MIPS64): Add options for
-mips5 and -mips64.
(OPTION_MIPS32): Tweak option number to fit.
(md_parse_option): Add cases for OPTION_MIPS5 and
OPTION_MIPS64.
(md_show_usage): Mention -mips5 and -mips64 args, and
generic-mips5 and generic-mips64 pseudo-CPUs.
(s_mipsset): Add cases for MIPS 5 and MIPS64.
(mips_cpu_info_table): Add cases for MIPS 5 and MIPS64
ISAs and pseudo-CPUs. Clean up MIPS32 comment.
* doc/as.texinfo: Mention -mips5 and -mips64 options
and their meanings.
* doc/c-mips.texi: Likewise. Also update header
and ".set" usage information.
ChangeLog for include/elf:
2000-10-13 Chris Demetriou <cgd@sibyte.com>
* mips.h (E_MIPS_ARCH_5, E_MIPS_ARCH_64,
E_MIPS_MACH_MIPS5_GENERIC, E_MIPS_MACH_MIPS64_GENERIC): New
definitions.
ChangeLog for include/opcode:
2000-10-13 Chris Demetriou <cgd@sibyte.com>
* mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64,
CPU_MIPS32_GENERIC, CPU_MIPS64_GENERIC): New definitions.
ChangeLog for opcodes:
2000-10-13 Chris Demetriou <cgd@sibyte.com>
* mips-dis.c (set_mips_isa_type): Add cases for
bfd_mach_mips5_generic and bfd_mach_mips64_generic.
* mips-opc.c (I5, I64): New definitions.
diff -rcp ../src.P7_REDO_1/bfd/aoutx.h ./bfd/aoutx.h
*** ../src.P7_REDO_1/bfd/aoutx.h Fri Oct 13 00:02:12 2000
--- ./bfd/aoutx.h Fri Oct 13 14:47:56 2000
*************** NAME(aout,machine_type) (arch, machine,
*** 778,784 ****
--- 778,786 ----
case bfd_mach_mips8000:
case bfd_mach_mips10000:
case bfd_mach_mips16:
+ case bfd_mach_mips5_generic:
case bfd_mach_mips32_generic:
+ case bfd_mach_mips64_generic:
/* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
arch_flags = M_MIPS2;
break;
diff -rcp ../src.P7_REDO_1/bfd/archures.c ./bfd/archures.c
*** ../src.P7_REDO_1/bfd/archures.c Thu Oct 12 23:37:06 2000
--- ./bfd/archures.c Fri Oct 13 14:48:12 2000
*************** DESCRIPTION
*** 127,133 ****
--- 127,135 ----
.#define bfd_mach_mips6000 6000
.#define bfd_mach_mips8000 8000
.#define bfd_mach_mips10000 10000
+ .#define bfd_mach_mips5_generic 115005 {* octal 'M', 005 *}
.#define bfd_mach_mips32_generic 115032 {* octal 'M', 032 *}
+ .#define bfd_mach_mips64_generic 115064 {* octal 'M', 064 *}
.#define bfd_mach_mips16 16
. bfd_arch_i386, {* Intel 386 *}
.#define bfd_mach_i386_i386 0
diff -rcp ../src.P7_REDO_1/bfd/bfd-in2.h ./bfd/bfd-in2.h
*** ../src.P7_REDO_1/bfd/bfd-in2.h Thu Oct 12 23:26:18 2000
--- ./bfd/bfd-in2.h Fri Oct 13 14:49:08 2000
*************** enum bfd_architecture
*** 1397,1403 ****
--- 1397,1405 ----
#define bfd_mach_mips6000 6000
#define bfd_mach_mips8000 8000
#define bfd_mach_mips10000 10000
+ #define bfd_mach_mips5_generic 115005 /* octal for 'M', 005 */
#define bfd_mach_mips32_generic 115032 /* octal for 'M', 032 */
+ #define bfd_mach_mips64_generic 115064 /* octal for 'M', 064 */
#define bfd_mach_mips16 16
bfd_arch_i386, /* Intel 386 */
#define bfd_mach_i386_i386 0
diff -rcp ../src.P7_REDO_1/bfd/cpu-mips.c ./bfd/cpu-mips.c
*** ../src.P7_REDO_1/bfd/cpu-mips.c Thu Oct 12 23:40:50 2000
--- ./bfd/cpu-mips.c Fri Oct 13 14:50:06 2000
*************** I_mips5000,
*** 53,59 ****
--- 53,61 ----
I_mips6000,
I_mips8000,
I_mips10000,
+ I_mips5_generic,
I_mips32_generic,
+ I_mips64_generic,
I_mips16
};
*************** static const bfd_arch_info_type arch_inf
*** 78,84 ****
--- 80,88 ----
N (32, 32, bfd_mach_mips6000, "mips:6000", false, NN(I_mips6000)),
N (64, 64, bfd_mach_mips8000, "mips:8000", false, NN(I_mips8000)),
N (64, 64, bfd_mach_mips10000, "mips:10000", false, NN(I_mips10000)),
+ N (64, 64, bfd_mach_mips5_generic, "mips:generic-mips5", false, NN(I_mips5_generic)),
N (32, 32, bfd_mach_mips32_generic, "mips:generic-mips32", false, NN(I_mips32_generic)),
+ N (64, 64, bfd_mach_mips64_generic, "mips:generic-mips64", false, NN(I_mips64_generic)),
N (64, 64, bfd_mach_mips16, "mips:16", false, 0),
};
diff -rcp ../src.P7_REDO_1/bfd/elf32-mips.c ./bfd/elf32-mips.c
*** ../src.P7_REDO_1/bfd/elf32-mips.c Thu Oct 12 23:27:39 2000
--- ./bfd/elf32-mips.c Fri Oct 13 16:00:35 2000
*************** elf_mips_isa (flags)
*** 1821,1828 ****
--- 1821,1832 ----
return 3;
case E_MIPS_ARCH_4:
return 4;
+ case E_MIPS_ARCH_5:
+ return 5;
case E_MIPS_ARCH_32:
return 32;
+ case E_MIPS_ARCH_64:
+ return 64;
}
return 4;
}
*************** elf_mips_mach (flags)
*** 1850,1858 ****
--- 1854,1868 ----
case E_MIPS_MACH_4650:
return bfd_mach_mips4650;
+ case E_MIPS_MACH_MIPS5_GENERIC:
+ return bfd_mach_mips5_generic;
+
case E_MIPS_MACH_MIPS32_GENERIC:
return bfd_mach_mips32_generic;
+ case E_MIPS_MACH_MIPS64_GENERIC:
+ return bfd_mach_mips64_generic;
+
default:
switch (flags & EF_MIPS_ARCH)
{
*************** elf_mips_mach (flags)
*** 1873,1881 ****
--- 1883,1899 ----
return bfd_mach_mips8000;
break;
+ case E_MIPS_ARCH_5:
+ return bfd_mach_mips5_generic;
+ break;
+
case E_MIPS_ARCH_32:
return bfd_mach_mips32_generic;
break;
+
+ case E_MIPS_ARCH_64:
+ return bfd_mach_mips64_generic;
+ break;
}
}
*************** _bfd_mips_elf_final_write_processing (ab
*** 2357,2365 ****
--- 2375,2391 ----
val = E_MIPS_ARCH_4;
break;
+ case bfd_mach_mips5_generic:
+ val = E_MIPS_ARCH_5 | E_MIPS_MACH_MIPS5_GENERIC;
+ break;
+
case bfd_mach_mips32_generic:
val = E_MIPS_ARCH_32 | E_MIPS_MACH_MIPS32_GENERIC;
break;
+
+ case bfd_mach_mips64_generic:
+ val = E_MIPS_ARCH_64 | E_MIPS_MACH_MIPS64_GENERIC;
+ break;
}
elf_elfheader (abfd)->e_flags &= ~ (EF_MIPS_ARCH | EF_MIPS_MACH);
*************** _bfd_mips_elf_print_private_bfd_data (ab
*** 2667,2674 ****
--- 2693,2704 ----
fprintf (file, _ (" [mips3]"));
else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_4)
fprintf (file, _ (" [mips4]"));
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_5)
+ fprintf (file, _ (" [mips5]"));
else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32)
fprintf (file, _ (" [mips32]"));
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64)
+ fprintf (file, _ (" [mips64]"));
else
fprintf (file, _ (" [unknown ISA]"));
diff -rcp ../src.P7_REDO_1/binutils/readelf.c ./binutils/readelf.c
*** ../src.P7_REDO_1/binutils/readelf.c Thu Oct 12 23:28:19 2000
--- ./binutils/readelf.c Fri Oct 13 14:52:31 2000
*************** get_machine_flags (e_flags, e_machine)
*** 1462,1470 ****
--- 1462,1476 ----
if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_4)
strcat (buf, ", mips4");
+ if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_5)
+ strcat (buf, ", mips5");
+
if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32)
strcat (buf, ", mips32");
+ if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64)
+ strcat (buf, ", mips64");
+
switch ((e_flags & EF_MIPS_MACH))
{
case E_MIPS_MACH_3900: strcat (buf, ", 3900"); break;
*************** get_machine_flags (e_flags, e_machine)
*** 1472,1479 ****
--- 1478,1489 ----
case E_MIPS_MACH_4100: strcat (buf, ", 4100"); break;
case E_MIPS_MACH_4650: strcat (buf, ", 4650"); break;
case E_MIPS_MACH_4111: strcat (buf, ", 4111"); break;
+ case E_MIPS_MACH_MIPS5_GENERIC:
+ strcat (buf, ", generic-mips5"); break;
case E_MIPS_MACH_MIPS32_GENERIC:
strcat (buf, ", generic-mips32"); break;
+ case E_MIPS_MACH_MIPS64_GENERIC:
+ strcat (buf, ", generic-mips64"); break;
}
break;
diff -rcp ../src.P7_REDO_1/gas/config/tc-mips.c ./gas/config/tc-mips.c
*** ../src.P7_REDO_1/gas/config/tc-mips.c Thu Oct 12 23:48:35 2000
--- ./gas/config/tc-mips.c Fri Oct 13 15:43:57 2000
*************** static int mips_gp32 = 0;
*** 238,243 ****
--- 238,245 ----
#define ISA_HAS_64BIT_REGS(ISA) ( \
(ISA) == ISA_MIPS3 \
|| (ISA) == ISA_MIPS4 \
+ || (ISA) == ISA_MIPS5 \
+ || (ISA) == ISA_MIPS64 \
)
/* Whether the processor uses hardware interlocks to protect
*************** struct option md_longopts[] =
*** 8882,8889 ****
{"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
#define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27)
{"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
! #define OPTION_MIPS32 (OPTION_MD_BASE + 28)
{"mips32", no_argument, NULL, OPTION_MIPS32},
#ifdef OBJ_ELF
#define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
--- 8884,8895 ----
{"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
#define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27)
{"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
! #define OPTION_MIPS5 (OPTION_MD_BASE + 28)
! {"mips5", no_argument, NULL, OPTION_MIPS5},
! #define OPTION_MIPS32 (OPTION_MD_BASE + 29)
{"mips32", no_argument, NULL, OPTION_MIPS32},
+ #define OPTION_MIPS64 (OPTION_MD_BASE + 30)
+ {"mips64", no_argument, NULL, OPTION_MIPS64},
#ifdef OBJ_ELF
#define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
*************** md_parse_option (c, arg)
*** 8969,8978 ****
--- 8975,8992 ----
mips_opts.isa = ISA_MIPS4;
break;
+ case OPTION_MIPS5:
+ mips_opts.isa = ISA_MIPS5;
+ break;
+
case OPTION_MIPS32:
mips_opts.isa = ISA_MIPS32;
break;
+ case OPTION_MIPS64:
+ mips_opts.isa = ISA_MIPS64;
+ break;
+
case OPTION_MCPU:
{
*************** MIPS options:\n\
*** 9207,9213 ****
--- 9221,9229 ----
-mips2 generate MIPS ISA II instructions\n\
-mips3 generate MIPS ISA III instructions\n\
-mips4 generate MIPS ISA IV instructions\n\
+ -mips5 generate MIPS ISA V instructions\n\
-mips32 generate MIPS32 ISA instructions\n\
+ -mips64 generate MIPS64 ISA instructions\n\
-mcpu=CPU generate code for CPU, where CPU is one of:\n"));
first = 1;
*************** MIPS options:\n\
*** 9227,9233 ****
--- 9243,9251 ----
show (stream, "6000", &column, &first);
show (stream, "8000", &column, &first);
show (stream, "10000", &column, &first);
+ show (stream, "generic-mips5", &column, &first);
show (stream, "generic-mips32", &column, &first);
+ show (stream, "generic-mips64", &column, &first);
fputc ('\n', stream);
fprintf (stream, _("\
*************** s_mipsset (x)
*** 10250,10258 ****
--- 10268,10282 ----
case 4:
mips_opts.isa = ISA_MIPS4;
break;
+ case 5:
+ mips_opts.isa = ISA_MIPS5;
+ break;
case 32:
mips_opts.isa = ISA_MIPS32;
break;
+ case 64:
+ mips_opts.isa = ISA_MIPS64;
+ break;
default:
as_bad (_("unknown ISA level"));
break;
*************** static const struct mips_cpu_info mips_c
*** 11927,11937 ****
--- 11951,11968 ----
/* MIPS4 ISA */
{ "MIPS4", 1, ISA_MIPS4, CPU_R8000, },
+ /* MIPS5 ISA */
+ { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5_GENERIC, },
+
/* MIPS32 ISA */
{ "MIPS32", 1, ISA_MIPS32, CPU_MIPS32_GENERIC, },
/* XXX for now, MIPS64 -> MIPS3 because of history */
+ #if 1
{ "MIPS64", 1, ISA_MIPS3, CPU_R4000 }, /* XXX! */
+ #else
+ { "MIPS64", 1, ISA_MIPS64, CPU_MIPS64_GENERIC, },
+ #endif
/* R2000 CPU */
{ "R2000", 0, ISA_MIPS1, CPU_R2000, },
*************** static const struct mips_cpu_info mips_c
*** 12024,12030 ****
{ "r5k", 0, ISA_MIPS4, CPU_R5000, },
{ "r7000", 0, ISA_MIPS4, CPU_R5000, },
! /* MIPS32 4K CPU */
{ "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32_GENERIC, },
{ "4kc", 0, ISA_MIPS32, CPU_MIPS32_GENERIC, },
{ "4km", 0, ISA_MIPS32, CPU_MIPS32_GENERIC, },
--- 12055,12064 ----
{ "r5k", 0, ISA_MIPS4, CPU_R5000, },
{ "r7000", 0, ISA_MIPS4, CPU_R5000, },
! /* Generic MIPS5 CPU */
! { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5_GENERIC, },
!
! /* Generic MIPS32 CPU */
{ "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32_GENERIC, },
{ "4kc", 0, ISA_MIPS32, CPU_MIPS32_GENERIC, },
{ "4km", 0, ISA_MIPS32, CPU_MIPS32_GENERIC, },
*************** static const struct mips_cpu_info mips_c
*** 12033,12038 ****
--- 12067,12075 ----
{ "mips32-4kc", 0, ISA_MIPS32, CPU_MIPS32_GENERIC, },
{ "mips32-4km", 0, ISA_MIPS32, CPU_MIPS32_GENERIC, },
{ "mips32-4kp", 0, ISA_MIPS32, CPU_MIPS32_GENERIC, },
+
+ /* Generic MIPS64 CPU */
+ { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64_GENERIC, },
/* End marker. */
{ NULL, 0, 0, 0, },
diff -rcp ../src.P7_REDO_1/gas/doc/as.texinfo ./gas/doc/as.texinfo
*** ../src.P7_REDO_1/gas/doc/as.texinfo Thu Oct 12 23:30:16 2000
--- ./gas/doc/as.texinfo Fri Oct 13 15:51:24 2000
*************** Here is a brief summary of how to invoke
*** 278,284 ****
@end ifset
@ifset MIPS
[ -nocpp ] [ -EL ] [ -EB ] [ -G @var{num} ] [ -mcpu=@var{CPU} ]
! [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -mips4 ] [ -mips32 ]
[ -m4650 ] [ -no-m4650 ]
[ --trap ] [ --break ]
[ --emulation=@var{name} ]
--- 278,285 ----
@end ifset
@ifset MIPS
[ -nocpp ] [ -EL ] [ -EB ] [ -G @var{num} ] [ -mcpu=@var{CPU} ]
! [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -mips4 ] [ -mips5 ]
! [ -mips32 ] [ -mips64 ]
[ -m4650 ] [ -no-m4650 ]
[ --trap ] [ --break ]
[ --emulation=@var{name} ]
*************** Generate ``little endian'' format output
*** 669,679 ****
@itemx -mips2
@itemx -mips3
@itemx -mips4
@itemx -mips32
Generate code for a particular MIPS Instruction Set Architecture level.
@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the @sc{r4000}
! processor, @samp{-mips32} to a generic @sc{MIPS32} processor.
@item -m4650
@itemx -no-m4650
--- 670,685 ----
@itemx -mips2
@itemx -mips3
@itemx -mips4
+ @itemx -mips5
@itemx -mips32
+ @itemx -mips64
Generate code for a particular MIPS Instruction Set Architecture level.
@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the @sc{r4000}
! processor.
! @samp{-mips5}, @samp{-mips32}, and @samp{-mips64} correspond
! to generic @sc{MIPS V}, @sc{MIPS32}, and @sc{MIPS64} ISA
! processors, respectively.
@item -m4650
@itemx -no-m4650
diff -rcp ../src.P7_REDO_1/gas/doc/c-mips.texi ./gas/doc/c-mips.texi
*** ../src.P7_REDO_1/gas/doc/c-mips.texi Thu Oct 12 23:30:36 2000
--- ./gas/doc/c-mips.texi Fri Oct 13 15:52:44 2000
***************
*** 13,19 ****
@cindex MIPS processor
@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
! different @sc{mips} processors, and MIPS ISA levels I through IV. For
information about the @sc{mips} instruction set, see @cite{MIPS RISC
Architecture}, by Kane and Heindrich (Prentice-Hall). For an overview
of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language
--- 13,20 ----
@cindex MIPS processor
@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
! different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
! and MIPS64. For
information about the @sc{mips} instruction set, see @cite{MIPS RISC
Architecture}, by Kane and Heindrich (Prentice-Hall). For an overview
of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language
*************** to select big-endian output, and @samp{-
*** 60,72 ****
@itemx -mips2
@itemx -mips3
@itemx -mips4
@itemx -mips32
Generate code for a particular MIPS Instruction Set Architecture level.
@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
@sc{r4000} processor, @samp{-mips4} to the @sc{r8000} and
! @sc{r10000} processors, and @samp{-mips32} to a generic @sc(MIPS32)
! processors. You can also switch instruction sets during the
assembly; see @ref{MIPS ISA, Directives to override the ISA level}.
@item -mgp32
--- 61,78 ----
@itemx -mips2
@itemx -mips3
@itemx -mips4
+ @itemx -mips5
@itemx -mips32
+ @itemx -mips64
Generate code for a particular MIPS Instruction Set Architecture level.
@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
@sc{r4000} processor, @samp{-mips4} to the @sc{r8000} and
! @sc{r10000} processors.
! @samp{-mips5}, @samp{-mips32}, and @samp{-mips64} correspond
! to generic @sc{MIPS V}, @sc{MIPS32}, and @sc{MIPS64} ISA
! processors, respectively.
! You can also switch instruction sets during the
assembly; see @ref{MIPS ISA, Directives to override the ISA level}.
@item -mgp32
*************** assembly language programmers!
*** 241,248 ****
@kindex @code{.set mips@var{n}}
@sc{gnu} @code{@value{AS}} supports an additional directive to change
the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
! mips@var{n}}. @var{n} should be a number from 0 to 4, or 32. The values 1
! to 4 and 32 make the assembler accept instructions for the corresponding
@sc{isa} level, from that point on in the assembly. @code{.set
mips@var{n}} affects not only which instructions are permitted, but also
how certain macros are expanded. @code{.set mips0} restores the
--- 247,255 ----
@kindex @code{.set mips@var{n}}
@sc{gnu} @code{@value{AS}} supports an additional directive to change
the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
! mips@var{n}}. @var{n} should be a number from 0 to 5, or 32 or 64.
! The values 1 to 5, 32, and 64 make the assembler accept instructions
! for the corresponding
@sc{isa} level, from that point on in the assembly. @code{.set
mips@var{n}} affects not only which instructions are permitted, but also
how certain macros are expanded. @code{.set mips0} restores the
diff -rcp ../src.P7_REDO_1/include/elf/mips.h ./include/elf/mips.h
*** ../src.P7_REDO_1/include/elf/mips.h Thu Oct 12 23:38:25 2000
--- ./include/elf/mips.h Fri Oct 13 14:59:48 2000
*************** END_RELOC_NUMBERS (R_MIPS_maxext)
*** 121,129 ****
--- 121,135 ----
/* -mips4 code. */
#define E_MIPS_ARCH_4 0x30000000
+ /* -mips5 code. */
+ #define E_MIPS_ARCH_5 0x40000000
+
/* -mips32 code. */
#define E_MIPS_ARCH_32 0x50000000
+ /* -mips64 code. */
+ #define E_MIPS_ARCH_64 0x60000000
+
/* The ABI of the file. Also see EF_MIPS_ABI2 above. */
#define EF_MIPS_ABI 0x0000F000
*************** END_RELOC_NUMBERS (R_MIPS_maxext)
*** 157,162 ****
--- 163,170 ----
#define E_MIPS_MACH_4650 0x00850000
#define E_MIPS_MACH_4111 0x00880000
#define E_MIPS_MACH_MIPS32_GENERIC 0x00890000
+ #define E_MIPS_MACH_MIPS5_GENERIC 0x008a0000
+ #define E_MIPS_MACH_MIPS64_GENERIC 0x008b0000
/* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these
diff -rcp ../src.P7_REDO_1/include/opcode/mips.h ./include/opcode/mips.h
*** ../src.P7_REDO_1/include/opcode/mips.h Thu Oct 12 23:43:14 2000
--- ./include/opcode/mips.h Fri Oct 13 15:00:57 2000
*************** struct mips_opcode
*** 314,319 ****
--- 314,320 ----
#define INSN_ISA4 0x00000080
#define INSN_ISA5 0x00000100
#define INSN_ISA32 0x00000200
+ #define INSN_ISA64 0x00000400
/* Chip specific instructions. These are bitmasks. */
/* MIPS R4650 instruction. */
*************** struct mips_opcode
*** 333,339 ****
--- 334,342 ----
#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
+ #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
+ #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
/* CPU defines, use instead of hardcoding processor number. Keep this
*************** struct mips_opcode
*** 355,361 ****
--- 358,366 ----
#define CPU_R8000 8000
#define CPU_R10000 10000
#define CPU_MIPS16 16
+ #define CPU_MIPS5_GENERIC 115005 /* octal 'M', 005 */
#define CPU_MIPS32_GENERIC 115032 /* octal 'M', 032 */
+ #define CPU_MIPS64_GENERIC 115064 /* octal 'M', 064 */
/* Test for membership in an ISA including chip specific ISAs.
INSN is pointer to an element of the opcode table; ISA is the
diff -rcp ../src.P7_REDO_1/opcodes/mips-dis.c ./opcodes/mips-dis.c
*** ../src.P7_REDO_1/opcodes/mips-dis.c Thu Oct 12 23:32:32 2000
--- ./opcodes/mips-dis.c Fri Oct 13 15:01:41 2000
*************** set_mips_isa_type (mach, isa, cputype)
*** 361,366 ****
--- 361,374 ----
target_processor = CPU_MIPS16;
mips_isa = ISA_MIPS3;
break;
+ case bfd_mach_mips5_generic:
+ target_processor = CPU_MIPS5_GENERIC;
+ mips_isa = ISA_MIPS5;
+ break;
+ case bfd_mach_mips64_generic:
+ target_processor = CPU_MIPS64_GENERIC;
+ mips_isa = ISA_MIPS64;
+ break;
default:
target_processor = CPU_R3000;
mips_isa = ISA_MIPS3;
diff -rcp ../src.P7_REDO_1/opcodes/mips-opc.c ./opcodes/mips-opc.c
*** ../src.P7_REDO_1/opcodes/mips-opc.c Fri Oct 13 10:21:14 2000
--- ./opcodes/mips-opc.c Fri Oct 13 15:02:26 2000
*************** Software Foundation, 59 Temple Place - S
*** 76,84 ****
#define I2 INSN_ISA2
#define I3 INSN_ISA3
#define I4 INSN_ISA4
#define I32 INSN_ISA32
#define P4 I32 /* XXX temporary */
! #define I5 INSN_ISA5
#define P3 INSN_4650
#define L1 INSN_4010
#define V1 INSN_4100
--- 76,87 ----
#define I2 INSN_ISA2
#define I3 INSN_ISA3
#define I4 INSN_ISA4
+ #define I5 INSN_ISA5
#define I32 INSN_ISA32
+ #define I64 INSN_ISA64
+
#define P4 I32 /* XXX temporary */
!
#define P3 INSN_4650
#define L1 INSN_4010
#define V1 INSN_4100