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[updated patch] Making MIPS32 a real ISA, and ISA/CPU name cleanup.
- To: binutils at sourceware dot cygnus dot com
- Subject: [updated patch] Making MIPS32 a real ISA, and ISA/CPU name cleanup.
- From: cgd at sibyte dot com (Chris G. Demetriou)
- Date: 16 Oct 2000 16:06:14 -0700
This patch is a rework of the patches presented in the thread with
subject:
[patch] MIPS32 is a real ISA, and MIPS ISA/CPU name/constant cleanup.
and also incorporates the changes in the post titled:
[patch] MIPS opcodes P4 -> I32 cleanup.
It applies over several of my previous patches; see
http://sources.redhat.com/ml/binutils/2000-10/msg00168.html for more
details. (This replaces 7 and 9, and needs 1-6 applied first. A new
version of 8 will be forthcoming.)
To reiterate the purpose of this patch:
The previous patch which integrated MIPS32 ISA support did so as a
fake-CPU extension to an earlier MIPS ISA. In fact, MIPS32 is an ISA
unto itself, and deserves to be treated as such.
So, this code converts MIPS32 to be a real ISA. Since MIPS32 is or is
going to be a 'standard' ISA, the notion of a 'vanilla' CPU which
implements exactly MIPS32 is quite reasonable. Therefore, the default
CPU for this ISA is a dummy 'generic' CPU, and no special machine is
noted in the MIPS ELF machine field in the flags.
This code preserves the original implementation's special handling of
the MIPS32 4K family of CPUs, though changes the names around a bit
(keeping backward compatibility) to avoid confusion with earlier MIPS
CPUs (specifically, the R4000, commonly known as the 4K 8-).
Because of the nature of MIPS32 (it breaks the numerical ordering
relationship used by earlier MIPS ISAs), i've changed the way ISAs are
numbered in GAS and the opcodes table.
As a side effect, it puts the CPU and ISA name lookup into a table and
common set of functions, eliminating some grotty option parsing code.
ChangeLog below broken out by directory, patch below and applies in
'src'.
chris
=============================================================================
for bfd/ChangeLog:
2000-10-16 Chris Demetriou <cgd@sibyte.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mips32 and
bfd_mach_mips32_4k. Update FIXME comment.
* archures.c (bfd_mach_mips32): New constant.
(bfd_mach_mips4K, bfd_mach_mips32_4k) Rename the former to
the latter, renumber it.
* bfd-in2.h (bfd_mach_mips32): New constant.
(bfd_mach_mips4K, bfd_mach_mips32_4k) Rename the former to
the latter, renumber it.
* cpu-mips.c (I_mips32): New constant.
(I_mips4K, I_mips32_4k): Rename the former to the latter.
(arch_info_struct): Add bfd_mach_mips32 entry, replace
bfd_mach_mips4K entry with bfd_mach_mips32_4k entry.
* elf32-mips.c (elf_mips_isa): Add E_MIPS_ARCH_32 case.
(elf_mips_mach): Likewise. Also, replace E_MIPS_MACH_MIPS32
with E_MIPS_MACH_MIPS32_4K.
(_bfd_mips_elf_final_write_processing): Replace
bfd_mach_mips4K with bfd_mach_mips32_4k case, add
bfd_mach_mips32 case.
(_bfd_mips_elf_merge_private_bfd_data): Generalize ISA mixing
comparison with support for MIPS32.
(_bfd_mips_elf_print_private_bfd_data): Print ISA name for
MIPS32.
for binutils/ChangeLog:
2000-10-16 Chris Demetriou <cgd@sibyte.com>
* readelf.c (get_machine_flags): Recognize MIPS32 ISA in
EF_MIPS_ARCH. Replace use of E_MIPS_MACH_MIPS32 with
E_MIPS_MACH_MIPS32_4K and adjust printed CPU name similarly.
for gas/ChangeLog:
2000-10-13 Chris Demetriou <cgd@sibyte.com>
* config/tc-mips.c (mips_set_options): Use ISA_UNKNOWN rather than
-1, and update comment.
(file_mips_isa): Likewise.
(mips_cpu): Use CPU_UNKNOWN rather than -1, and update comment.
(ISA_HAS_COPROC_DELAYS, ISA_HAS_64BIT_REGS, gpr_interlocks): Use
ISA_* constants rather than hard-coded numbers.
(mips_cpu_info): New structure.
(mips_cpu_info_table): New table describing CPU and ISA names
and numbers.
(mips_cpu_info_from_name, mips_cpu_info_from_isa,
mips_cpu_info_from_cpu): New functions.
(mips_isa_to_str): New function to get string for ISA name.
(mips_cpu_to_str): Convert to use mips_cpu_info_from_cpu, and
return const char *.
(md_begin): Redo CPU and ISA selection logic, using
mips_cpu_info_from_*. Convert to use ISA_* constants rather
than hard-coded numbers.
(append_insn, mips_emit_delays, macro, macro2): Convert to use
ISA_* constants rather than hard-coded numbers.
(mips_ip): Convert to use mips_isa_to_str to get ISA name.
(md_longopts): Delete OPTION_NO_MIPS32.
(md_parse_option): Convert to use ISA_* constants rather than
hard-coded numbers. Make OPTIONS_MIPS32 case treat MIPS32
as an ISA. Delete OPTION_NO_MIPS32 case. Convert OPTION_MCPU
to use strcasecmp to recognize "default" and to use
mips_cpu_info_from_name to get CPU numbers from argument.
(md_show_usage): Move -mips32 so it's with the rest of the ISA
flags. Change 4Kc, 4Kp and 4Km CPU entries to just be
mips32-4k.
(s_mipsset): Accept ISA value 32.
* doc/as.texinfo: Clean up MIPS options summary slightly,
remove -no-mips32. Add note about -mips4 and -mips32
specifying those ISA levels. Delete -mips32 and -no-mips32
cpu flag descriptions.
* doc/c-mips.texi: Add -mips32 to list of ISA switches. Clean
up the supported CPU switch list, and replace 4Kc, 4Km, and
4Kp entries with a single mips32-4k entry. Note that you can
use ".set mips32".
for include/elf/ChangeLog:
2000-10-16 Chris Demetriou <cgd@sibyte.com>
* mips.h (E_MIPS_ARCH_32): New constant.
(E_MIPS_MACH_MIPS32, E_MIPS_MACH_MIPS32_4K): Replace the
former with the latter.
for include/opcode/ChangeLog:
2000-10-13 Chris Demetriou <cgd@sibyte.com>
* mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4,
INSN_ISA5): Renumber, redefine to mean the ISA at which the
instruction was added.
(INSN_ISA32): New constant.
(INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32):
Renumber to avoid new and/or renumbered INSN_* constants.
(INSN_MIPS32): Delete.
(ISA_UNKNOWN): New constant to indicate unknown ISA.
(ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5,
ISA_MIPS32): New constants, defined to be the mask of INSN_*
constants available at that ISA level.
(CPU_UNKNOWN): New constant to indicate unknown CPU.
(CPU_4K, CPU_MIPS32_4K): Rename the former to the latter,
define it with a unique value.
(OPCODE_IS_MEMBER): Update for new ISA membership-related
constant meanings.
for opcodes/ChangeLog:
2000-10-13 Chris Demetriou <cgd@sibyte.com>
* mips-dis.c (set_mips_isa_type): Update to use
CPU_UNKNOWN and ISA_* constants. Add bfd_mach_mips32 case.
Replace bfd_mach_mips4K with bfd_mach_mips32_4k case.
* mips-opc.c (I32): New constant for instructions added in
MIPS32.
(P4): Delete.
(mips_builtin_opcodes) Replace all uses of P4 with I32.
diff -rcp ../src.P06/bfd/aoutx.h ./bfd/aoutx.h
*** ../src.P06/bfd/aoutx.h Thu Jul 20 09:21:06 2000
--- ./bfd/aoutx.h Sat Oct 14 23:16:43 2000
*************** NAME(aout,machine_type) (arch, machine,
*** 778,784 ****
case bfd_mach_mips8000:
case bfd_mach_mips10000:
case bfd_mach_mips16:
! /* FIXME: These should be MIPS3 or MIPS4. */
arch_flags = M_MIPS2;
break;
default:
--- 778,786 ----
case bfd_mach_mips8000:
case bfd_mach_mips10000:
case bfd_mach_mips16:
! case bfd_mach_mips32:
! case bfd_mach_mips32_4k:
! /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
arch_flags = M_MIPS2;
break;
default:
diff -rcp ../src.P06/bfd/archures.c ./bfd/archures.c
*** ../src.P06/bfd/archures.c Wed Sep 13 18:47:31 2000
--- ./bfd/archures.c Sat Oct 14 23:18:56 2000
*************** DESCRIPTION
*** 127,134 ****
.#define bfd_mach_mips6000 6000
.#define bfd_mach_mips8000 8000
.#define bfd_mach_mips10000 10000
- .#define bfd_mach_mips4K 32
.#define bfd_mach_mips16 16
. bfd_arch_i386, {* Intel 386 *}
.#define bfd_mach_i386_i386 0
.#define bfd_mach_i386_i8086 1
--- 127,135 ----
.#define bfd_mach_mips6000 6000
.#define bfd_mach_mips8000 8000
.#define bfd_mach_mips10000 10000
.#define bfd_mach_mips16 16
+ .#define bfd_mach_mips32 32
+ .#define bfd_mach_mips32_4k 3204113 {* 32, 04, octal 'K' *}
. bfd_arch_i386, {* Intel 386 *}
.#define bfd_mach_i386_i386 0
.#define bfd_mach_i386_i8086 1
diff -rcp ../src.P06/bfd/bfd-in2.h ./bfd/bfd-in2.h
*** ../src.P06/bfd/bfd-in2.h Wed Oct 11 20:44:50 2000
--- ./bfd/bfd-in2.h Sat Oct 14 23:31:40 2000
*************** enum bfd_architecture
*** 1397,1404 ****
#define bfd_mach_mips6000 6000
#define bfd_mach_mips8000 8000
#define bfd_mach_mips10000 10000
- #define bfd_mach_mips4K 32
#define bfd_mach_mips16 16
bfd_arch_i386, /* Intel 386 */
#define bfd_mach_i386_i386 0
#define bfd_mach_i386_i8086 1
--- 1397,1405 ----
#define bfd_mach_mips6000 6000
#define bfd_mach_mips8000 8000
#define bfd_mach_mips10000 10000
#define bfd_mach_mips16 16
+ #define bfd_mach_mips32 32
+ #define bfd_mach_mips32_4k 3204113 /* 32, 04, octal 'K' */
bfd_arch_i386, /* Intel 386 */
#define bfd_mach_i386_i386 0
#define bfd_mach_i386_i8086 1
diff -rcp ../src.P06/bfd/cpu-mips.c ./bfd/cpu-mips.c
*** ../src.P06/bfd/cpu-mips.c Wed Sep 13 18:47:31 2000
--- ./bfd/cpu-mips.c Mon Oct 16 14:49:19 2000
*************** I_mips5000,
*** 53,60 ****
I_mips6000,
I_mips8000,
I_mips10000,
! I_mips4K,
! I_mips16
};
--- 53,61 ----
I_mips6000,
I_mips8000,
I_mips10000,
! I_mips16,
! I_mips32,
! I_mips32_4k,
};
*************** static const bfd_arch_info_type arch_inf
*** 76,83 ****
N (32, 32, bfd_mach_mips6000, "mips:6000", false, NN(I_mips6000)),
N (64, 64, bfd_mach_mips8000, "mips:8000", false, NN(I_mips8000)),
N (64, 64, bfd_mach_mips10000, "mips:10000", false, NN(I_mips10000)),
! N (32, 32, bfd_mach_mips4K, "mips:4K", false, NN(I_mips4K)),
! N (64, 64, bfd_mach_mips16, "mips:16", false, 0),
};
/* The default architecture is mips:3000, but with a machine number of
--- 77,85 ----
N (32, 32, bfd_mach_mips6000, "mips:6000", false, NN(I_mips6000)),
N (64, 64, bfd_mach_mips8000, "mips:8000", false, NN(I_mips8000)),
N (64, 64, bfd_mach_mips10000, "mips:10000", false, NN(I_mips10000)),
! N (64, 64, bfd_mach_mips16, "mips:16", false, NN(I_mips16)),
! N (32, 32, bfd_mach_mips32, "mips:mips32", false, NN(I_mips32)),
! N (32, 32, bfd_mach_mips32_4k, "mips:mips32-4k", false, 0),
};
/* The default architecture is mips:3000, but with a machine number of
diff -rcp ../src.P06/bfd/elf32-mips.c ./bfd/elf32-mips.c
*** ../src.P06/bfd/elf32-mips.c Fri Oct 13 21:05:23 2000
--- ./bfd/elf32-mips.c Sat Oct 14 23:22:41 2000
*************** elf_mips_isa (flags)
*** 1821,1826 ****
--- 1821,1828 ----
return 3;
case E_MIPS_ARCH_4:
return 4;
+ case E_MIPS_ARCH_32:
+ return 32;
}
return 4;
}
*************** elf_mips_mach (flags)
*** 1848,1855 ****
case E_MIPS_MACH_4650:
return bfd_mach_mips4650;
! case E_MIPS_MACH_MIPS32:
! return bfd_mach_mips4K;
default:
switch (flags & EF_MIPS_ARCH)
--- 1850,1857 ----
case E_MIPS_MACH_4650:
return bfd_mach_mips4650;
! case E_MIPS_MACH_MIPS32_4K:
! return bfd_mach_mips32_4k;
default:
switch (flags & EF_MIPS_ARCH)
*************** elf_mips_mach (flags)
*** 1870,1875 ****
--- 1872,1881 ----
case E_MIPS_ARCH_4:
return bfd_mach_mips8000;
break;
+
+ case E_MIPS_ARCH_32:
+ return bfd_mach_mips32;
+ break;
}
}
*************** _bfd_mips_elf_final_write_processing (ab
*** 2351,2358 ****
val = E_MIPS_ARCH_4;
break;
! case bfd_mach_mips4K:
! val = E_MIPS_ARCH_2 | E_MIPS_MACH_MIPS32;
break;
}
--- 2357,2368 ----
val = E_MIPS_ARCH_4;
break;
! case bfd_mach_mips32:
! val = E_MIPS_ARCH_32;
! break;
!
! case bfd_mach_mips32_4k:
! val = E_MIPS_ARCH_32 | E_MIPS_MACH_MIPS32_4K;
break;
}
*************** _bfd_mips_elf_merge_private_bfd_data (ib
*** 2552,2564 ****
|| new_mach == old_mach
)
{
! /* Don't warn about mixing -mips1 and -mips2 code, or mixing -mips3
! and -mips4 code. They will normally use the same data sizes and
! calling conventions. */
!
! if ((new_isa == 1 || new_isa == 2)
! ? (old_isa != 1 && old_isa != 2)
! : (old_isa == 1 || old_isa == 2))
{
(*_bfd_error_handler)
(_("%s: ISA mismatch (-mips%d) with previous modules (-mips%d)"),
--- 2562,2573 ----
|| new_mach == old_mach
)
{
! /* Don't warn about mixing code using 32-bit ISAs, or mixing code
! using 64-bit ISAs. They will normally use the same data sizes
! and calling conventions. */
!
! if (((new_isa == 1 || new_isa == 2 || new_isa == 32)
! ^ (old_isa == 1 || old_isa == 2 || old_isa == 32)) != 0)
{
(*_bfd_error_handler)
(_("%s: ISA mismatch (-mips%d) with previous modules (-mips%d)"),
*************** _bfd_mips_elf_print_private_bfd_data (ab
*** 2662,2667 ****
--- 2671,2678 ----
fprintf (file, _ (" [mips3]"));
else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_4)
fprintf (file, _ (" [mips4]"));
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32)
+ fprintf (file, _ (" [mips32]"));
else
fprintf (file, _ (" [unknown ISA]"));
diff -rcp ../src.P06/binutils/readelf.c ./binutils/readelf.c
*** ../src.P06/binutils/readelf.c Wed Sep 13 18:47:33 2000
--- ./binutils/readelf.c Sat Oct 14 23:17:04 2000
*************** get_machine_flags (e_flags, e_machine)
*** 1462,1467 ****
--- 1462,1470 ----
if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_4)
strcat (buf, ", mips4");
+ if ((e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32)
+ strcat (buf, ", mips32");
+
switch ((e_flags & EF_MIPS_MACH))
{
case E_MIPS_MACH_3900: strcat (buf, ", 3900"); break;
*************** get_machine_flags (e_flags, e_machine)
*** 1469,1475 ****
case E_MIPS_MACH_4100: strcat (buf, ", 4100"); break;
case E_MIPS_MACH_4650: strcat (buf, ", 4650"); break;
case E_MIPS_MACH_4111: strcat (buf, ", 4111"); break;
! case E_MIPS_MACH_MIPS32: strcat (buf, ", mips32"); break;
}
break;
--- 1472,1479 ----
case E_MIPS_MACH_4100: strcat (buf, ", 4100"); break;
case E_MIPS_MACH_4650: strcat (buf, ", 4650"); break;
case E_MIPS_MACH_4111: strcat (buf, ", 4111"); break;
! case E_MIPS_MACH_MIPS32_4K:
! strcat (buf, ", mips32-4k"); break;
}
break;
diff -rcp ../src.P06/gas/config/tc-mips.c ./gas/config/tc-mips.c
*** ../src.P06/gas/config/tc-mips.c Sat Oct 14 22:51:51 2000
--- ./gas/config/tc-mips.c Mon Oct 16 14:37:22 2000
*************** struct mips_set_options
*** 187,196 ****
};
/* This is the struct we use to hold the current set of options. Note
! that we must set the isa and mips16 fields to -1 to indicate that
! they have not been initialized. */
! static struct mips_set_options mips_opts = { -1, -1, 0, 0, 0, 0, 0, 0 };
/* These variables are filled in with the masks of registers used.
The object format code reads them and puts them in the appropriate
--- 187,199 ----
};
/* This is the struct we use to hold the current set of options. Note
! that we must set the isa field to ISA_UNKNOWN and the mips16 field to
! -1 to indicate that they have not been initialized. */
! static struct mips_set_options mips_opts =
! {
! ISA_UNKNOWN, -1, 0, 0, 0, 0, 0, 0
! };
/* These variables are filled in with the masks of registers used.
The object format code reads them and puts them in the appropriate
*************** unsigned long mips_gprmask;
*** 199,208 ****
unsigned long mips_cprmask[4];
/* MIPS ISA we are using for this output file. */
! static int file_mips_isa;
! /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
! static int mips_cpu = -1;
/* The argument of the -mabi= flag. */
static char* mips_abi_string = 0;
--- 202,211 ----
unsigned long mips_cprmask[4];
/* MIPS ISA we are using for this output file. */
! static int file_mips_isa = ISA_UNKNOWN;
! /* The CPU type we are using for this output file. */
! static int mips_cpu = CPU_UNKNOWN;
/* The argument of the -mabi= flag. */
static char* mips_abi_string = 0;
*************** static int mips_gp32 = 0;
*** 226,240 ****
also assume that ISAs which don't have delays for these insns, don't
have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
#define ISA_HAS_COPROC_DELAYS(ISA) ( \
! (ISA) == 1 \
! || (ISA) == 2 \
! || (ISA) == 3 \
)
/* Return true if ISA supports 64 bit gp register instructions. */
#define ISA_HAS_64BIT_REGS(ISA) ( \
! (ISA) == 3 \
! || (ISA) == 4 \
)
/* Whether the processor uses hardware interlocks to protect
--- 229,243 ----
also assume that ISAs which don't have delays for these insns, don't
have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
#define ISA_HAS_COPROC_DELAYS(ISA) ( \
! (ISA) == ISA_MIPS1 \
! || (ISA) == ISA_MIPS2 \
! || (ISA) == ISA_MIPS3 \
)
/* Return true if ISA supports 64 bit gp register instructions. */
#define ISA_HAS_64BIT_REGS(ISA) ( \
! (ISA) == ISA_MIPS3 \
! || (ISA) == ISA_MIPS4 \
)
/* Whether the processor uses hardware interlocks to protect
*************** static int mips_gp32 = 0;
*** 270,276 ****
/* Whether the processor uses hardware interlocks to protect reads
from the GPRs, and thus does not require nops to be inserted. */
#define gpr_interlocks \
! (mips_opts.isa != 1 \
|| mips_cpu == CPU_R3900)
/* As with other "interlocks" this is used by hardware that has FP
--- 273,279 ----
/* Whether the processor uses hardware interlocks to protect reads
from the GPRs, and thus does not require nops to be inserted. */
#define gpr_interlocks \
! (mips_opts.isa != ISA_MIPS1 \
|| mips_cpu == CPU_R3900)
/* As with other "interlocks" this is used by hardware that has FP
*************** static void s_mips_stab PARAMS ((int));
*** 706,715 ****
static void s_mips_weakext PARAMS ((int));
static void s_file PARAMS ((int));
static int mips16_extended_frag PARAMS ((fragS *, asection *, long));
! static char *mips_cpu_to_str PARAMS ((int));
static int validate_mips_insn PARAMS ((const struct mips_opcode *));
/* Pseudo-op table.
The following pseudo-ops from the Kane and Heinrich MIPS book
--- 709,735 ----
static void s_mips_weakext PARAMS ((int));
static void s_file PARAMS ((int));
static int mips16_extended_frag PARAMS ((fragS *, asection *, long));
! static const char *mips_isa_to_str PARAMS ((int));
! static const char *mips_cpu_to_str PARAMS ((int));
static int validate_mips_insn PARAMS ((const struct mips_opcode *));
+ /* Table and functions used to map between CPU/ISA names, and
+ ISA levels, and CPU numbers. */
+
+ struct mips_cpu_info
+ {
+ const char *name; /* CPU or ISA name. */
+ int is_isa; /* Is this an ISA? (If 0, a CPU.) */
+ int isa; /* ISA level. */
+ int cpu; /* CPU number (default CPU if ISA). */
+ };
+
+ static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS
+ ((const char *));
+ static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int));
+ static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int));
+
/* Pseudo-op table.
The following pseudo-ops from the Kane and Heinrich MIPS book
*************** static boolean mips16_small, mips16_ext;
*** 852,884 ****
static segT pdr_seg;
#endif
! static char *
mips_cpu_to_str (cpu)
int cpu;
{
static char s[16];
! switch (cpu)
! {
! case CPU_R2000: return "R2000";
! case CPU_R3000: return "R3000";
! case CPU_R3900: return "R3900";
! case CPU_R4000: return "R4000";
! case CPU_R4010: return "R4010";
! case CPU_VR4100: return "VR4100";
! case CPU_R4111: return "R4111";
! case CPU_R4300: return "R4300";
! case CPU_R4400: return "R4400";
! case CPU_R4600: return "R4600";
! case CPU_R4650: return "R4650";
! case CPU_R5000: return "R5000";
! case CPU_R6000: return "R6000";
! case CPU_R8000: return "R8000";
! case CPU_R10000: return "R10000";
! case CPU_4K: return "4K";
! default:
! sprintf (s, "%d", cpu);
! return s;
! }
}
/* This function is called once, at assembler startup time. It should
--- 872,905 ----
static segT pdr_seg;
#endif
! static const char *
! mips_isa_to_str (isa)
! int isa;
! {
! const struct mips_cpu_info *ci;
! static char s[20];
!
! ci = mips_cpu_info_from_isa (isa);
! if (ci != NULL)
! return (ci->name);
!
! sprintf (s, "ISA#%d", isa);
! return s;
! }
!
! static const char *
mips_cpu_to_str (cpu)
int cpu;
{
+ const struct mips_cpu_info *ci;
static char s[16];
!
! ci = mips_cpu_info_from_cpu (cpu);
! if (ci != NULL)
! return (ci->name);
!
! sprintf (s, "CPU#%d", cpu);
! return s;
}
/* This function is called once, at assembler startup time. It should
*************** mips_cpu_to_str (cpu)
*** 887,899 ****
void
md_begin ()
{
- boolean ok = false;
register const char *retval = NULL;
int i = 0;
const char *cpu;
char *a = NULL;
int broken = 0;
int mips_isa_from_cpu;
/* GP relative stuff not working for PE */
if (strncmp (TARGET_OS, "pe", 2) == 0
--- 908,921 ----
void
md_begin ()
{
register const char *retval = NULL;
int i = 0;
const char *cpu;
char *a = NULL;
int broken = 0;
int mips_isa_from_cpu;
+ int target_cpu_had_mips16 = 0;
+ const struct mips_cpu_info *ci;
/* GP relative stuff not working for PE */
if (strncmp (TARGET_OS, "pe", 2) == 0
*************** md_begin ()
*** 912,1042 ****
a[(sizeof TARGET_CPU) - 3] = '\0';
cpu = a;
}
!
! if (mips_cpu < 0)
{
! /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
! just the generic 'mips', in which case set mips_cpu based
! on the given ISA, if any. */
!
! if (strcmp (cpu, "mips") == 0)
! {
! if (mips_opts.isa < 0)
! mips_cpu = CPU_R3000;
!
! else if (mips_opts.isa == 2)
! mips_cpu = CPU_R6000;
!
! else if (mips_opts.isa == 3)
! mips_cpu = CPU_R4000;
!
! else if (mips_opts.isa == 4)
! mips_cpu = CPU_R8000;
!
! else
! mips_cpu = CPU_R3000;
! }
!
! else if (strcmp (cpu, "r3900") == 0
! || strcmp (cpu, "mipstx39") == 0
! )
! mips_cpu = CPU_R3900;
!
! else if (strcmp (cpu, "r6000") == 0
! || strcmp (cpu, "mips2") == 0)
! mips_cpu = CPU_R6000;
!
! else if (strcmp (cpu, "mips64") == 0
! || strcmp (cpu, "r4000") == 0
! || strcmp (cpu, "mips3") == 0)
! mips_cpu = CPU_R4000;
!
! else if (strcmp (cpu, "r4400") == 0)
! mips_cpu = CPU_R4400;
!
! else if (strcmp (cpu, "mips64orion") == 0
! || strcmp (cpu, "r4600") == 0)
! mips_cpu = CPU_R4600;
!
! else if (strcmp (cpu, "r4650") == 0)
! mips_cpu = CPU_R4650;
!
! else if (strcmp (cpu, "mips64vr4300") == 0)
! mips_cpu = CPU_R4300;
!
! else if (strcmp (cpu, "mips64vr4111") == 0)
! mips_cpu = CPU_R4111;
!
! else if (strcmp (cpu, "mips64vr4100") == 0)
! mips_cpu = CPU_VR4100;
!
! else if (strcmp (cpu, "r4010") == 0)
! mips_cpu = CPU_R4010;
!
! else if (strcmp (cpu, "4Kc") == 0
! || strcmp (cpu, "4Kp") == 0
! || strcmp (cpu, "4Km") == 0)
! mips_cpu = CPU_4K;
!
! else if (strcmp (cpu, "r5000") == 0
! || strcmp (cpu, "mips64vr5000") == 0)
! mips_cpu = CPU_R5000;
!
! else if (strcmp (cpu, "r8000") == 0
! || strcmp (cpu, "mips4") == 0)
! mips_cpu = CPU_R8000;
!
! else if (strcmp (cpu, "r10000") == 0)
! mips_cpu = CPU_R10000;
!
! else if (strcmp (cpu, "mips16") == 0)
! mips_cpu = 0; /* FIXME */
!
! else
! mips_cpu = CPU_R3000;
}
! if (mips_cpu == CPU_R3000
! || mips_cpu == CPU_R3900)
! mips_isa_from_cpu = 1;
!
! else if (mips_cpu == CPU_R6000
! || mips_cpu == CPU_R4010)
! mips_isa_from_cpu = 2;
!
! else if (mips_cpu == CPU_R4000
! || mips_cpu == CPU_VR4100
! || mips_cpu == CPU_R4111
! || mips_cpu == CPU_R4400
! || mips_cpu == CPU_R4300
! || mips_cpu == CPU_R4600
! || mips_cpu == CPU_R4650)
! mips_isa_from_cpu = 3;
!
! else if (mips_cpu == CPU_R5000
! || mips_cpu == CPU_R8000
! || mips_cpu == CPU_R10000)
! mips_isa_from_cpu = 4;
!
! else
! mips_isa_from_cpu = -1;
!
! if (mips_opts.isa == -1)
{
! if (mips_isa_from_cpu != -1)
! mips_opts.isa = mips_isa_from_cpu;
! else
! mips_opts.isa = 1;
}
!
! if (mips_opts.mips16 < 0)
{
! if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0)
! mips_opts.mips16 = 1;
! else
! mips_opts.mips16 = 0;
}
/* End of TARGET_CPU processing, get rid of malloced memory
if necessary. */
cpu = NULL;
--- 934,984 ----
a[(sizeof TARGET_CPU) - 3] = '\0';
cpu = a;
}
! if (strncmp (cpu, "mips16", sizeof "mips16" - 1) == 0)
{
! target_cpu_had_mips16 = 1;
! cpu += sizeof "mips16" - 1;
}
+ if (mips_opts.mips16 < 0)
+ mips_opts.mips16 = target_cpu_had_mips16;
! /* At this point, mips_cpu will either be CPU_UNKNOWN if no CPU was
! specified on the command line, or some other value if one was.
! Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
! the command line, or will be set otherwise if one was. */
! if (mips_cpu != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
{
! /* We have it all. There's nothing to do. */
}
! else if (mips_cpu != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN)
{
! /* We have CPU, we need ISA. */
! ci = mips_cpu_info_from_cpu (mips_cpu);
! assert (ci != NULL);
! mips_opts.isa = ci->isa;
! }
! else if (mips_cpu == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
! {
! /* We have ISA, we need default CPU. */
! ci = mips_cpu_info_from_isa (mips_opts.isa);
! assert (ci != NULL);
! mips_cpu = ci->cpu;
! }
! else
! {
! /* We need to set both ISA and CPU from target cpu. */
! ci = mips_cpu_info_from_name (cpu);
! if (ci == NULL)
! ci = mips_cpu_info_from_cpu (CPU_R3000);
! assert (ci != NULL);
! mips_opts.isa = ci->isa;
! mips_cpu = ci->cpu;
}
+ ci = mips_cpu_info_from_cpu (mips_cpu);
+ assert (ci != NULL);
+ mips_isa_from_cpu = ci->isa;
+
/* End of TARGET_CPU processing, get rid of malloced memory
if necessary. */
cpu = NULL;
*************** md_begin ()
*** 1046,1052 ****
a = NULL;
}
! if (mips_opts.isa == 1 && mips_trap)
as_bad (_("trap exception not supported at ISA 1"));
/* Set the EABI kind based on the ISA before the user gets
--- 988,994 ----
a = NULL;
}
! if (mips_opts.isa == ISA_MIPS1 && mips_trap)
as_bad (_("trap exception not supported at ISA 1"));
/* Set the EABI kind based on the ISA before the user gets
*************** md_begin ()
*** 1057,1093 ****
&& 0 == strcmp (mips_abi_string,"eabi"))
mips_eabi64 = 1;
! if (mips_cpu != 0 && mips_cpu != -1)
! {
! ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu);
! /* If they asked for mips1 or mips2 and a cpu that is
! mips3 or greater, then mark the object file 32BITMODE. */
! if (mips_isa_from_cpu != -1
! && ! ISA_HAS_64BIT_REGS (mips_opts.isa)
! && ISA_HAS_64BIT_REGS (mips_isa_from_cpu))
! mips_32bitmode = 1;
! }
! else
! {
! switch (mips_opts.isa)
! {
! case 1:
! ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, CPU_R3000);
! break;
! case 2:
! ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, CPU_R6000);
! break;
! case 3:
! ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, CPU_R4000);
! break;
! case 4:
! ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, CPU_R8000);
! break;
! }
! }
!
! if (! ok)
as_warn (_("Could not set architecture and machine"));
file_mips_isa = mips_opts.isa;
--- 999,1012 ----
&& 0 == strcmp (mips_abi_string,"eabi"))
mips_eabi64 = 1;
! /* If they asked for mips1 or mips2 and a cpu that is
! mips3 or greater, then mark the object file 32BITMODE. */
! if (mips_isa_from_cpu != ISA_UNKNOWN
! && ! ISA_HAS_64BIT_REGS (mips_opts.isa)
! && ISA_HAS_64BIT_REGS (mips_isa_from_cpu))
! mips_32bitmode = 1;
! if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu))
as_warn (_("Could not set architecture and machine"));
file_mips_isa = mips_opts.isa;
*************** append_insn (place, ip, address_expr, re
*** 1549,1555 ****
&& ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
&& ! cop_interlocks)
! || (mips_opts.isa == 1
&& (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
{
/* A generic coprocessor delay. The previous instruction
--- 1468,1474 ----
&& ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
&& ! cop_interlocks)
! || (mips_opts.isa == ISA_MIPS1
&& (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
{
/* A generic coprocessor delay. The previous instruction
*************** append_insn (place, ip, address_expr, re
*** 2083,2089 ****
&& ! gpr_interlocks
&& (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
|| (! mips_opts.mips16
! && mips_opts.isa == 1
/* Itbl support may require additional care here. */
&& (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
/* We can not swap with a branch instruction. */
--- 2002,2008 ----
&& ! gpr_interlocks
&& (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
|| (! mips_opts.mips16
! && mips_opts.isa == ISA_MIPS1
/* Itbl support may require additional care here. */
&& (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
/* We can not swap with a branch instruction. */
*************** mips_emit_delays (insns)
*** 2419,2425 ****
&& (prev_insn.insn_mo->pinfo
& INSN_LOAD_MEMORY_DELAY))
|| (! mips_opts.mips16
! && mips_opts.isa == 1
&& (prev_insn.insn_mo->pinfo
& INSN_COPROC_MEMORY_DELAY)))
{
--- 2338,2344 ----
&& (prev_insn.insn_mo->pinfo
& INSN_LOAD_MEMORY_DELAY))
|| (! mips_opts.mips16
! && mips_opts.isa == ISA_MIPS1
&& (prev_insn.insn_mo->pinfo
& INSN_COPROC_MEMORY_DELAY)))
{
*************** macro (ip)
*** 5420,5426 ****
s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
if (strcmp (s, ".lit8") == 0)
{
! if (mips_opts.isa != 1)
{
macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
"T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP);
--- 5339,5345 ----
s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
if (strcmp (s, ".lit8") == 0)
{
! if (mips_opts.isa != ISA_MIPS1)
{
macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
"T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP);
*************** macro (ip)
*** 5445,5451 ****
macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT);
}
! if (mips_opts.isa != 1)
{
macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
"T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
--- 5364,5370 ----
macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT);
}
! if (mips_opts.isa != ISA_MIPS1)
{
macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
"T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
*************** macro (ip)
*** 5472,5478 ****
to adjust when loading from memory. */
r = BFD_RELOC_LO16;
dob:
! assert (mips_opts.isa == 1);
macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
target_big_endian ? treg + 1 : treg,
(int) r, breg);
--- 5391,5397 ----
to adjust when loading from memory. */
r = BFD_RELOC_LO16;
dob:
! assert (mips_opts.isa == ISA_MIPS1);
macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
target_big_endian ? treg + 1 : treg,
(int) r, breg);
*************** macro (ip)
*** 5511,5517 ****
}
/* Itbl support may require additional care here. */
coproc = 1;
! if (mips_opts.isa != 1)
{
s = "ldc1";
goto ld;
--- 5430,5436 ----
}
/* Itbl support may require additional care here. */
coproc = 1;
! if (mips_opts.isa != ISA_MIPS1)
{
s = "ldc1";
goto ld;
*************** macro (ip)
*** 5528,5534 ****
return;
}
! if (mips_opts.isa != 1)
{
s = "sdc1";
goto st;
--- 5447,5453 ----
return;
}
! if (mips_opts.isa != ISA_MIPS1)
{
s = "sdc1";
goto st;
*************** macro2 (ip)
*** 6156,6162 ****
as_bad (_("opcode not supported on this processor"));
return;
}
! assert (mips_opts.isa == 1);
/* Even on a big endian machine $fn comes before $fn+1. We have
to adjust when storing to memory. */
macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
--- 6075,6081 ----
as_bad (_("opcode not supported on this processor"));
return;
}
! assert (mips_opts.isa == ISA_MIPS1);
/* Even on a big endian machine $fn comes before $fn+1. We have
to adjust when storing to memory. */
macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
*************** macro2 (ip)
*** 6465,6471 ****
case M_TRUNCWS:
case M_TRUNCWD:
! assert (mips_opts.isa == 1);
sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
--- 6384,6390 ----
case M_TRUNCWS:
case M_TRUNCWD:
! assert (mips_opts.isa == ISA_MIPS1);
sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
*************** mips_ip (str, ip)
*** 7146,7153 ****
{
static char buf[100];
sprintf (buf,
! _("opcode not supported on this processor: %s (MIPS%d)"),
! mips_cpu_to_str (mips_cpu), mips_opts.isa);
insn_error = buf;
return;
--- 7065,7073 ----
{
static char buf[100];
sprintf (buf,
! _("opcode not supported on this processor: %s (%s)"),
! mips_cpu_to_str (mips_cpu),
! mips_isa_to_str (mips_opts.isa));
insn_error = buf;
return;
*************** struct option md_longopts[] =
*** 8964,8972 ****
{"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
#define OPTION_MIPS32 (OPTION_MD_BASE + 28)
{"mips32", no_argument, NULL, OPTION_MIPS32},
- #define OPTION_NO_MIPS32 (OPTION_MD_BASE + 29)
- {"no-mips32", no_argument, NULL, OPTION_NO_MIPS32},
-
#ifdef OBJ_ELF
#define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
--- 8884,8889 ----
*************** md_parse_option (c, arg)
*** 9037,9190 ****
break;
case OPTION_MIPS1:
! mips_opts.isa = 1;
break;
case OPTION_MIPS2:
! mips_opts.isa = 2;
break;
case OPTION_MIPS3:
! mips_opts.isa = 3;
break;
case OPTION_MIPS4:
! mips_opts.isa = 4;
break;
case OPTION_MCPU:
{
- char *p;
/* Identify the processor type */
! p = arg;
! if (strcmp (p, "default") == 0
! || strcmp (p, "DEFAULT") == 0)
! mips_cpu = -1;
else
{
! int sv = 0;
! /* We need to cope with the various "vr" prefixes for the 4300
! processor. */
! if (*p == 'v' || *p == 'V')
! {
! sv = 1;
! p++;
! }
!
! if (*p == 'r' || *p == 'R')
! p++;
!
! mips_cpu = -1;
! switch (*p)
! {
! case '1':
! if (strcmp (p, "10000") == 0
! || strcmp (p, "10k") == 0
! || strcmp (p, "10K") == 0)
! mips_cpu = CPU_R10000;
! break;
!
! case '2':
! if (strcmp (p, "2000") == 0
! || strcmp (p, "2k") == 0
! || strcmp (p, "2K") == 0)
! mips_cpu = CPU_R2000;
! break;
!
! case '3':
! if (strcmp (p, "3000") == 0
! || strcmp (p, "3k") == 0
! || strcmp (p, "3K") == 0)
! mips_cpu = CPU_R3000;
! else if (strcmp (p, "3900") == 0)
! mips_cpu = CPU_R3900;
! break;
!
! case '4':
! if (strcmp (p, "4000") == 0
! || strcmp (p, "4k") == 0
! || strcmp (p, "4K") == 0)
! mips_cpu = CPU_R4000;
! else if (strcmp (p, "4100") == 0)
! mips_cpu = CPU_VR4100;
! else if (strcmp (p, "4111") == 0)
! mips_cpu = CPU_R4111;
! else if (strcmp (p, "4300") == 0)
! mips_cpu = CPU_R4300;
! else if (strcmp (p, "4400") == 0)
! mips_cpu = CPU_R4400;
! else if (strcmp (p, "4600") == 0)
! mips_cpu = CPU_R4600;
! else if (strcmp (p, "4650") == 0)
! mips_cpu = CPU_R4650;
! else if (strcmp (p, "4010") == 0)
! mips_cpu = CPU_R4010;
! else if (strcmp (p, "4Kc") == 0
! || strcmp (p, "4Kp") == 0
! || strcmp (p, "4Km") == 0)
! mips_cpu = CPU_MIPS32;
! break;
!
! case '5':
! if (strcmp (p, "5000") == 0
! || strcmp (p, "5k") == 0
! || strcmp (p, "5K") == 0)
! mips_cpu = CPU_R5000;
! break;
!
! case '6':
! if (strcmp (p, "6000") == 0
! || strcmp (p, "6k") == 0
! || strcmp (p, "6K") == 0)
! mips_cpu = CPU_R6000;
! break;
!
! case '8':
! if (strcmp (p, "8000") == 0
! || strcmp (p, "8k") == 0
! || strcmp (p, "8K") == 0)
! mips_cpu = CPU_R8000;
! break;
!
! case 'o':
! if (strcmp (p, "orion") == 0)
! mips_cpu = CPU_R4600;
! break;
!
! case 'm':
! case 'M':
! switch (atoi (p + 1))
! {
! case 5200:
! case 5230:
! case 5231:
! case 5261:
! case 5721:
! case 7000:
! mips_cpu = CPU_R5000;
! break;
! default:
! break;
! }
! }
!
! if (sv
! && (mips_cpu != CPU_R4300
! && mips_cpu != CPU_VR4100
! && mips_cpu != CPU_R4111
! && mips_cpu != CPU_R5000))
! {
! as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg);
! return 0;
! }
!
! if (mips_cpu == -1)
! {
as_bad (_("invalid architecture -mcpu=%s"), arg);
! return 0;
! }
}
}
break;
--- 8954,8993 ----
break;
case OPTION_MIPS1:
! mips_opts.isa = ISA_MIPS1;
break;
case OPTION_MIPS2:
! mips_opts.isa = ISA_MIPS2;
break;
case OPTION_MIPS3:
! mips_opts.isa = ISA_MIPS3;
break;
case OPTION_MIPS4:
! mips_opts.isa = ISA_MIPS4;
! break;
!
! case OPTION_MIPS32:
! mips_opts.isa = ISA_MIPS32;
break;
case OPTION_MCPU:
{
/* Identify the processor type */
! if (strcasecmp (arg, "default") == 0)
! mips_cpu = CPU_UNKNOWN;
else
{
! const struct mips_cpu_info *ci;
! ci = mips_cpu_info_from_name (arg);
! if (ci == NULL || ci->is_isa)
as_bad (_("invalid architecture -mcpu=%s"), arg);
! else
! mips_cpu = ci->cpu;
}
}
break;
*************** md_parse_option (c, arg)
*** 9210,9222 ****
case OPTION_NO_M4100:
break;
- case OPTION_MIPS32:
- mips_cpu = CPU_MIPS32;
- break;
-
- case OPTION_NO_MIPS32:
- break;
-
case OPTION_M3900:
mips_cpu = CPU_R3900;
break;
--- 9013,9018 ----
*************** MIPS options:\n\
*** 9411,9416 ****
--- 9207,9213 ----
-mips2 generate MIPS ISA II instructions\n\
-mips3 generate MIPS ISA III instructions\n\
-mips4 generate MIPS ISA IV instructions\n\
+ -mips32 generate MIPS32 ISA instructions\n\
-mcpu=CPU generate code for CPU, where CPU is one of:\n"));
first = 1;
*************** MIPS options:\n\
*** 9430,9438 ****
show (stream, "6000", &column, &first);
show (stream, "8000", &column, &first);
show (stream, "10000", &column, &first);
! show (stream, "4Kc", &column, &first);
! show (stream, "4Kp", &column, &first);
! show (stream, "4Km", &column, &first);
fputc ('\n', stream);
fprintf (stream, _("\
--- 9227,9233 ----
show (stream, "6000", &column, &first);
show (stream, "8000", &column, &first);
show (stream, "10000", &column, &first);
! show (stream, "mips32-4k", &column, &first);
fputc ('\n', stream);
fprintf (stream, _("\
*************** MIPS options:\n\
*** 9448,9456 ****
show (stream, "4650", &column, &first);
fputc ('\n', stream);
- fprintf (stream, _("\
- -mips32 generate MIPS32 instructions\n"));
-
fprintf(stream, _("\
-mips16 generate mips16 instructions\n\
-no-mips16 do not generate mips16 instructions\n"));
--- 9243,9248 ----
*************** s_mipsset (x)
*** 10441,10452 ****
/* Permit the user to change the ISA on the fly. Needless to
say, misuse can cause serious problems. */
isa = atoi (name + 4);
! if (isa == 0)
! mips_opts.isa = file_mips_isa;
! else if (isa < 1 || isa > 4)
! as_bad (_("unknown ISA level"));
! else
! mips_opts.isa = isa;
}
else if (strcmp (name, "autoextend") == 0)
mips_opts.noautoextend = 0;
--- 10233,10262 ----
/* Permit the user to change the ISA on the fly. Needless to
say, misuse can cause serious problems. */
isa = atoi (name + 4);
! switch (isa)
! {
! case 0:
! mips_opts.isa = file_mips_isa;
! break;
! case 1:
! mips_opts.isa = ISA_MIPS1;
! break;
! case 2:
! mips_opts.isa = ISA_MIPS2;
! break;
! case 3:
! mips_opts.isa = ISA_MIPS3;
! break;
! case 4:
! mips_opts.isa = ISA_MIPS4;
! break;
! case 32:
! mips_opts.isa = ISA_MIPS32;
! break;
! default:
! as_bad (_("unknown ISA level"));
! break;
! }
}
else if (strcmp (name, "autoextend") == 0)
mips_opts.noautoextend = 0;
*************** s_loc (x)
*** 12092,12094 ****
--- 11902,12080 ----
symbolP->sy_segment = now_seg;
}
#endif
+
+ /* CPU name/ISA/number mapping table.
+
+ Entries are grouped by type. The first matching CPU or ISA entry
+ gets chosen by CPU or ISA, so it should be the 'canonical' name
+ for that type. Entries after that within the type are sorted
+ alphabetically.
+
+ Case is ignored in comparison, so put the canonical entry in the
+ appropriate case but everything else in lower case to ease eye pain. */
+ static const struct mips_cpu_info mips_cpu_info_table[] =
+ {
+ /* MIPS1 ISA */
+ { "MIPS1", 1, ISA_MIPS1, CPU_R3000, },
+ { "mips", 1, ISA_MIPS1, CPU_R3000, },
+
+ /* MIPS2 ISA */
+ { "MIPS2", 1, ISA_MIPS2, CPU_R6000, },
+
+ /* MIPS3 ISA */
+ { "MIPS3", 1, ISA_MIPS3, CPU_R4000, },
+
+ /* MIPS4 ISA */
+ { "MIPS4", 1, ISA_MIPS4, CPU_R8000, },
+
+ /* MIPS32 ISA */
+ { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, },
+ { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, },
+
+ /* XXX for now, MIPS64 -> MIPS3 because of history */
+ { "MIPS64", 1, ISA_MIPS3, CPU_R4000 }, /* XXX! */
+
+ /* R2000 CPU */
+ { "R2000", 0, ISA_MIPS1, CPU_R2000, },
+ { "2000", 0, ISA_MIPS1, CPU_R2000, },
+ { "2k", 0, ISA_MIPS1, CPU_R2000, },
+ { "r2k", 0, ISA_MIPS1, CPU_R2000, },
+
+ /* R3000 CPU */
+ { "R3000", 0, ISA_MIPS1, CPU_R3000, },
+ { "3000", 0, ISA_MIPS1, CPU_R3000, },
+ { "3k", 0, ISA_MIPS1, CPU_R3000, },
+ { "r3k", 0, ISA_MIPS1, CPU_R3000, },
+
+ /* TX3900 CPU */
+ { "R3900", 0, ISA_MIPS1, CPU_R3900, },
+ { "3900", 0, ISA_MIPS1, CPU_R3900, },
+ { "mipstx39", 0, ISA_MIPS1, CPU_R3900, },
+
+ /* R4000 CPU */
+ { "R4000", 0, ISA_MIPS3, CPU_R4000, },
+ { "4000", 0, ISA_MIPS3, CPU_R4000, },
+ { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */
+ { "r4k", 0, ISA_MIPS3, CPU_R4000, },
+
+ /* R4010 CPU */
+ { "R4010", 0, ISA_MIPS2, CPU_R4010, },
+ { "4010", 0, ISA_MIPS2, CPU_R4010, },
+
+ /* R4400 CPU */
+ { "R4400", 0, ISA_MIPS3, CPU_R4400, },
+ { "4400", 0, ISA_MIPS3, CPU_R4400, },
+
+ /* R4600 CPU */
+ { "R4600", 0, ISA_MIPS3, CPU_R4600, },
+ { "4600", 0, ISA_MIPS3, CPU_R4600, },
+ { "mips64orion", 0, ISA_MIPS3, CPU_R4600, },
+ { "orion", 0, ISA_MIPS3, CPU_R4600, },
+
+ /* R4650 CPU */
+ { "R4650", 0, ISA_MIPS3, CPU_R4650, },
+ { "4650", 0, ISA_MIPS3, CPU_R4650, },
+
+ /* R6000 CPU */
+ { "R6000", 0, ISA_MIPS2, CPU_R6000, },
+ { "6000", 0, ISA_MIPS2, CPU_R6000, },
+ { "6k", 0, ISA_MIPS2, CPU_R6000, },
+ { "r6k", 0, ISA_MIPS2, CPU_R6000, },
+
+ /* R8000 CPU */
+ { "R8000", 0, ISA_MIPS4, CPU_R8000, },
+ { "8000", 0, ISA_MIPS4, CPU_R8000, },
+ { "8k", 0, ISA_MIPS4, CPU_R8000, },
+ { "r8k", 0, ISA_MIPS4, CPU_R8000, },
+
+ /* R10000 CPU */
+ { "R10000", 0, ISA_MIPS4, CPU_R10000, },
+ { "10000", 0, ISA_MIPS4, CPU_R10000, },
+ { "10k", 0, ISA_MIPS4, CPU_R10000, },
+ { "r10k", 0, ISA_MIPS4, CPU_R10000, },
+
+ /* VR4100 CPU */
+ { "VR4100", 0, ISA_MIPS3, CPU_VR4100, },
+ { "4100", 0, ISA_MIPS3, CPU_VR4100, },
+ { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, },
+ { "r4100", 0, ISA_MIPS3, CPU_VR4100, },
+
+ /* VR4111 CPU */
+ { "VR4111", 0, ISA_MIPS3, CPU_R4111, },
+ { "4111", 0, ISA_MIPS3, CPU_R4111, },
+ { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, },
+ { "r4111", 0, ISA_MIPS3, CPU_R4111, },
+
+ /* VR4300 CPU */
+ { "VR4300", 0, ISA_MIPS3, CPU_R4300, },
+ { "4300", 0, ISA_MIPS3, CPU_R4300, },
+ { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, },
+ { "r4300", 0, ISA_MIPS3, CPU_R4300, },
+
+ /* VR5000 CPU */
+ { "VR5000", 0, ISA_MIPS4, CPU_R5000, },
+ { "5000", 0, ISA_MIPS4, CPU_R5000, },
+ { "5k", 0, ISA_MIPS4, CPU_R5000, },
+ { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, },
+ { "r5000", 0, ISA_MIPS4, CPU_R5000, },
+ { "r5200", 0, ISA_MIPS4, CPU_R5000, },
+ { "r5230", 0, ISA_MIPS4, CPU_R5000, },
+ { "r5231", 0, ISA_MIPS4, CPU_R5000, },
+ { "r5261", 0, ISA_MIPS4, CPU_R5000, },
+ { "r5721", 0, ISA_MIPS4, CPU_R5000, },
+ { "r5k", 0, ISA_MIPS4, CPU_R5000, },
+ { "r7000", 0, ISA_MIPS4, CPU_R5000, },
+
+ /* MIPS32 4K CPU */
+ { "MIPS32-4K", 0, ISA_MIPS32, CPU_MIPS32_4K, },
+ { "4kc", 0, ISA_MIPS32, CPU_MIPS32_4K, },
+ { "4km", 0, ISA_MIPS32, CPU_MIPS32_4K, },
+ { "4kp", 0, ISA_MIPS32, CPU_MIPS32_4K, },
+ { "mips32-4kc", 0, ISA_MIPS32, CPU_MIPS32_4K, },
+ { "mips32-4km", 0, ISA_MIPS32, CPU_MIPS32_4K, },
+ { "mips32-4kp", 0, ISA_MIPS32, CPU_MIPS32_4K, },
+
+ /* End marker. */
+ { NULL, 0, 0, 0, },
+ };
+
+ static const struct mips_cpu_info *
+ mips_cpu_info_from_name (name)
+ const char *name;
+ {
+ int i;
+
+ for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
+ if (strcasecmp(name, mips_cpu_info_table[i].name) == 0)
+ return (&mips_cpu_info_table[i]);
+
+ return (NULL);
+ }
+
+ static const struct mips_cpu_info *
+ mips_cpu_info_from_isa (isa)
+ int isa;
+ {
+ int i;
+
+ for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
+ if (mips_cpu_info_table[i].is_isa
+ && isa == mips_cpu_info_table[i].isa)
+ return (&mips_cpu_info_table[i]);
+
+ return (NULL);
+ }
+
+ static const struct mips_cpu_info *
+ mips_cpu_info_from_cpu (cpu)
+ int cpu;
+ {
+ int i;
+
+ for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
+ if (!mips_cpu_info_table[i].is_isa
+ && cpu == mips_cpu_info_table[i].cpu)
+ return (&mips_cpu_info_table[i]);
+
+ return (NULL);
+ }
diff -rcp ../src.P06/gas/doc/as.texinfo ./gas/doc/as.texinfo
*** ../src.P06/gas/doc/as.texinfo Wed Sep 13 18:47:35 2000
--- ./gas/doc/as.texinfo Sat Oct 14 23:25:30 2000
*************** Here is a brief summary of how to invoke
*** 278,284 ****
@end ifset
@ifset MIPS
[ -nocpp ] [ -EL ] [ -EB ] [ -G @var{num} ] [ -mcpu=@var{CPU} ]
! [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -m4650 ] [ -no-m4650 ] [ -mips32 ] [ -no-mips32 ]
[ --trap ] [ --break ]
[ --emulation=@var{name} ]
@end ifset
--- 278,285 ----
@end ifset
@ifset MIPS
[ -nocpp ] [ -EL ] [ -EB ] [ -G @var{num} ] [ -mcpu=@var{CPU} ]
! [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -mips4 ] [ -mips32 ]
! [ -m4650 ] [ -no-m4650 ]
[ --trap ] [ --break ]
[ --emulation=@var{name} ]
@end ifset
*************** Generate ``little endian'' format output
*** 667,676 ****
@item -mips1
@itemx -mips2
@itemx -mips3
Generate code for a particular MIPS Instruction Set Architecture level.
@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
! @samp{-mips2} to the @sc{r6000} processor, and @samp{-mips3} to the @sc{r4000}
! processor.
@item -m4650
@itemx -no-m4650
--- 668,679 ----
@item -mips1
@itemx -mips2
@itemx -mips3
+ @itemx -mips4
+ @itemx -mips32
Generate code for a particular MIPS Instruction Set Architecture level.
@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
! @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the @sc{r4000}
! processor, @samp{-mips32} to a generic @sc{MIPS32} processor.
@item -m4650
@itemx -no-m4650
*************** Generate code for the MIPS @sc{r4650} ch
*** 678,689 ****
the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
instructions around accesses to the @samp{HI} and @samp{LO} registers.
@samp{-no-m4650} turns off this option.
-
- @item -mips32
- @itemx -no-mips32
- Generate code for the @sc{MIPS32} architecture. This tells the assembler to
- accept ISA level 2 instructions and MIPS32 extensions including some @sc{r4000}
- instructions.
@item -mcpu=@var{CPU}
Generate code for a particular MIPS cpu. This has little effect on the
--- 681,686 ----
diff -rcp ../src.P06/gas/doc/c-mips.texi ./gas/doc/c-mips.texi
*** ../src.P06/gas/doc/c-mips.texi Wed Sep 13 18:47:36 2000
--- ./gas/doc/c-mips.texi Mon Oct 16 15:03:50 2000
*************** to select big-endian output, and @samp{-
*** 60,71 ****
@itemx -mips2
@itemx -mips3
@itemx -mips4
Generate code for a particular MIPS Instruction Set Architecture level.
@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
! @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
! @sc{r10000} processors. You can also switch instruction sets during the
! assembly; see @ref{MIPS ISA,, Directives to override the ISA level}.
@item -mgp32
Assume that 32-bit general purpose registers are available. This
--- 60,73 ----
@itemx -mips2
@itemx -mips3
@itemx -mips4
+ @itemx -mips32
Generate code for a particular MIPS Instruction Set Architecture level.
@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
! @sc{r4000} processor, @samp{-mips4} to the @sc{r8000} and
! @sc{r10000} processors, and @samp{-mips32} to a generic @sc(MIPS32)
! processor. You can also switch instruction sets during the
! assembly; see @ref{MIPS ISA, Directives to override the ISA level}.
@item -mgp32
Assume that 32-bit general purpose registers are available. This
*************** rm5721,
*** 140,149 ****
6000,
rm7000,
8000,
! 10000
! 4Kc
! 4Km
! 4Kp
@end quotation
--- 142,149 ----
6000,
rm7000,
8000,
! 10000,
! mips32-4k
@end quotation
*************** assembly language programmers!
*** 239,246 ****
@kindex @code{.set mips@var{n}}
@sc{gnu} @code{@value{AS}} supports an additional directive to change
the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
! mips@var{n}}. @var{n} should be a number from 0 to 4. A value from 1
! to 4 makes the assembler accept instructions for the corresponding
@sc{isa} level, from that point on in the assembly. @code{.set
mips@var{n}} affects not only which instructions are permitted, but also
how certain macros are expanded. @code{.set mips0} restores the
--- 239,246 ----
@kindex @code{.set mips@var{n}}
@sc{gnu} @code{@value{AS}} supports an additional directive to change
the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
! mips@var{n}}. @var{n} should be a number from 0 to 4, or 32. The values 1
! to 4 and 32 make the assembler accept instructions for the corresponding
@sc{isa} level, from that point on in the assembly. @code{.set
mips@var{n}} affects not only which instructions are permitted, but also
how certain macros are expanded. @code{.set mips0} restores the
diff -rcp ../src.P06/include/elf/mips.h ./include/elf/mips.h
*** ../src.P06/include/elf/mips.h Wed Sep 13 18:47:36 2000
--- ./include/elf/mips.h Sat Oct 14 23:23:21 2000
*************** END_RELOC_NUMBERS (R_MIPS_maxext)
*** 121,126 ****
--- 121,129 ----
/* -mips4 code. */
#define E_MIPS_ARCH_4 0x30000000
+ /* -mips32 code. */
+ #define E_MIPS_ARCH_32 0x50000000
+
/* The ABI of the file. Also see EF_MIPS_ABI2 above. */
#define EF_MIPS_ABI 0x0000F000
*************** END_RELOC_NUMBERS (R_MIPS_maxext)
*** 153,161 ****
#define E_MIPS_MACH_4100 0x00830000
#define E_MIPS_MACH_4650 0x00850000
#define E_MIPS_MACH_4111 0x00880000
! /* -mips32 code.
! It is easier to treat MIPS32 as a machine rather than an architecture. */
! #define E_MIPS_MACH_MIPS32 0x00890000
/* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these
--- 156,162 ----
#define E_MIPS_MACH_4100 0x00830000
#define E_MIPS_MACH_4650 0x00850000
#define E_MIPS_MACH_4111 0x00880000
! #define E_MIPS_MACH_MIPS32_4K 0x00890000
/* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these
diff -rcp ../src.P06/include/opcode/mips.h ./include/opcode/mips.h
*** ../src.P06/include/opcode/mips.h Sat Oct 14 22:51:58 2000
--- ./include/opcode/mips.h Sat Oct 14 23:36:27 2000
*************** struct mips_opcode
*** 303,341 ****
!
!
! /* MIPS ISA field--CPU level at which insn is supported. */
! #define INSN_ISA 0x0000000F
! /* An instruction which is not part of any basic MIPS ISA.
! (ie it is a chip specific instruction) */
! #define INSN_NO_ISA 0x00000000
! /* MIPS ISA 1 instruction. */
! #define INSN_ISA1 0x00000001
! /* MIPS ISA 2 instruction (R6000 or R4000). */
! #define INSN_ISA2 0x00000002
! /* MIPS ISA 3 instruction (R4000). */
! #define INSN_ISA3 0x00000003
! /* MIPS ISA 4 instruction (R8000). */
! #define INSN_ISA4 0x00000004
! #define INSN_ISA5 0x00000005
/* Chip specific instructions. These are bitmasks. */
/* MIPS R4650 instruction. */
! #define INSN_4650 0x00000010
/* LSI R4010 instruction. */
! #define INSN_4010 0x00000020
/* NEC VR4100 instruction. */
! #define INSN_4100 0x00000040
/* Toshiba R3900 instruction. */
! #define INSN_3900 0x00000080
! /* MIPS32 instruction (4Kc, 4Km, 4Kp). */
! #define INSN_MIPS32 0x00000100
/* 32-bit code running on a ISA3+ CPU. */
! #define INSN_GP32 0x00001000
/* CPU defines, use instead of hardcoding processor number. Keep this
in sync with bfd/archures.c in order for machine selection to work. */
#define CPU_R2000 2000
#define CPU_R3000 3000
#define CPU_R3900 3900
--- 303,344 ----
! /* Masks used to mark instructions to indicate which MIPS ISA level
! they were introduced in. ISAs, as defined below, are logical
! ORs of these bits, indicatingthat they support the instructions
! defined at the given level. */
!
! #define INSN_ISA1 0x00000010
! #define INSN_ISA2 0x00000020
! #define INSN_ISA3 0x00000040
! #define INSN_ISA4 0x00000080
! #define INSN_ISA5 0x00000100
! #define INSN_ISA32 0x00000200
/* Chip specific instructions. These are bitmasks. */
/* MIPS R4650 instruction. */
! #define INSN_4650 0x00010000
/* LSI R4010 instruction. */
! #define INSN_4010 0x00020000
/* NEC VR4100 instruction. */
! #define INSN_4100 0x00040000
/* Toshiba R3900 instruction. */
! #define INSN_3900 0x00080000
/* 32-bit code running on a ISA3+ CPU. */
! #define INSN_GP32 0x00100000
!
! /* MIPS ISA defines, use instead of hardcoding ISA level. */
! #define ISA_UNKNOWN 0 /* gas internal use */
! #define ISA_MIPS1 (INSN_ISA1)
! #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
! #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
! #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
! #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
!
/* CPU defines, use instead of hardcoding processor number. Keep this
in sync with bfd/archures.c in order for machine selection to work. */
+ #define CPU_UNKNOWN 0 /* gas internal use */
#define CPU_R2000 2000
#define CPU_R3000 3000
#define CPU_R3900 3900
*************** struct mips_opcode
*** 353,359 ****
#define CPU_R10000 10000
#define CPU_MIPS16 16
#define CPU_MIPS32 32
! #define CPU_4K CPU_MIPS32
/* Test for membership in an ISA including chip specific ISAs.
INSN is pointer to an element of the opcode table; ISA is the
--- 356,362 ----
#define CPU_R10000 10000
#define CPU_MIPS16 16
#define CPU_MIPS32 32
! #define CPU_MIPS32_4K 3204113 /* 32, 04, octal 'K' */
/* Test for membership in an ISA including chip specific ISAs.
INSN is pointer to an element of the opcode table; ISA is the
*************** struct mips_opcode
*** 364,377 ****
in the MIPS gas docs. */
#define OPCODE_IS_MEMBER(insn, isa, cpu, gp32) \
! ((((insn)->membership & INSN_ISA) != 0 \
! && ((insn)->membership & INSN_ISA) <= (unsigned) isa \
&& ((insn)->membership & INSN_GP32 ? gp32 : 1)) \
|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|| ((cpu == CPU_VR4100 || cpu == CPU_R4111) \
&& ((insn)->membership & INSN_4100) != 0) \
- || (cpu == CPU_MIPS32 && ((insn)->membership & INSN_MIPS32) != 0) \
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0))
/* This is a list of macro expanded instructions.
--- 367,378 ----
in the MIPS gas docs. */
#define OPCODE_IS_MEMBER(insn, isa, cpu, gp32) \
! ((((insn)->membership & isa) != 0 \
&& ((insn)->membership & INSN_GP32 ? gp32 : 1)) \
|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|| ((cpu == CPU_VR4100 || cpu == CPU_R4111) \
&& ((insn)->membership & INSN_4100) != 0) \
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0))
/* This is a list of macro expanded instructions.
diff -rcp ../src.P06/opcodes/mips-dis.c ./opcodes/mips-dis.c
*** ../src.P06/opcodes/mips-dis.c Sat Oct 14 22:52:02 2000
--- ./opcodes/mips-dis.c Sat Oct 14 23:16:55 2000
*************** set_mips_isa_type (mach, isa, cputype)
*** 289,296 ****
int *isa;
int *cputype;
{
! int target_processor = 0;
! int mips_isa = 0;
/* Use standard MIPS register names by default. */
reg_names = std_reg_names;
--- 289,296 ----
int *isa;
int *cputype;
{
! int target_processor = CPU_UNKNOWN;
! int mips_isa = ISA_UNKNOWN;
/* Use standard MIPS register names by default. */
reg_names = std_reg_names;
*************** set_mips_isa_type (mach, isa, cputype)
*** 299,369 ****
{
case bfd_mach_mips3000:
target_processor = CPU_R3000;
! mips_isa = 1;
break;
case bfd_mach_mips3900:
target_processor = CPU_R3900;
! mips_isa = 1;
break;
case bfd_mach_mips4000:
target_processor = CPU_R4000;
! mips_isa = 3;
break;
case bfd_mach_mips4010:
target_processor = CPU_R4010;
! mips_isa = 2;
break;
case bfd_mach_mips4100:
target_processor = CPU_VR4100;
! mips_isa = 3;
break;
case bfd_mach_mips4111:
target_processor = CPU_VR4100; /* FIXME: Shouldn't this be CPU_R4111 ??? */
! mips_isa = 3;
break;
case bfd_mach_mips4300:
target_processor = CPU_R4300;
! mips_isa = 3;
break;
case bfd_mach_mips4400:
target_processor = CPU_R4400;
! mips_isa = 3;
break;
case bfd_mach_mips4600:
target_processor = CPU_R4600;
! mips_isa = 3;
break;
case bfd_mach_mips4650:
target_processor = CPU_R4650;
! mips_isa = 3;
! break;
! case bfd_mach_mips4K:
! target_processor = CPU_4K;
! mips_isa = 2;
break;
case bfd_mach_mips5000:
target_processor = CPU_R5000;
! mips_isa = 4;
break;
case bfd_mach_mips6000:
target_processor = CPU_R6000;
! mips_isa = 2;
break;
case bfd_mach_mips8000:
target_processor = CPU_R8000;
! mips_isa = 4;
break;
case bfd_mach_mips10000:
target_processor = CPU_R10000;
! mips_isa = 4;
break;
case bfd_mach_mips16:
target_processor = CPU_MIPS16;
! mips_isa = 3;
break;
default:
target_processor = CPU_R3000;
! mips_isa = 3;
break;
}
--- 299,373 ----
{
case bfd_mach_mips3000:
target_processor = CPU_R3000;
! mips_isa = ISA_MIPS1;
break;
case bfd_mach_mips3900:
target_processor = CPU_R3900;
! mips_isa = ISA_MIPS1;
break;
case bfd_mach_mips4000:
target_processor = CPU_R4000;
! mips_isa = ISA_MIPS3;
break;
case bfd_mach_mips4010:
target_processor = CPU_R4010;
! mips_isa = ISA_MIPS2;
break;
case bfd_mach_mips4100:
target_processor = CPU_VR4100;
! mips_isa = ISA_MIPS3;
break;
case bfd_mach_mips4111:
target_processor = CPU_VR4100; /* FIXME: Shouldn't this be CPU_R4111 ??? */
! mips_isa = ISA_MIPS3;
break;
case bfd_mach_mips4300:
target_processor = CPU_R4300;
! mips_isa = ISA_MIPS3;
break;
case bfd_mach_mips4400:
target_processor = CPU_R4400;
! mips_isa = ISA_MIPS3;
break;
case bfd_mach_mips4600:
target_processor = CPU_R4600;
! mips_isa = ISA_MIPS3;
break;
case bfd_mach_mips4650:
target_processor = CPU_R4650;
! mips_isa = ISA_MIPS3;
break;
case bfd_mach_mips5000:
target_processor = CPU_R5000;
! mips_isa = ISA_MIPS4;
break;
case bfd_mach_mips6000:
target_processor = CPU_R6000;
! mips_isa = ISA_MIPS2;
break;
case bfd_mach_mips8000:
target_processor = CPU_R8000;
! mips_isa = ISA_MIPS4;
break;
case bfd_mach_mips10000:
target_processor = CPU_R10000;
! mips_isa = ISA_MIPS4;
break;
case bfd_mach_mips16:
target_processor = CPU_MIPS16;
! mips_isa = ISA_MIPS3;
! break;
! case bfd_mach_mips32:
! target_processor = CPU_MIPS32;
! mips_isa = ISA_MIPS32;
! break;
! case bfd_mach_mips32_4k:
! target_processor = CPU_MIPS32_4K;
! mips_isa = ISA_MIPS32;
break;
default:
target_processor = CPU_R3000;
! mips_isa = ISA_MIPS3;
break;
}
diff -rcp ../src.P06/opcodes/mips-opc.c ./opcodes/mips-opc.c
*** ../src.P06/opcodes/mips-opc.c Sat Oct 14 22:52:08 2000
--- ./opcodes/mips-opc.c Sat Oct 14 23:12:21 2000
*************** Software Foundation, 59 Temple Place - S
*** 77,84 ****
#define I3 INSN_ISA3
#define I4 INSN_ISA4
#define I5 INSN_ISA5
#define P3 INSN_4650
- #define P4 INSN_MIPS32
#define L1 INSN_4010
#define V1 INSN_4100
#define T3 INSN_3900
--- 77,85 ----
#define I3 INSN_ISA3
#define I4 INSN_ISA4
#define I5 INSN_ISA5
+ #define I32 INSN_ISA32
+
#define P3 INSN_4650
#define L1 INSN_4010
#define V1 INSN_4100
#define T3 INSN_3900
*************** const struct mips_opcode mips_builtin_op
*** 112,120 ****
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
/* name, args, match, mask, pinfo, membership */
! {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3|M1|P4 },
{"nop", "", 0x00000000, 0xffffffff, 0, I1 },
! {"ssnop", "", 0x00000040, 0xffffffff, 0, M1|P4 },
{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 },
--- 113,121 ----
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
/* name, args, match, mask, pinfo, membership */
! {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3|M1|I32 },
{"nop", "", 0x00000000, 0xffffffff, 0, I1 },
! {"ssnop", "", 0x00000040, 0xffffffff, 0, M1|I32 },
{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 },
*************** const struct mips_opcode mips_builtin_op
*** 222,228 ****
{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2 },
{"break", "", 0x0000000d, 0xffffffff, TRAP, I1 },
! {"break", "B", 0x0000000d, 0xfc00003f, TRAP, P4 },
{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 },
{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 },
{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
--- 223,229 ----
{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2 },
{"break", "", 0x0000000d, 0xffffffff, TRAP, I1 },
! {"break", "B", 0x0000000d, 0xfc00003f, TRAP, I32 },
{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 },
{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 },
{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
*************** const struct mips_opcode mips_builtin_op
*** 321,327 ****
{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
! {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|T3|M1|P4 },
{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 },
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 },
{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 },
--- 322,328 ----
{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
! {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|T3|M1|I32 },
{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 },
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 },
{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 },
*************** const struct mips_opcode mips_builtin_op
*** 331,338 ****
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
! {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|RD_s, P4 },
! {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|RD_s, P4 },
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
--- 332,339 ----
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
! {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|RD_s, I32 },
! {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|RD_s, I32 },
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
*************** const struct mips_opcode mips_builtin_op
*** 361,367 ****
/* dctr and dctw are used on the r5000. */
{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 },
{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 },
! {"deret", "", 0x4200001f, 0xffffffff, 0, G2|M1|P4 },
/* For ddiv, see the comments about div. */
{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 },
--- 362,368 ----
/* dctr and dctw are used on the r5000. */
{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 },
{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 },
! {"deret", "", 0x4200001f, 0xffffffff, 0, G2|M1|I32 },
/* For ddiv, see the comments about div. */
{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 },
*************** const struct mips_opcode mips_builtin_op
*** 433,439 ****
{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, I3 },
{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 },
! {"eret", "", 0x42000018, 0xffffffff, 0, I3|M1|P4 },
{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 },
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 },
{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 },
--- 434,440 ----
{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, I3 },
{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 },
! {"eret", "", 0x42000018, 0xffffffff, 0, I3|M1|I32 },
{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 },
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 },
{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 },
*************** const struct mips_opcode mips_builtin_op
*** 530,558 ****
{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, I3 },
{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
! {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3|P4 },
! {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3|P4 },
{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
! {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P4 },
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1|M1 },
{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1 },
{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
! {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P4 },
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1|M1},
{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1},
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, V1 },
{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
! {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, P4 },
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
! {"mfc1", "t,G,H", 0x44000000, 0xffe007f8, LCD|WR_t|RD_S|FP_S, P4},
{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
! {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, P4 },
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
! {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, P4 },
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 },
{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 },
--- 531,559 ----
{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, I3 },
{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
! {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3|I32 },
! {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3|I32 },
{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
! {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, I32 },
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1|M1 },
{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1 },
{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
! {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, I32 },
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1|M1},
{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1},
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, V1 },
{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
! {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 },
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
! {"mfc1", "t,G,H", 0x44000000, 0xffe007f8, LCD|WR_t|RD_S|FP_S, I32},
{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
! {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32 },
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
! {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32 },
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 },
{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 },
*************** const struct mips_opcode mips_builtin_op
*** 562,568 ****
{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|M1 },
{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|M1 },
{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
! {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|P4 },
{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s,L1 },
{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|M1 },
{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|M1 },
--- 563,569 ----
{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|M1 },
{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|M1 },
{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
! {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|I32 },
{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s,L1 },
{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|M1 },
{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|M1 },
*************** const struct mips_opcode mips_builtin_op
*** 570,576 ****
{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|M1 },
{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|M1 },
{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5},
! {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|P4 },
{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s,L1 },
{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|M1 },
{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|M1 },
--- 571,577 ----
{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|M1 },
{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|M1 },
{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5},
! {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|I32 },
{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s,L1 },
{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|M1 },
{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|M1 },
*************** const struct mips_opcode mips_builtin_op
*** 579,602 ****
{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 },
! {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P4 },
{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 },
! {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P4 },
{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 },
! {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, P4 },
{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
! {"mtc1", "t,G,H", 0x44800000, 0xffe007f8, COD|RD_t|WR_S|FP_S, P4 },
{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 },
! {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, P4 },
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 },
! {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, P4 },
{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 },
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 },
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
! {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, P3|P4 },
{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 },
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 },
{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 },
--- 580,603 ----
{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 },
! {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, I32 },
{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 },
! {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, I32 },
{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 },
! {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 },
{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
! {"mtc1", "t,G,H", 0x44800000, 0xffe007f8, COD|RD_t|WR_S|FP_S, I32 },
{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 },
! {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I32 },
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 },
! {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I32 },
{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 },
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 },
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
! {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, P3|I32 },
{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 },
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 },
{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 },
*************** const struct mips_opcode mips_builtin_op
*** 666,672 ****
{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2|M1 },
{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2|M1 },
{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2|M1 },
! {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, P4 },
{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 },
--- 667,673 ----
{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2|M1 },
{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2|M1 },
{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2|M1 },
! {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, I32 },
{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 },
*************** const struct mips_opcode mips_builtin_op
*** 774,783 ****
{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */
{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, I2 },
! {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1|M1|P4 },
! {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1|M1|P4 },
! {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1|M1|P4 },
! {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1|M1|P4 },
{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 },
{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
--- 775,784 ----
{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */
{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, I2 },
! {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1|M1|I32 },
! {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1|M1|I32 },
! {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1|M1|I32 },
! {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1|M1|I32 },
{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 },
{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
*************** const struct mips_opcode mips_builtin_op
*** 818,825 ****
{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
! {"wait", "", 0x42000020, 0xffffffff, TRAP, I3|M1|P4 },
! {"wait", "J", 0x42000020, 0xfe00003f, TRAP, P4 },
{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },
/* No hazard protection on coprocessor instructions--they shouldn't
--- 819,826 ----
{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
! {"wait", "", 0x42000020, 0xffffffff, TRAP, I3|M1|I32 },
! {"wait", "J", 0x42000020, 0xfe00003f, TRAP, I32 },
{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },
/* No hazard protection on coprocessor instructions--they shouldn't