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[patch] MIPS64 opcodes and a few minor related fixes.
- To: binutils at sourceware dot cygnus dot com
- Subject: [patch] MIPS64 opcodes and a few minor related fixes.
- From: cgd at sibyte dot com (Chris G. Demetriou)
- Date: 25 Oct 2000 23:53:28 -0700
Yet another extraction from our source tree: MIPS64 opcodes, and a
test for the extensions.
Along the way I noticed a few problems, which are also fixed here, notably:
(1) the dm[ft]c2 ops used an 'S' arg specifier rather than 'G' --
"uh, wrong." 8-)
(2) there were m[ft]c3 ops, but no corresponding dm[ft]c3 ops.
(3) there are 'G'-operand variants of the m[ft]c1 ops, but not of the
dm[ft]c1 ops. unnecessary limitation.
(4) My previous patches added 'sel' variants for mfc1. I checked the
ISA manual, and those aren't defined. There's no real harm to have
them, but there's no defined need for them and the FPU _is_
well-defined, so i've pulled them. (The particular patch at fault was
http://sources.redhat.com/ml/binutils/2000-10/msg00097.html.)
On account of the latter, i'm definitely willing to regen that patch
and the following ones (as necessary) if desired ... but you've gotta
review them first! ("muhahaha!")
made check on mips-elf, mips64-elf, and mips-linux, host sparc-solaris
to the tune of ... NO new failures! patches below apply on top of
previous, la la la la. 8-)
chris
=============================================================================
for opcodes/ChangeLog:
2000-10-25 Chris Demetriou <cgd@sibyte.com>
* mips-opc.c (mips_builtin_opcodes): The dmfc2 and dmtc2
instructions take "G" format second operands.
* mips-opc.c (mips_builtin_opcodes): There are mfc3 and
mtc3 opcodes, so add dmfc3 and dmtc3 opcodes to match.
* mips-opc.c (mips_builtin_opcodes): Delete "sel" code
operands from mfc1 and mtc1.
* mips-opc.c (mips_builtin_opcodes): Add MIPS64 opcode
changes (dclo, dclz), and "sel" codes for dm[ft]c[023].
for gas/testsuite/ChangeLog:
2000-10-25 Chris Demetriou <cgd@sibyte.com>
* gas/mips/mips64.s: Add test for assembly of MIPS64
extensions.
* gas/mips/mips64.d: Likewise.
* gas/mips/mips.exp: Test using the new "mips64" test.
diff -rcN ../src.P14/gas/testsuite/gas/mips/mips.exp ./gas/testsuite/gas/mips/mips.exp
*** ../src.P14/gas/testsuite/gas/mips/mips.exp Mon Oct 16 15:57:55 2000
--- ./gas/testsuite/gas/mips/mips.exp Wed Oct 25 23:05:25 2000
***************
*** 89,94 ****
--- 89,95 ----
run_dump_test "lineno"
run_dump_test "sync"
run_dump_test "mips32"
+ run_dump_test "mips64"
# Make sure that -mcpu=FOO and -mFOO are equivalent. Assemble a file
# containing 4650-specific instructions with -m4650 and -mcpu=4650,
diff -rcN ../src.P14/gas/testsuite/gas/mips/mips64.d ./gas/testsuite/gas/mips/mips64.d
*** ../src.P14/gas/testsuite/gas/mips/mips64.d Wed Dec 31 16:00:00 1969
--- ./gas/testsuite/gas/mips/mips64.d Wed Oct 25 23:07:42 2000
***************
*** 0 ****
--- 1,17 ----
+ #objdump: -dr --prefix-addresses --show-raw-insn
+ #name: MIPS MIPS64 instructions
+ #as: -mips64
+
+ # Check MIPS32 instruction assembly
+
+ .*: +file format elf.*mips.*
+
+ Disassembly of section .text:
+ 0+0000 <[^>]*> 70410825 dclo \$at,\$v0
+ 0+0004 <[^>]*> 70831824 dclz \$v1,\$a0
+ 0+0008 <[^>]*> 48232000 dmfc2 \$v1,\$4
+ 0+000c <[^>]*> 48242800 dmfc2 \$a0,\$5
+ 0+0010 <[^>]*> 48253007 dmfc2 \$a1,\$6,7
+ 0+0014 <[^>]*> 48a63800 dmtc2 \$a2,\$7
+ 0+0018 <[^>]*> 48a74000 dmtc2 \$a3,\$8
+ 0+001c <[^>]*> 48a84807 dmtc2 \$t0,\$9,7
diff -rcN ../src.P14/gas/testsuite/gas/mips/mips64.s ./gas/testsuite/gas/mips/mips64.s
*** ../src.P14/gas/testsuite/gas/mips/mips64.s Wed Dec 31 16:00:00 1969
--- ./gas/testsuite/gas/mips/mips64.s Wed Oct 25 23:01:23 2000
***************
*** 0 ****
--- 1,22 ----
+ # source file to test assembly of mips64 instructions
+
+ .set noreorder
+ .set noat
+
+ .globl text_label .text
+ text_label:
+
+ # unprivileged CPU instructions
+
+ dclo $1, $2
+ dclz $3, $4
+
+ # unprivileged coprocessor instructions.
+ # these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
+
+ dmfc2 $3, $4
+ dmfc2 $4, $5, 0 # disassembles without sel
+ dmfc2 $5, $6, 7
+ dmtc2 $6, $7
+ dmtc2 $7, $8, 0 # disassembles without sel
+ dmtc2 $8, $9, 7
diff -rcN ../src.P14/opcodes/mips-opc.c ./opcodes/mips-opc.c
*** ../src.P14/opcodes/mips-opc.c Wed Oct 25 22:11:01 2000
--- ./opcodes/mips-opc.c Wed Oct 25 23:12:40 2000
***************
*** 360,365 ****
--- 360,367 ----
{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 },
{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, I3 },
+ {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, I64 },
+ {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, I64 },
/* dctr and dctw are used on the r5000. */
{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 },
{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 },
***************
*** 395,405 ****
{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, V1 },
{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 },
{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 },
{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
! {"dmfc2", "t,S", 0x48200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
! {"dmtc2", "t,S", 0x48a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, I3 },
{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, I3 },
{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, I3 },
--- 397,417 ----
{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, V1 },
{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 },
+ {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, I64 },
{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 },
+ {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I64 },
{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
+ {"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
! {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
! {"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
! {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_S|FP_S, I64 },
! {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
! {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_S|FP_S, I64 },
! {"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
! {"dmfc3", "t,G,H", 0x4c200000, 0xffe007f8, LCD|WR_t|RD_S|FP_S, I64 },
! {"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
! {"dmtc3", "t,G,H", 0x4ca00000, 0xffe007f8, COD|RD_t|WR_S|FP_S, I64 },
{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, I3 },
{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, I3 },
{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, I3 },
***************
*** 550,556 ****
{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 },
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
- {"mfc1", "t,G,H", 0x44000000, 0xffe007f8, LCD|WR_t|RD_S|FP_S, I32},
{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32 },
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
--- 562,567 ----
***************
*** 588,594 ****
{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 },
{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
- {"mtc1", "t,G,H", 0x44800000, 0xffe007f8, COD|RD_t|WR_S|FP_S, I32 },
{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 },
{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I32 },
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 },
--- 599,604 ----