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[PATCH] Performance counter opcodes for MIPS R1[02]000
- To: binutils at sources dot redhat dot com
- Subject: [PATCH] Performance counter opcodes for MIPS R1[02]000
- From: Thiemo Seufer <ica2_ts at csv dot ica dot uni-stuttgart dot de>
- Date: Wed, 30 May 2001 03:50:06 +0200
Hi All,
this patch adds the performance counter opcodes for R1[02]000
(mtpc, mfpc mtps, mfps) and fixes the naming of coprocessor
registers.
Thiemo
2001-05-30 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
/gas/testsuite/ChangeLog
* gas/mips/mips32.d: Update to use hardware names for coprocessor
registers.
* gas/mips/mips64.d: Likewise.
/include/opcode/ChangeLog
* mips.h (INSN_10000): Define.
(OPCODE_IS_MEMBER): Add check for R1[02]000.
/opcodes/ChangeLog
* mips-dis.c (print_insn_arg): Don't use (wrong) symbolic names for
coprocessor registers.
* mips-opc.c (M1): Define.
(mips_builtin_opcodes): Add performance counter insns. Typo.
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/gas/testsuite/gas/mips/mips32.d src/gas/testsuite/gas/mips/mips32.d
--- src-orig/gas/testsuite/gas/mips/mips32.d Tue May 15 16:33:53 2001
+++ src/gas/testsuite/gas/mips/mips32.d Wed May 30 03:28:03 2001
@@ -26,15 +26,15 @@
0+0040 <[^>]*> 00000000 nop
0+0044 <[^>]*> 4903ffee bc2tl 0+0000 <text_label>
0+0048 <[^>]*> 00000000 nop
-0+004c <[^>]*> 48411000 cfc2 at,v0
+0+004c <[^>]*> 48411000 cfc2 at,$2
0+0050 <[^>]*> 4b234567 c2 0x1234567
-0+0054 <[^>]*> 48c21800 ctc2 v0,v1
-0+0058 <[^>]*> 48032000 mfc2 v1,a0
-0+005c <[^>]*> 48042800 mfc2 a0,a1
-0+0060 <[^>]*> 48053007 mfc2 a1,a2,7
-0+0064 <[^>]*> 48863800 mtc2 a2,a3
-0+0068 <[^>]*> 48874000 mtc2 a3,t0
-0+006c <[^>]*> 48884807 mtc2 t0,t1,7
+0+0054 <[^>]*> 48c21800 ctc2 v0,$3
+0+0058 <[^>]*> 48032000 mfc2 v1,$4
+0+005c <[^>]*> 48042800 mfc2 a0,$5
+0+0060 <[^>]*> 48053007 mfc2 a1,$6,7
+0+0064 <[^>]*> 48863800 mtc2 a2,$7
+0+0068 <[^>]*> 48874000 mtc2 a3,$8
+0+006c <[^>]*> 48884807 mtc2 t0,$9,7
0+0070 <[^>]*> bc250000 cache 0x5,0\(at\)
0+0074 <[^>]*> bc457fff cache 0x5,32767\(v0\)
0+0078 <[^>]*> bc658000 cache 0x5,-32768\(v1\)
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/gas/testsuite/gas/mips/mips64.d src/gas/testsuite/gas/mips/mips64.d
--- src-orig/gas/testsuite/gas/mips/mips64.d Tue May 15 16:33:53 2001
+++ src/gas/testsuite/gas/mips/mips64.d Wed May 30 03:30:07 2001
@@ -9,9 +9,9 @@
Disassembly of section .text:
0+0000 <[^>]*> 70410825 dclo at,v0
0+0004 <[^>]*> 70831824 dclz v1,a0
-0+0008 <[^>]*> 48232000 dmfc2 v1,a0
-0+000c <[^>]*> 48242800 dmfc2 a0,a1
-0+0010 <[^>]*> 48253007 dmfc2 a1,a2,7
-0+0014 <[^>]*> 48a63800 dmtc2 a2,a3
-0+0018 <[^>]*> 48a74000 dmtc2 a3,t0
-0+001c <[^>]*> 48a84807 dmtc2 t0,t1,7
+0+0008 <[^>]*> 48232000 dmfc2 v1,$4
+0+000c <[^>]*> 48242800 dmfc2 a0,$5
+0+0010 <[^>]*> 48253007 dmfc2 a1,$6,7
+0+0014 <[^>]*> 48a63800 dmtc2 a2,$7
+0+0018 <[^>]*> 48a74000 dmtc2 a3,$8
+0+001c <[^>]*> 48a84807 dmtc2 t0,$9,7
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/include/opcode/mips.h src/include/opcode/mips.h
--- src-orig/include/opcode/mips.h Wed May 23 21:09:08 2001
+++ src/include/opcode/mips.h Tue May 29 23:32:43 2001
@@ -326,8 +326,10 @@
#define INSN_4100 0x00040000
/* Toshiba R3900 instruction. */
#define INSN_3900 0x00080000
+/* MIPS R1[02]000 instruction. */
+#define INSN_10000 0x00100000
/* 32-bit code running on a ISA3+ CPU. */
-#define INSN_GP32 0x00100000
+#define INSN_GP32 0x00200000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@@ -382,7 +384,9 @@
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|| ((cpu == CPU_VR4100 || cpu == CPU_R4111) \
&& ((insn)->membership & INSN_4100) != 0) \
- || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0))
+ || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
+ || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
+ && ((insn)->membership & INSN_10000) != 0))
/* This is a list of macro expanded instructions.
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/opcodes/mips-dis.c src/opcodes/mips-dis.c
--- src-orig/opcodes/mips-dis.c Wed May 23 21:09:17 2001
+++ src/opcodes/mips-dis.c Tue May 29 23:32:43 2001
@@ -256,13 +256,13 @@
break;
case 'E':
- (*info->fprintf_func) (info->stream, "%s",
- reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
+ (*info->fprintf_func) (info->stream, "$%d",
+ (l >> OP_SH_RT) & OP_MASK_RT);
break;
case 'G':
- (*info->fprintf_func) (info->stream, "%s",
- reg_names[(l >> OP_SH_RD) & OP_MASK_RD]);
+ (*info->fprintf_func) (info->stream, "$%d",
+ (l >> OP_SH_RD) & OP_MASK_RD);
break;
case 'N':
@@ -276,7 +276,7 @@
break;
case 'P':
- (*info->fprintf_func) (info->stream, "%d",
+ (*info->fprintf_func) (info->stream, "$%d",
(l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
break;
diff -BurPX /bigdisk/dl/src/binutils-exclude src-orig/opcodes/mips-opc.c src/opcodes/mips-opc.c
--- src-orig/opcodes/mips-opc.c Wed Apr 4 18:37:02 2001
+++ src/opcodes/mips-opc.c Tue May 29 23:32:43 2001
@@ -86,15 +86,16 @@
#define L1 INSN_4010
#define V1 INSN_4100
#define T3 INSN_3900
+#define M1 INSN_10000
#define G1 (T3 \
)
-#define G2 (T3 \
+#define G2 (T3 \
)
-#define G3 (I4 \
- )
+#define G3 (I4 \
+ )
#define G6 INSN_GP32
@@ -568,6 +569,8 @@
{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32 },
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 },
+{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 },
+{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 },
{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 },
{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 },
{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, I5 },
@@ -605,6 +608,8 @@
{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I32 },
{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 },
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 },
+{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, M1 },
+{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, M1 },
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
@@ -838,7 +843,7 @@
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
- disasembler recognizes more specific versions first. */
+ disassembler recognizes more specific versions first. */
{"c0", "C", 0x42000000, 0xfe000000, 0, I1 },
{"c1", "C", 0x46000000, 0xfe000000, 0, I1 },
{"c2", "C", 0x4a000000, 0xfe000000, 0, I1 },