Re: binutils patch

[Daniel Egger <egger at suse dot de>]

Am 17 Aug 2001 13:19:09 +0200 schrieb Andreas Schwab:

> I think you want an XT macro that lets you specify the T bit in the
> opcode:

I had this one before but it seems I did something wrong because it also
didn't work.
 
> #define XT(op, xop, t) (X (op, xop) | (((unsigned long)(t) & 1) << 25))
> #define T_MASK ((unsigned long)1 << 25)
> #define XT_MASK (X_MASK | T_MASK)
> 
> { "dss",     XT(31,822,0), XT_MASK,	PPCVEC,		{ STRM } },
> { "dssall",  XT(31,822,1), XT_MASK,	PPCVEC,		{ STRM } },
> { "dst",     XT(31,342,0), XT_MASK,	PPCVEC,		{ RA, RB, STRM } },
> { "dstt",    XT(31,342,1), XT_MASK,	PPCVEC,		{ RA, RB, STRM } },
> { "dstst",   XT(31,374,0), XT_MASK,	PPCVEC,		{ RA, RB, STRM } },
> { "dststt",  XT(31,374,1), XT_MASK,	PPCVEC,		{ RA, RB, STRM } },

Actually the XT_MASK is bogus because this is a valid X form opcode,
it's just that I didn't understand what the macros really do. After
hacking in a similar version of your suggestion the code worked
correctly:
     fe8:       7e 04 02 ec     dstst   r4,r0,0
     fec:       3d 20 01 08     lis     r9,264
     ff0:       61 29 00 10     ori     r9,r9,16
     ff4:       7c 23 4a ac     dst     r3,r9,1

I'm attaching a cleanup version of the patch, can this one please be
considered for inclusion into the official binutils? I'll also prepare
a patch for SuSE.

Servus,
       Daniel

--- opcodes/ppc-opc.c.orig	Thu Aug  9 16:16:28 2001
+++ opcodes/ppc-opc.c	Fri Aug 17 15:02:39 2001
@@ -375,8 +375,12 @@
 #define SR SPRG + 1
   { 4, 16, 0, 0, 0 },
 
+  /* The STRM field in an X form instruction.  */
+#define STRM SR + 1
+  { 2, 21, 0, 0, 0 },
+
   /* The SV field in a POWER SC form instruction.  */
-#define SV SR + 1
+#define SV STRM + 1
   { 14, 2, 0, 0, 0 },
 
   /* The TBR field in an XFX form instruction.  This is like the SPR
@@ -1162,6 +1166,9 @@
 /* An X form instruction with the RC bit specified.  */
 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
 
+/* An X form instruction with the T bit specified.  */
+#define XT(op, xop, t) (X (op, xop) | (((unsigned long) (t) & 1) << 25))
+
 /* The mask for an X form instruction.  */
 #define X_MASK XRC (0x3f, 0x3ff, 1)
 
@@ -3199,6 +3206,13 @@
 
 { "dcbz",    X(31,1014), XRT_MASK,	PPC,		{ RA, RB } },
 { "dclz",    X(31,1014), XRT_MASK,	PPC,		{ RA, RB } },
+
+{ "dssall",  XT(31,822,1), X_MASK,	PPCVEC,		{ STRM } },
+{ "dss",     XT(31,822,0), X_MASK,	PPCVEC,		{ STRM } },
+{ "dstt",    XT(31,342,1), X_MASK,	PPCVEC,		{ RA, RB, STRM } },
+{ "dst",     XT(31,342,0), X_MASK,	PPCVEC,		{ RA, RB, STRM } },
+{ "dststt",  XT(31,374,1), X_MASK,	PPCVEC,		{ RA, RB, STRM } },
+{ "dstst",   XT(31,374,0), X_MASK,	PPCVEC,		{ RA, RB, STRM } },
 
 { "lvebx",   X(31,   7), X_MASK,	PPCVEC,		{ VD, RA, RB } },
 { "lvehx",   X(31,  39), X_MASK,	PPCVEC,		{ VD, RA, RB } },