This is the mail archive of the binutils@sources.redhat.com mailing list for the binutils project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]

[PATCH] a couple of tweaks to opcodes/mips.h


How about these tweaks to opcodes/mips.h:

2001-10-17  Chris Demetriou  <cgd@broadcom.com>

	* mips.h: Sort coprocessor instruction argument characters.
	(OPCODE_IS_MEMBER): Add no-op term to the expression, for
	easier source code merging.

(I don't know that the latter is "OK" by the coding standards, but it
sure is a pain to have to have to slightly tweak the OPCODE_IS_MEMBER
changes at almost every source code merge.  I'm sure others feel this
pain.  8-)


chris
===================================================================
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.19
diff -u -r1.19 mips.h
--- mips.h	2001/08/31 21:21:54	1.19
+++ mips.h	2001/10/17 19:04:35
@@ -209,8 +209,8 @@
    Coprocessor instructions:
    "E" 5 bit target register (OP_*_RT)
    "G" 5 bit destination register (OP_*_RD)
+   "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
    "P" 5 bit performance-monitor register (OP_*_PERFREG)
-   "H" 3 bit sel field (OP_*_SEL)
 
    Macro instructions:
    "A" General 32 bit expression
@@ -378,7 +378,8 @@
 	 && ((insn)->membership & INSN_4100) != 0)			\
      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)	\
      || ((cpu == CPU_R10000 || cpu == CPU_R12000)			\
-	 && ((insn)->membership & INSN_10000) != 0))
+	 && ((insn)->membership & INSN_10000) != 0)			\
+     || 0)
 
 /* This is a list of macro expanded instructions.
 


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]