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Merging of various patches for d10v gas
- From: Alan Matsuoka <alanm at cygnus dot com>
- To: binutils at sources dot redhat dot com
- Date: Tue, 11 Dec 2001 12:53:12 -0500
- Subject: Merging of various patches for d10v gas
- Organization: Red Hat Canada
The following patches are from various fixes that have been floating
around and have not been merged back into the head.
2001-06-22 Diego Novillo <dnovillo@redhat.com>
* config/tc-d10v.c (check_resource_conflict): Only check
write-write conflicts.
(md_assemble): Reformat introductory comment.
2001-06-08 Jason Eckhardt <jle@cygnus.com>
* config/tc-d10v.c (build_insn): Check for unresolved imm4 or
imm3 fields.
2001-04-11 Jason Eckhardt <jle@cygnus.com>
* config/tc-d10v.c (find_opcode): Emit a warning if one of the
reserved control registers is used.
2000-04-12 Nick Clifton <nickc@cygnus.com>
* config/tc-d10v.c (find_opcode): Correctly calculate position of
symbol in frag chain.
2000-02-17 Nick Clifton <nickc@cygnus.com>
* config/tc-d10v.c (find_opcode): Add a symbol's value to
the computed frag offset, rather than overwriting it.
2000-12-04 Matthew Hiller <hiller@redhat.com>
* config/tc-d10v.c (parallel_ok): Fixed detection of branch
instructions.
Index: config/tc-d10v.c
===================================================================
RCS file: /cvs/cvsfiles/devo/gas/config/tc-d10v.c,v
retrieving revision 1.78
diff -d -c -p -b -w -B -r1.78 tc-d10v.c
*** tc-d10v.c 2001/12/04 17:29:45 1.78
--- tc-d10v.c 2001/12/11 15:33:06
***************
*** 1,6 ****
/* tc-d10v.c -- Assembler code for the Mitsubishi D10V
! Copyright 1996, 1997, 1998, 1999, 2000, 2001
! Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
--- 1,5 ----
/* tc-d10v.c -- Assembler code for the Mitsubishi D10V
! Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation.
This file is part of GAS, the GNU Assembler.
***************
*** 20,31 ****
Boston, MA 02111-1307, USA. */
#include <stdio.h>
#include "as.h"
- #include "safe-ctype.h"
#include "subsegs.h"
#include "opcode/d10v.h"
#include "elf/ppc.h"
- //#include "read.h"
const char comment_chars[] = ";";
const char line_comment_chars[] = "#";
--- 19,29 ----
Boston, MA 02111-1307, USA. */
#include <stdio.h>
+ #include <ctype.h>
#include "as.h"
#include "subsegs.h"
#include "opcode/d10v.h"
#include "elf/ppc.h"
const char comment_chars[] = ";";
const char line_comment_chars[] = "#";
*************** int Optimizing = 0;
*** 42,48 ****
&& S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT)
#define AT_WORD_RIGHT_SHIFT 2
! /* Fixups. */
#define MAX_INSN_FIXUPS (5)
struct d10v_fixup
{
--- 40,47 ----
&& S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT)
#define AT_WORD_RIGHT_SHIFT 2
!
! /* fixups */
#define MAX_INSN_FIXUPS (5)
struct d10v_fixup
{
*************** static Fixups *fixups;
*** 66,86 ****
static int do_not_ignore_hash = 0;
typedef int packing_type;
! #define PACK_UNSPEC (0) /* Packing order not specified. */
#define PACK_PARALLEL (1) /* "||" */
#define PACK_LEFT_RIGHT (2) /* "->" */
#define PACK_RIGHT_LEFT (3) /* "<-" */
! static packing_type etype = PACK_UNSPEC; /* Used by d10v_cleanup. */
! /* True if instruction swapping warnings should be inhibited.
! --nowarnswap. */
! static boolean flag_warn_suppress_instructionswap;
/* True if instruction packing should be performed when --gstabs is specified.
--gstabs-packing, --no-gstabs-packing. */
! static boolean flag_allow_gstabs_packing = 1;
! /* Local functions. */
static int reg_name_search PARAMS ((char *name));
static int register_name PARAMS ((expressionS *expressionP));
static int check_range PARAMS ((unsigned long num, int bits, int flags));
--- 65,84 ----
static int do_not_ignore_hash = 0;
typedef int packing_type;
! #define PACK_UNSPEC (0) /* packing order not specified */
#define PACK_PARALLEL (1) /* "||" */
#define PACK_LEFT_RIGHT (2) /* "->" */
#define PACK_RIGHT_LEFT (3) /* "<-" */
! static packing_type etype = PACK_UNSPEC; /* used by d10v_cleanup */
! /* True if instruction swapping warnings should be inhibited. */
! static unsigned char flag_warn_suppress_instructionswap; /* --nowarnswap. */
/* True if instruction packing should be performed when --gstabs is specified.
--gstabs-packing, --no-gstabs-packing. */
! static unsigned char flag_allow_gstabs_packing = 1;
! /* local functions */
static int reg_name_search PARAMS ((char *name));
static int register_name PARAMS ((expressionS *expressionP));
static int check_range PARAMS ((unsigned long num, int bits, int flags));
*************** static bfd_reloc_code_real_type get_relo
*** 89,95 ****
static int get_operands PARAMS ((expressionS exp[]));
static struct d10v_opcode *find_opcode PARAMS ((struct d10v_opcode *opcode, expressionS ops[]));
static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers, unsigned long insn));
! static void write_long PARAMS ((unsigned long insn, Fixups *fx));
static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
struct d10v_opcode *opcode2, unsigned long insn2, packing_type exec_type, Fixups *fx));
--- 87,93 ----
static int get_operands PARAMS ((expressionS exp[]));
static struct d10v_opcode *find_opcode PARAMS ((struct d10v_opcode *opcode, expressionS ops[]));
static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers, unsigned long insn));
! static void write_long PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
struct d10v_opcode *opcode2, unsigned long insn2, packing_type exec_type, Fixups *fx));
*************** static unsigned long d10v_insert_operand
*** 99,104 ****
--- 97,104 ----
static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
struct d10v_opcode *opcode2, unsigned long insn2,
packing_type exec_type));
+ static void check_resource_conflict PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
+ struct d10v_opcode *opcode2, unsigned long insn2));
static symbolS * find_symbol_matching_register PARAMS ((expressionS *));
struct option md_longopts[] =
*************** const pseudo_typeS md_pseudo_table[] =
*** 128,136 ****
/* Opcode hash table. */
static struct hash_control *d10v_hash;
! /* Do a binary search of the d10v_predefined_registers array to see if
! NAME is a valid regiter name. Return the register number from the
! array on success, or -1 on failure. */
static int
reg_name_search (name)
--- 127,135 ----
/* Opcode hash table. */
static struct hash_control *d10v_hash;
! /* reg_name_search does a binary search of the d10v_predefined_registers
! array to see if "name" is a valid regiter name. Returns the register
! number from the array on success, or -1 on failure. */
static int
reg_name_search (name)
*************** reg_name_search (name)
*** 157,164 ****
return -1;
}
! /* Check the string at input_line_pointer
! to see if it is a valid register name. */
static int
register_name (expressionP)
--- 156,163 ----
return -1;
}
! /* register_name() checks the string at input_line_pointer
! to see if it is a valid register name */
static int
register_name (expressionP)
*************** register_name (expressionP)
*** 167,186 ****
int reg_number;
char c, *p = input_line_pointer;
! while (*p
! && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')')
p++;
c = *p;
if (c)
*p++ = 0;
! /* Look to see if it's in the register table. */
reg_number = reg_name_search (input_line_pointer);
if (reg_number >= 0)
{
expressionP->X_op = O_register;
! /* Temporarily store a pointer to the string here. */
expressionP->X_op_symbol = (symbolS *) input_line_pointer;
expressionP->X_add_number = reg_number;
input_line_pointer = p;
--- 166,184 ----
int reg_number;
char c, *p = input_line_pointer;
! while (*p && *p!='\n' && *p!='\r' && *p !=',' && *p!=' ' && *p!=')')
p++;
c = *p;
if (c)
*p++ = 0;
! /* look to see if it's in the register table */
reg_number = reg_name_search (input_line_pointer);
if (reg_number >= 0)
{
expressionP->X_op = O_register;
! /* temporarily store a pointer to the string here */
expressionP->X_op_symbol = (symbolS *)input_line_pointer;
expressionP->X_add_number = reg_number;
input_line_pointer = p;
*************** check_range (num, bits, flags)
*** 197,213 ****
int bits;
int flags;
{
! long min, max;
int retval = 0;
! /* Don't bother checking 16-bit values. */
if (bits == 16)
return 0;
if (flags & OPERAND_SHIFT)
{
! /* All special shift operands are unsigned and <= 16.
! We allow 0 for now. */
if (num > 16)
return 1;
else
--- 196,212 ----
int bits;
int flags;
{
! long min, max, bit1;
int retval=0;
! /* don't bother checking 16-bit values */
if (bits == 16)
return 0;
if (flags & OPERAND_SHIFT)
{
! /* all special shift operands are unsigned */
! /* and <= 16. We allow 0 for now. */
if (num>16)
return 1;
else
*************** check_range (num, bits, flags)
*** 216,222 ****
if (flags & OPERAND_SIGNED)
{
! /* Signed 3-bit integers are restricted to the (-2, 3) range. */
if (flags & RESTRICTED_NUM3)
{
if ((long) num < -2 || (long) num > 3)
--- 215,221 ----
if (flags & OPERAND_SIGNED)
{
! /* Signed 3-bit integers are restricted to the (-2, 3) range */
if (flags & RESTRICTED_NUM3)
{
if ((long) num < -2 || (long) num > 3)
*************** check_range (num, bits, flags)
*** 234,240 ****
{
max = (1 << bits) - 1;
min = 0;
! if (((long) num > max) || ((long) num < min))
retval = 1;
}
return retval;
--- 233,239 ----
{
max = (1 << bits) - 1;
min = 0;
! if ((num > max) || (num < min))
retval = 1;
}
return retval;
*************** md_show_usage (stream)
*** 245,266 ****
FILE *stream;
{
fprintf (stream, _("D10V options:\n\
! -O Optimize. Will do some operations in parallel.\n\
! --gstabs-packing Pack adjacent short instructions together even\n\
when --gstabs is specified. On by default.\n\
! --no-gstabs-packing If --gstabs is specified, do not pack adjacent\n\
! instructions together.\n"));
}
int
md_parse_option (c, arg)
int c;
! char *arg ATTRIBUTE_UNUSED;
{
switch (c)
{
case 'O':
! /* Optimize. Will attempt to parallelize operations. */
Optimizing = 1;
break;
case OPTION_NOWARNSWAP:
--- 245,266 ----
FILE *stream;
{
fprintf(stream, _("D10V options:\n\
! -O optimize. Will do some operations in parallel.\n\
! --gstabs-packing pack adjacent short instructions together even\n\
when --gstabs is specified. On by default.\n\
! --no-gstabs-packing if --gstabs is specified, do not pack adjacent\n\
! instructions together\n"));
}
int
md_parse_option (c, arg)
int c;
! char *arg;
{
switch (c)
{
case 'O':
! /* Optimize. Will attempt to parallelize operations */
Optimizing = 1;
break;
case OPTION_NOWARNSWAP:
*************** md_parse_option (c, arg)
*** 280,295 ****
symbolS *
md_undefined_symbol (name)
! char *name ATTRIBUTE_UNUSED;
{
return 0;
}
! /* Turn a string in input_line_pointer into a floating point constant
! of type TYPE, and store the appropriate bytes in *LITP. The number
! of LITTLENUMS emitted is stored in *SIZEP. An error message is
! returned, or NULL on OK. */
!
char *
md_atof (type, litP, sizeP)
int type;
--- 280,294 ----
symbolS *
md_undefined_symbol (name)
! char *name;
{
return 0;
}
! /* Turn a string in input_line_pointer into a floating point constant of type
! type, and store the appropriate bytes in *litP. The number of LITTLENUMS
! emitted is stored in *sizeP . An error message is returned, or NULL on OK.
! */
char *
md_atof (type, litP, sizeP)
int type;
*************** md_atof (type, litP, sizeP)
*** 330,338 ****
void
md_convert_frag (abfd, sec, fragP)
! bfd *abfd ATTRIBUTE_UNUSED;
! asection *sec ATTRIBUTE_UNUSED;
! fragS *fragP ATTRIBUTE_UNUSED;
{
abort ();
}
--- 329,337 ----
void
md_convert_frag (abfd, sec, fragP)
! bfd *abfd;
! asection *sec;
! fragS *fragP;
{
abort ();
}
*************** md_begin ()
*** 372,382 ****
FixUps[1].next = &FixUps[0];
}
- /* Remove the postincrement or postdecrement operator ( '+' or '-' )
- from an expression. */
! static int
! postfix (p)
char *p;
{
while (*p != '-' && *p != '+')
--- 372,382 ----
FixUps[1].next = &FixUps[0];
}
! /* this function removes the postincrement or postdecrement
! operator ( '+' or '-' ) from an expression */
!
! static int postfix (p)
char *p;
{
while (*p != '-' && *p != '+')
*************** get_reloc (op)
*** 420,427 ****
return (BFD_RELOC_16);
}
- /* Parse a string of operands. Return an array of expressions. */
static int
get_operands (exp)
expressionS exp[];
--- 421,430 ----
return (BFD_RELOC_16);
}
+ /* get_operands parses a string of operands and returns
+ an array of expressions */
+
static int
get_operands (exp)
expressionS exp[];
*************** get_operands (exp)
*** 470,486 ****
if (*p == ')')
{
! /* Just skip the trailing paren. */
p++;
continue;
}
input_line_pointer = p;
! /* Check to see if it might be a register name. */
if (!register_name (&exp[numops]))
{
! /* Parse as an expression. */
if (uses_at)
{
/* Any expression that involves the indirect addressing
--- 473,489 ----
if (*p == ')')
{
! /* just skip the trailing paren */
p++;
continue;
}
input_line_pointer = p;
! /* check to see if it might be a register name */
if (!register_name (&exp[numops]))
{
! /* parse as an expression */
if (uses_at)
{
/* Any expression that involves the indirect addressing
*************** get_operands (exp)
*** 502,524 ****
input_line_pointer += 5;
if (exp[numops].X_op == O_register)
{
! /* If it looked like a register name but was followed by
"@word" then it was really a symbol, so change it to
! one. */
exp[numops].X_op = O_symbol;
! exp[numops].X_add_symbol =
! symbol_find_or_make ((char *) exp[numops].X_op_symbol);
}
! /* Check for identifier@word+constant. */
if (*input_line_pointer == '-' || *input_line_pointer == '+')
{
expressionS new_exp;
expression (&new_exp);
exp[numops].X_add_number = new_exp.X_add_number;
}
! /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT. */
{
expressionS new_exp;
memset (&new_exp, 0, sizeof new_exp);
--- 505,527 ----
input_line_pointer += 5;
if (exp[numops].X_op == O_register)
{
! /* if it looked like a register name but was followed by
"@word" then it was really a symbol, so change it to
! one */
exp[numops].X_op = O_symbol;
! exp[numops].X_add_symbol = symbol_find_or_make ((char *)exp[numops].X_op_symbol);
}
! /* check for identifier@word+constant */
if (*input_line_pointer == '-' || *input_line_pointer == '+')
{
+ char *orig_line = input_line_pointer;
expressionS new_exp;
expression (&new_exp);
exp[numops].X_add_number = new_exp.X_add_number;
}
! /* convert expr into a right shift by AT_WORD_RIGHT_SHIFT */
{
expressionS new_exp;
memset (&new_exp, 0, sizeof new_exp);
*************** get_operands (exp)
*** 543,553 ****
switch (post)
{
! case -1: /* Postdecrement mode. */
exp[numops].X_op = O_absent;
exp[numops++].X_add_number = OPERAND_MINUS;
break;
! case 1: /* Postincrement mode. */
exp[numops].X_op = O_absent;
exp[numops++].X_add_number = OPERAND_PLUS;
break;
--- 546,556 ----
switch (post)
{
! case -1: /* postdecrement mode */
exp[numops].X_op = O_absent;
exp[numops++].X_add_number = OPERAND_MINUS;
break;
! case 1: /* postincrement mode */
exp[numops].X_op = O_absent;
exp[numops++].X_add_number = OPERAND_PLUS;
break;
*************** d10v_insert_operand (insn, op_type, valu
*** 573,582 ****
bits = d10v_operands[op_type].bits;
! /* Truncate to the proper number of bits. */
if (check_range (value, bits, d10v_operands[op_type].flags))
! as_bad_where (fix->fx_file, fix->fx_line,
! _("operand out of range: %d"), value);
value &= 0x7FFFFFFF >> (31 - bits);
insn |= (value << shift);
--- 576,584 ----
bits = d10v_operands[op_type].bits;
! /* truncate to the proper number of bits */
if (check_range (value, bits, d10v_operands[op_type].flags))
! as_bad_where (fix->fx_file, fix->fx_line, _("operand out of range: %d"), value);
value &= 0x7FFFFFFF >> (31 - bits);
insn |= (value << shift);
*************** d10v_insert_operand (insn, op_type, valu
*** 584,592 ****
return insn;
}
- /* Take a pointer to the opcode entry in the opcode table and the
- array of operand expressions. Return the instruction. */
static unsigned long
build_insn (opcode, opers, insn)
struct d10v_opcode *opcode;
--- 586,595 ----
return insn;
}
+ /* build_insn takes a pointer to the opcode entry in the opcode table
+ and the array of operand expressions and returns the instruction */
+
static unsigned long
build_insn (opcode, opers, insn)
struct d10v_opcode *opcode;
*************** build_insn (opcode, opers, insn)
*** 596,602 ****
int i, bits, shift, flags, format;
unsigned long number;
! /* The insn argument is only used for the DIVS kludge. */
if (insn)
format = LONG_R;
else
--- 599,605 ----
int i, bits, shift, flags, format;
unsigned long number;
! /* the insn argument is only used for the DIVS kludge */
if (insn)
format = LONG_R;
else
*************** build_insn (opcode, opers, insn)
*** 621,637 ****
if (opers[i].X_op != O_register && opers[i].X_op != O_constant)
{
! /* Now create a fixup. */
if (fixups->fc >= MAX_INSN_FIXUPS)
as_fatal (_("too many fixups"));
if (AT_WORD_P (&opers[i]))
{
! /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD). */
fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18;
opers[i].X_op = O_symbol;
! opers[i].X_op_symbol = NULL; /* Should free it. */
/* number is left shifted by AT_WORD_RIGHT_SHIFT so
that, it is aligned with the symbol's value. Later,
BFD_RELOC_D10V_18 will right shift (symbol_value +
--- 624,640 ----
if (opers[i].X_op != O_register && opers[i].X_op != O_constant)
{
! /* now create a fixup */
if (fixups->fc >= MAX_INSN_FIXUPS)
as_fatal (_("too many fixups"));
if (AT_WORD_P (&opers[i]))
{
! /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD) */
fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18;
opers[i].X_op = O_symbol;
! opers[i].X_op_symbol = NULL; /* Should free it */
/* number is left shifted by AT_WORD_RIGHT_SHIFT so
that, it is aligned with the symbol's value. Later,
BFD_RELOC_D10V_18 will right shift (symbol_value +
*************** build_insn (opcode, opers, insn)
*** 651,662 ****
fixups->fix[fixups->fc].exp = opers[i];
fixups->fix[fixups->fc].operand = opcode->operands[i];
! fixups->fix[fixups->fc].pcrel =
! (flags & OPERAND_ADDR) ? true : false;
(fixups->fc)++;
}
! /* Truncate to the proper number of bits. */
if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
as_bad (_("operand out of range: %d"), number);
number &= 0x7FFFFFFF >> (31 - bits);
--- 654,664 ----
fixups->fix[fixups->fc].exp = opers[i];
fixups->fix[fixups->fc].operand = opcode->operands[i];
! fixups->fix[fixups->fc].pcrel = (flags & OPERAND_ADDR) ? true : false;
(fixups->fc)++;
}
! /* truncate to the proper number of bits */
if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
as_bad (_("operand out of range: %d"),number);
number &= 0x7FFFFFFF >> (31 - bits);
*************** build_insn (opcode, opers, insn)
*** 664,681 ****
}
/* kludge: for DIVS, we need to put the operands in twice */
! /* on the second pass, format is changed to LONG_R to force
! the second set of operands to not be shifted over 15. */
if ((opcode->opcode == OPCODE_DIVS) && (format == LONG_L))
insn = build_insn (opcode, opers, insn);
return insn;
}
-
- /* Write out a long form instruction. */
static void
! write_long (insn, fx)
unsigned long insn;
Fixups *fx;
{
--- 666,683 ----
}
/* kludge: for DIVS, we need to put the operands in twice */
! /* on the second pass, format is changed to LONG_R to force */
! /* the second set of operands to not be shifted over 15 */
if ((opcode->opcode == OPCODE_DIVS) && (format==LONG_L))
insn = build_insn (opcode, opers, insn);
return insn;
}
+ /* write out a long form instruction */
static void
! write_long (opcode, insn, fx)
! struct d10v_opcode *opcode;
unsigned long insn;
Fixups *fx;
{
*************** write_long (insn, fx)
*** 707,714 ****
fx->fc = 0;
}
- /* Write out a short form instruction by itself. */
static void
write_1_short (opcode, insn, fx)
struct d10v_opcode *opcode;
--- 709,716 ----
fx->fc = 0;
}
+ /* write out a short form instruction by itself */
static void
write_1_short (opcode, insn, fx)
struct d10v_opcode *opcode;
*************** write_1_short (opcode, insn, fx)
*** 721,733 ****
if (opcode->exec_type & PARONLY)
as_fatal (_("Instruction must be executed in parallel with another instruction."));
! /* The other container needs to be NOP. */
! /* According to 4.3.1: for FM=00, sub-instructions performed only
by IU cannot be encoded in L-container. */
if (opcode->unit == IU)
! insn |= FM00 | (NOP << 15); /* Right container. */
else
! insn = FM00 | (insn << 15) | NOP; /* Left container. */
number_to_chars_bigendian (f, insn, 4);
for (i = 0; i < fx->fc; i++)
--- 723,735 ----
if (opcode->exec_type & PARONLY)
as_fatal (_("Instruction must be executed in parallel with another instruction."));
! /* the other container needs to be NOP */
! /* according to 4.3.1: for FM=00, sub-instructions performed only
by IU cannot be encoded in L-container. */
if (opcode->unit == IU)
! insn |= FM00 | (NOP << 15); /* right container */
else
! insn = FM00 | (insn << 15) | NOP; /* left container */
number_to_chars_bigendian (f, insn, 4);
for (i=0; i < fx->fc; i++)
*************** write_1_short (opcode, insn, fx)
*** 741,749 ****
if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
fx->fix[i].operand |= 4096;
! /* If it's an R reloc, we may have to switch it to L. */
! if ((fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R)
! && (opcode->unit != IU))
fx->fix[i].operand |= 1024;
fix_new_exp (frag_now,
--- 743,750 ----
if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
fx->fix[i].operand |= 4096;
! /* if it's an R reloc, we may have to switch it to L */
! if ( (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) && (opcode->unit != IU) )
fx->fix[i].operand |= 1024;
fix_new_exp (frag_now,
*************** write_2_short (opcode1, insn1, opcode2,
*** 773,780 ****
char *f;
int i, j, where;
! if ((exec_type != PACK_PARALLEL)
! && ((opcode1->exec_type & PARONLY) || (opcode2->exec_type & PARONLY)))
as_fatal (_("Instruction must be executed in parallel"));
if ((opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
--- 774,781 ----
char *f;
int i,j, where;
! if ( (exec_type != PACK_PARALLEL) && ((opcode1->exec_type & PARONLY)
! || (opcode2->exec_type & PARONLY)))
as_fatal (_("Instruction must be executed in parallel"));
if ( (opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
*************** write_2_short (opcode1, insn1, opcode2,
*** 780,799 ****
if ((opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
as_fatal (_("Long instructions may not be combined."));
switch (exec_type)
{
! case PACK_UNSPEC: /* Order not specified. */
if (opcode1->exec_type & ALONE)
{
! /* Case of a short branch on a separate GAS line.
! Pack with NOP. */
write_1_short (opcode1, insn1, fx->next);
return 1;
}
! if (Optimizing
! && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
{
! /* Parallel. */
if (opcode1->unit == IU)
insn = FM00 | (insn2 << 15) | insn1;
else if (opcode2->unit == MU)
--- 781,799 ----
if ( (opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
as_fatal (_("Long instructions may not be combined."));
+
switch (exec_type)
{
! case PACK_UNSPEC: /* order not specified */
if (opcode1->exec_type & ALONE)
{
! /* Case of a short branch on a separate GAS line. Pack with NOP. */
write_1_short (opcode1, insn1, fx->next);
return 1;
}
! if (Optimizing && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
{
! /* parallel */
if (opcode1->unit == IU)
insn = FM00 | (insn2 << 15) | insn1;
else if (opcode2->unit == MU)
*************** write_2_short (opcode1, insn1, opcode2,
*** 802,808 ****
insn = FM00 | (insn1 << 15) | insn2;
}
else if (opcode1->unit == IU)
! /* Reverse sequential with IU opcode1 on right and done first. */
insn = FM10 | (insn2 << 15) | insn1;
else
/* Sequential with non-IU opcode1 on left and done first. */
--- 802,808 ----
insn = FM00 | (insn1 << 15) | insn2;
}
else if (opcode1->unit == IU)
! /* reverse sequential with IU opcode1 on right and done first */
insn = FM10 | (insn2 << 15) | insn1;
else
/* Sequential with non-IU opcode1 on left and done first. */
*************** write_2_short (opcode1, insn1, opcode2,
*** 831,838 ****
--- 832,841 ----
}
else
insn = FM00 | (insn1 << 15) | insn2;
+ check_resource_conflict (opcode1, insn1, opcode2, insn2);
break;
+
case PACK_LEFT_RIGHT:
if (opcode1->unit != IU)
insn = FM01 | (insn1 << 15) | insn2;
*************** write_2_short (opcode1, insn1, opcode2,
*** 914,922 ****
return (0);
}
- /* Check 2 instructions and determine if they can be safely
- executed in parallel. Return 1 if they can be. */
static int
parallel_ok (op1, insn1, op2, insn2, exec_type)
struct d10v_opcode *op1, *op2;
--- 920,928 ----
return (0);
}
+ /* Check 2 instructions and determine if they can be safely */
+ /* executed in parallel. Returns 1 if they can be. */
static int
parallel_ok (op1, insn1, op2, insn2, exec_type)
struct d10v_opcode *op1, *op2;
*************** parallel_ok (op1, insn1, op2, insn2, exe
*** 937,943 ****
/* If this is auto parallization, and either instruction is a branch,
don't parallel. */
if (exec_type == PACK_UNSPEC
! && (op1->exec_type & ALONE || op2->exec_type & ALONE))
return 0;
/* The idea here is to create two sets of bitmasks (mod and used)
--- 943,949 ----
/* If this is auto parallization, and either instruction is a branch,
don't parallel. */
if (exec_type == PACK_UNSPEC
! && ( op1->exec_type & (ALONE|BRANCH) || op2->exec_type & (ALONE|BRANCH) ))
return 0;
/* The idea here is to create two sets of bitmasks (mod and used)
*************** parallel_ok (op1, insn1, op2, insn2, exe
*** 955,961 ****
and the second reads the PSW (which includes C, F0, and F1), then
they cannot operate safely in parallel. */
! /* The bitmasks (mod and used) look like this (bit 31 = MSB). */
/* r0-r15 0-15 */
/* a0-a1 16-17 */
/* cr (not psw) 18 */
--- 961,967 ----
and the second reads the PSW (which includes C, F0, and F1), then
they cannot operate safely in parallel. */
! /* the bitmasks (mod and used) look like this (bit 31 = MSB) */
/* r0-r15 0-15 */
/* a0-a1 16-17 */
/* cr (not psw) 18 */
*************** parallel_ok (op1, insn1, op2, insn2, exe
*** 988,994 ****
regno = (ins >> shift) & mask;
if (flags & (OPERAND_ACC0 | OPERAND_ACC1))
regno += 16;
! else if (flags & OPERAND_CONTROL) /* mvtc or mvfc. */
{
if (regno == 0)
regno = 19;
--- 994,1000 ----
regno = (ins >> shift) & mask;
if (flags & (OPERAND_ACC0|OPERAND_ACC1))
regno += 16;
! else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */
{
if (regno == 0)
regno = 19;
*************** parallel_ok (op1, insn1, op2, insn2, exe
*** 1019,1025 ****
}
else if (flags & OPERAND_ATMINUS)
{
! /* SP implicitly used/modified. */
mod[j] |= 1 << 15;
used[j] |= 1 << 15;
}
--- 1025,1031 ----
}
else if (flags & OPERAND_ATMINUS)
{
! /* SP implicitly used/modified */
mod[j] |= 1 << 15;
used[j] |= 1 << 15;
}
*************** parallel_ok (op1, insn1, op2, insn2, exe
*** 1040,1051 ****
return 0;
}
- /* This is the main entry point for the machine-dependent assembler.
- STR points to a machine-dependent instruction. This function is
- supposed to emit the frags/bytes it assembles to. For the D10V, it
- mostly handles the special VLIW parsing and packing and leaves the
- difficult stuff to do_assemble(). */
static unsigned long prev_insn;
static struct d10v_opcode *prev_opcode = 0;
static subsegT prev_subseg;
--- 1046,1207 ----
return 0;
}
+ /* Determine if there are any resource conflicts among two manually
+ parallelized instructions. Some of this was lifted from parallel_ok. */
+ static void
+ check_resource_conflict (op1, insn1, op2, insn2)
+ struct d10v_opcode *op1, *op2;
+ unsigned long insn1, insn2;
+ {
+ int i, j, flags, mask, shift, regno;
+ unsigned long ins, mod[2], used[2];
+ struct d10v_opcode *op;
+
+ if ((op1->exec_type & SEQ)
+ || ! ((op1->exec_type & PAR) || (op1->exec_type & PARONLY)))
+ {
+ as_warn (_("packing conflict: %s must dispatch sequentially"),
+ op1->name);
+ return;
+ }
+
+ if ((op2->exec_type & SEQ)
+ || ! ((op2->exec_type & PAR) || (op2->exec_type & PARONLY)))
+ {
+ as_warn (_("packing conflict: %s must dispatch sequentially"),
+ op2->name);
+ return;
+ }
+
+
+ /* The idea here is to create two sets of bitmasks (mod and used)
+ which indicate which registers are modified or used by each
+ instruction. The operation can only be done in parallel if
+ instruction 1 and instruction 2 modify different registers, and
+ the first instruction does not modify registers that the second
+ is using (The second instruction can modify registers that the
+ first is using as they are only written back after the first
+ instruction has completed). Accesses to control registers
+ and memory are treated as accesses to a single register. So if
+ both instructions write memory or if the first instruction writes
+ memory and the second reads, then they cannot be done in
+ parallel. We treat reads to the PSW (which includes C, F0, and F1)
+ in isolation. So simultaneously writing C and F0 in two different
+ sub-instructions is permitted. */
+
+ /* the bitmasks (mod and used) look like this (bit 31 = MSB) */
+ /* r0-r15 0-15 */
+ /* a0-a1 16-17 */
+ /* cr (not psw) 18 */
+ /* psw(other) 19 */
+ /* mem 20 */
+ /* psw(C flag) 21 */
+ /* psw(F0 flag) 22 */
+
+
+ for (j = 0; j < 2; j++)
+ {
+ if (j == 0)
+ {
+ op = op1;
+ ins = insn1;
+ }
+ else
+ {
+ op = op2;
+ ins = insn2;
+ }
+ mod[j] = used[j] = 0;
+ if (op->exec_type & BRANCH_LINK)
+ mod[j] |= 1 << 13;
+
+ for (i = 0; op->operands[i]; i++)
+ {
+ flags = d10v_operands[op->operands[i]].flags;
+ shift = d10v_operands[op->operands[i]].shift;
+ mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
+ if (flags & OPERAND_REG)
+ {
+ regno = (ins >> shift) & mask;
+ if (flags & (OPERAND_ACC0 | OPERAND_ACC1))
+ regno += 16;
+ else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */
+ {
+ if (regno == 0)
+ regno = 19;
+ else
+ regno = 18;
+ }
+ else if (flags & OPERAND_FFLAG)
+ regno = 22;
+ else if (flags & OPERAND_CFLAG)
+ regno = 21;
+
+ if ( flags & OPERAND_DEST )
+ {
+ mod[j] |= 1 << regno;
+ if (flags & OPERAND_EVEN)
+ mod[j] |= 1 << (regno + 1);
+ }
+ else
+ {
+ used[j] |= 1 << regno ;
+ if (flags & OPERAND_EVEN)
+ used[j] |= 1 << (regno + 1);
+
+ /* Auto inc/dec also modifies the register. */
+ if (op->operands[i+1] != 0
+ && (d10v_operands[op->operands[i+1]].flags
+ & (OPERAND_PLUS | OPERAND_MINUS)) != 0)
+ mod[j] |= 1 << regno;
+ }
+ }
+ else if (flags & OPERAND_ATMINUS)
+ {
+ /* SP implicitly used/modified */
+ mod[j] |= 1 << 15;
+ used[j] |= 1 << 15;
+ }
+ }
+ if (op->exec_type & RMEM)
+ used[j] |= 1 << 20;
+ else if (op->exec_type & WMEM)
+ mod[j] |= 1 << 20;
+ else if (op->exec_type & RF0)
+ used[j] |= 1 << 22;
+ else if (op->exec_type & WF0)
+ mod[j] |= 1 << 22;
+ else if (op->exec_type & WCAR)
+ mod[j] |= 1 << 21;
+ }
+ if ((mod[0] & mod[1]) == 0)
+ return;
+ else
+ {
+ unsigned long x;
+ x = mod[0] & mod[1];
+
+ for (j = 0; j <= 15; j++)
+ if (x & (1 << j))
+ as_warn (_("resource conflict (R%d)"), j);
+ for (j = 16; j <= 17; j++)
+ if (x & (1 << j))
+ as_warn (_("resource conflict (A%d)"), j - 16);
+ if (x & (1 << 19))
+ as_warn (_("resource conflict (PSW)"));
+ if (x & (1 << 21))
+ as_warn (_("resource conflict (C flag)"));
+ if (x & (1 << 22))
+ as_warn (_("resource conflict (F flag)"));
+ }
+ }
+ /* This is the main entry point for the machine-dependent assembler. str points to a
+ machine-dependent instruction. This function is supposed to emit the frags/bytes
+ it assembles to. For the D10V, it mostly handles the special VLIW parsing and packing
+ and leaves the difficult stuff to do_assemble().
+ */
+
static unsigned long prev_insn;
static struct d10v_opcode *prev_opcode = 0;
static subsegT prev_subseg;
*************** void
*** 1055,1063 ****
md_assemble (str)
char *str;
{
! /* etype is saved extype. For multi-line instructions. */
! packing_type extype = PACK_UNSPEC; /* Parallel, etc. */
struct d10v_opcode *opcode;
unsigned long insn;
--- 1211,1219 ----
md_assemble (str)
char *str;
{
! /* etype is saved extype. for multiline instructions */
! packing_type extype = PACK_UNSPEC; /* parallel, etc */
struct d10v_opcode * opcode;
unsigned long insn;
*************** md_assemble (str)
*** 1065,1071 ****
if (etype == PACK_UNSPEC)
{
! /* Look for the special multiple instruction separators. */
str2 = strstr (str, "||");
if (str2)
extype = PACK_PARALLEL;
--- 1221,1227 ----
if (etype == PACK_UNSPEC)
{
! /* look for the special multiple instruction separators */
str2 = strstr (str, "||");
if (str2)
extype = PACK_PARALLEL;
*************** md_assemble (str)
*** 1081,1100 ****
extype = PACK_RIGHT_LEFT;
}
}
! /* STR2 points to the separator, if there is one. */
if (str2)
{
*str2 = 0;
! /* If two instructions are present and we already have one saved,
! then first write out the saved one. */
d10v_cleanup ();
! /* Assemble first instruction and save it. */
prev_insn = do_assemble (str, &prev_opcode);
prev_seg = now_seg;
prev_subseg = now_subseg;
! if (prev_insn == (unsigned long) -1)
as_fatal (_("can't find opcode "));
fixups = fixups->next;
str = str2 + 2;
--- 1237,1256 ----
extype = PACK_RIGHT_LEFT;
}
}
! /* str2 points to the separator, if one */
if (str2)
{
*str2 = 0;
! /* if two instructions are present and we already have one saved
! then first write out the save one */
d10v_cleanup ();
! /* assemble first instruction and save it */
prev_insn = do_assemble (str, &prev_opcode);
prev_seg = now_seg;
prev_subseg = now_subseg;
! if (prev_insn == -1)
as_fatal (_("can't find opcode "));
fixups = fixups->next;
str = str2 + 2;
*************** md_assemble (str)
*** 1102,1108 ****
}
insn = do_assemble (str, &opcode);
! if (insn == (unsigned long) -1)
{
if (extype != PACK_UNSPEC)
{
--- 1258,1264 ----
}
insn = do_assemble (str, &opcode);
! if (insn == -1)
{
if (extype != PACK_UNSPEC)
{
*************** md_assemble (str)
*** 1118,1151 ****
etype = PACK_UNSPEC;
}
! /* If this is a long instruction, write it and any previous short
! instruction. */
if (opcode->format & LONG_OPCODE)
{
if (extype != PACK_UNSPEC)
as_fatal (_("Unable to mix instructions as specified"));
d10v_cleanup ();
! write_long (insn, fixups);
prev_opcode = NULL;
return;
}
! if (prev_opcode
! && prev_seg
! && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
d10v_cleanup ();
! if (prev_opcode
! && (write_2_short (prev_opcode, prev_insn, opcode, insn, extype, fixups) == 0))
{
! /* No instructions saved. */
prev_opcode = NULL;
}
else
{
if (extype != PACK_UNSPEC)
as_fatal (_("Unable to mix instructions as specified"));
! /* Save last instruction so it may be packed on next pass. */
prev_opcode = opcode;
prev_insn = insn;
prev_seg = now_seg;
--- 1274,1303 ----
etype = PACK_UNSPEC;
}
! /* if this is a long instruction, write it and any previous short instruction */
if (opcode->format & LONG_OPCODE)
{
if (extype != PACK_UNSPEC)
as_fatal (_("Unable to mix instructions as specified"));
d10v_cleanup ();
! write_long (opcode, insn, fixups);
prev_opcode = NULL;
return;
}
! if (prev_opcode && prev_seg && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
d10v_cleanup ();
! if (prev_opcode && (write_2_short (prev_opcode, prev_insn, opcode, insn, extype, fixups) == 0))
{
! /* no instructions saved */
prev_opcode = NULL;
}
else
{
if (extype != PACK_UNSPEC)
as_fatal (_("Unable to mix instructions as specified"));
! /* save off last instruction so it may be packed on next pass */
prev_opcode = opcode;
prev_insn = insn;
prev_seg = now_seg;
*************** md_assemble (str)
*** 1154,1161 ****
}
}
! /* Assemble a single instruction.
! Return an opcode, or -1 (an invalid opcode) on error. */
static unsigned long
do_assemble (str, opcode)
--- 1306,1314 ----
}
}
!
! /* do_assemble assembles a single instruction and returns an opcode */
! /* it returns -1 (an invalid opcode) on error */
static unsigned long
do_assemble (str, opcode)
*************** do_assemble (str, opcode)
*** 1180,1186 ****
&& !is_end_of_line[*op_end] && *op_end != ' ';
op_end++)
{
! name[nlen] = TOLOWER (op_start[nlen]);
nlen++;
}
name[nlen] = 0;
--- 1333,1339 ----
&& !is_end_of_line[*op_end] && *op_end != ' ';
op_end++)
{
! name[nlen] = tolower (op_start[nlen]);
nlen++;
}
name[nlen] = 0;
*************** do_assemble (str, opcode)
*** 1204,1211 ****
return (insn);
}
! /* Find the symbol which has the same name as the register in EXP. */
!
static symbolS *
find_symbol_matching_register (exp)
expressionS *exp;
--- 1357,1363 ----
return (insn);
}
! /* Find the symbol which has the same name as the register in the given expression. */
static symbolS *
find_symbol_matching_register (exp)
expressionS * exp;
*************** find_symbol_matching_register (exp)
*** 1227,1249 ****
return symbol_find (d10v_predefined_registers[i].name);
}
! /* Get a pointer to an entry in the opcode table.
! The function must look at all opcodes with the same name and use
! the operands to choose the correct opcode. */
static struct d10v_opcode *
find_opcode (opcode, myops)
struct d10v_opcode *opcode;
expressionS myops[];
{
! int i, match;
struct d10v_opcode *next_opcode;
! /* Get all the operands and save them as expressions. */
get_operands (myops);
! /* Now see if the operand is a fake. If so, find the correct size
! instruction, if possible. */
if (opcode->format == OPCODE_FAKE)
{
int opnum = opcode->operands[0];
--- 1379,1402 ----
return symbol_find (d10v_predefined_registers [i].name);
}
!
! /* find_opcode() gets a pointer to an entry in the opcode table. */
! /* It must look at all opcodes with the same name and use the operands */
! /* to choose the correct opcode. */
static struct d10v_opcode *
find_opcode (opcode, myops)
struct d10v_opcode *opcode;
expressionS myops[];
{
! int i, match, done;
struct d10v_opcode *next_opcode;
! /* get all the operands and save them as expressions */
get_operands (myops);
! /* now see if the operand is a fake. If so, find the correct size */
! /* instruction, if possible */
if (opcode->format == OPCODE_FAKE)
{
int opnum = opcode->operands[0];
*************** find_opcode (opcode, myops)
*** 1252,1259 ****
if (myops[opnum].X_op == O_register)
{
myops[opnum].X_op = O_symbol;
! myops[opnum].X_add_symbol =
! symbol_find_or_make ((char *) myops[opnum].X_op_symbol);
myops[opnum].X_add_number = 0;
myops[opnum].X_op_symbol = NULL;
}
--- 1405,1411 ----
if (myops[opnum].X_op == O_register)
{
myops[opnum].X_op = O_symbol;
! myops[opnum].X_add_symbol = symbol_find_or_make ((char *)myops[opnum].X_op_symbol);
myops[opnum].X_add_number = 0;
myops[opnum].X_op_symbol = NULL;
}
*************** find_opcode (opcode, myops)
*** 1279,1288 ****
}
}
! if (myops[opnum].X_op == O_constant
! || (myops[opnum].X_op == O_symbol
! && S_IS_DEFINED (myops[opnum].X_add_symbol)
! && (S_GET_SEGMENT (myops[opnum].X_add_symbol) == now_seg)))
{
for (i = 0; opcode->operands[i + 1]; i++)
{
--- 1431,1439 ----
}
}
! if (myops[opnum].X_op == O_constant || (myops[opnum].X_op == O_symbol &&
! S_IS_DEFINED(myops[opnum].X_add_symbol) &&
! (S_GET_SEGMENT(myops[opnum].X_add_symbol) == now_seg)))
{
for (i=0; opcode->operands[i+1]; i++)
{
*************** find_opcode (opcode, myops)
*** 1294,1300 ****
if (myops[opnum].X_op == O_constant)
{
if (!check_range (myops[opnum].X_add_number, bits, flags))
! return next_opcode;
}
else
{
--- 1444,1450 ----
if (myops[opnum].X_op == O_constant)
{
if (!check_range (myops[opnum].X_add_number, bits, flags))
! break;
}
else
{
*************** find_opcode (opcode, myops)
*** 1312,1320 ****
sym_frag = symbol_get_frag (myops[opnum].X_add_symbol);
found_symbol = false;
! current_position =
! obstack_next_free (&frchain_now->frch_obstack)
! - frag_now->fr_literal;
symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol);
for (f = frchain_now->frch_root; f; f = f->fr_next)
--- 1462,1468 ----
sym_frag = symbol_get_frag (myops[opnum].X_add_symbol);
found_symbol = false;
! current_position = obstack_next_free (&frchain_now->frch_obstack) - frag_now->fr_literal;
symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol);
for (f = frchain_now->frch_root; f; f = f->fr_next)
*************** find_opcode (opcode, myops)
*** 1339,1365 ****
{
bits += 2;
if (!check_range (value, bits, flags))
! return next_opcode;
}
}
else if (!check_range (value, bits, flags))
! return next_opcode;
}
next_opcode++;
}
as_fatal (_("value out of range"));
}
else
{
! /* Not a constant, so use a long instruction. */
! return opcode + 2;
}
}
! else
! {
match = 0;
! /* Now search the opcode table table for one with operands
! that matches what we've got. */
while (!match)
{
match = 1;
--- 1487,1518 ----
{
bits += 2;
if (!check_range (value, bits, flags))
! break;
}
}
else if (!check_range (value, bits, flags))
! break;
}
next_opcode++;
}
+
+ if (opcode->operands [i + 1] == 0)
as_fatal (_("value out of range"));
+ else
+ opcode = next_opcode;
}
else
{
! /* not a constant, so use a long instruction */
! opcode += 2;
}
}
!
match = 0;
!
! /* now search the opcode table table for one with operands */
! /* that matches what we've got */
!
while (!match)
{
match = 1;
*************** find_opcode (opcode, myops)
*** 1399,1422 ****
break;
}
! /* Unfortunatly, for the indirect operand in
! instructions such as ``ldb r1, @(c,r14)'' this
! function can be passed X_op == O_register (because
! 'c' is a valid register name). However we cannot
! just ignore the case when X_op == O_register but
! flags & OPERAND_REG is null, so we check to see if a
! symbol of the same name as the register exists. If
! the symbol does exist, then the parser was unable to
! distinguish the two cases and we fix things here.
! (Ref: PR14826) */
if (!(flags & OPERAND_REG) && (X_op == O_register))
{
! symbolS *sym = find_symbol_matching_register (&myops[i]);
if (sym != NULL)
{
! myops[i].X_op = X_op = O_symbol;
myops[i].X_add_symbol = sym;
}
else
--- 1553,1575 ----
break;
}
! /* Unfortunatly, for the indirect operand in instructions such as
! ``ldb r1, @(c,r14)'' this function can be passed X_op == O_register
! (because 'c' is a valid register name). However we cannot just
! ignore the case when X_op == O_register but flags & OPERAND_REG is
! null, so we check to see if a symbol of the same name as the register
! exists. If the symbol does exist, then the parser was unable to
! distinguish the two cases and we fix things here. (Ref: PR14826) */
if (!(flags & OPERAND_REG) && (X_op == O_register))
{
! symbolS * sym;
+ sym = find_symbol_matching_register (& myops[i]);
+
if (sym != NULL)
{
! myops [i].X_op = (X_op == O_symbol);
myops [i].X_add_symbol = sym;
}
else
*************** find_opcode (opcode, myops)
*** 1442,1448 ****
opcode = next_opcode;
}
- }
if (!match)
{
--- 1595,1600 ----
*************** find_opcode (opcode, myops)
*** 1450,1458 ****
return (0);
}
! /* Check that all registers that are required to be even are.
! Also, if any operands were marked as registers, but were really symbols,
! fix that here. */
for (i = 0; opcode->operands[i]; i++)
{
if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) &&
--- 1602,1612 ----
return (0);
}
! /* Check that all registers that are required to be even are. */
! /* Also, if any operands were marked as registers, but were really symbols */
! /* fix that here. */
! /* Also emit a warning if any of the reserved control registers were
! used. The reserved CRs are CR4-6, CR12, CR13 and CR15. */
for (i=0; opcode->operands[i]; i++)
{
if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) &&
*************** find_opcode (opcode, myops)
*** 1466,1487 ****
if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG))
{
myops[i].X_op = O_symbol;
! myops[i].X_add_symbol =
! symbol_find_or_make ((char *) myops[i].X_op_symbol);
myops[i].X_add_number = 0;
myops[i].X_op_symbol = NULL;
}
}
}
return opcode;
}
! /* If while processing a fixup, a reloc really needs to be created.
! Then it is done here. */
arelent *
tc_gen_reloc (seg, fixp)
! asection *seg ATTRIBUTE_UNUSED;
fixS *fixp;
{
arelent *reloc;
--- 1620,1649 ----
if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG))
{
myops[i].X_op = O_symbol;
! myops[i].X_add_symbol = symbol_find_or_make ((char *)myops[i].X_op_symbol);
myops[i].X_add_number = 0;
myops[i].X_op_symbol = NULL;
}
}
+ if ((d10v_operands[opcode->operands[i]].flags & OPERAND_CONTROL)
+ && (myops[i].X_add_number == OPERAND_CONTROL + 4
+ || myops[i].X_add_number == OPERAND_CONTROL + 5
+ || myops[i].X_add_number == OPERAND_CONTROL + 6
+ || myops[i].X_add_number == OPERAND_CONTROL + 12
+ || myops[i].X_add_number == OPERAND_CONTROL + 13
+ || myops[i].X_add_number == OPERAND_CONTROL + 15))
+ as_warn (_("cr%d is a reserved control register"),
+ myops[i].X_add_number - OPERAND_CONTROL);
}
return opcode;
}
! /* if while processing a fixup, a reloc really needs to be created */
! /* then it is done here */
arelent *
tc_gen_reloc (seg, fixp)
! asection *seg;
fixS *fixp;
{
arelent *reloc;
*************** tc_gen_reloc (seg, fixp)
*** 1493,1500 ****
if (reloc->howto == (reloc_howto_type *) NULL)
{
as_bad_where (fixp->fx_file, fixp->fx_line,
! _("reloc %d not supported by object file format"),
! (int) fixp->fx_r_type);
return NULL;
}
--- 1655,1661 ----
if (reloc->howto == (reloc_howto_type *) NULL)
{
as_bad_where (fixp->fx_file, fixp->fx_line,
! _("reloc %d not supported by object file format"), (int)fixp->fx_r_type);
return NULL;
}
*************** tc_gen_reloc (seg, fixp)
*** 1509,1516 ****
int
md_estimate_size_before_relax (fragp, seg)
! fragS *fragp ATTRIBUTE_UNUSED;
! asection *seg ATTRIBUTE_UNUSED;
{
abort ();
return 0;
--- 1670,1677 ----
int
md_estimate_size_before_relax (fragp, seg)
! fragS *fragp;
! asection *seg;
{
abort ();
return 0;
*************** md_pcrel_from_section (fixp, sec)
*** 1521,1529 ****
fixS *fixp;
segT sec;
{
! if (fixp->fx_addsy != (symbolS *) NULL
! && (!S_IS_DEFINED (fixp->fx_addsy)
! || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
return 0;
return fixp->fx_frag->fr_address + fixp->fx_where;
}
--- 1682,1689 ----
fixS *fixp;
segT sec;
{
! if (fixp->fx_addsy != (symbolS *)NULL && (!S_IS_DEFINED (fixp->fx_addsy) ||
! (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
return 0;
return fixp->fx_frag->fr_address + fixp->fx_where;
}
*************** md_apply_fix3 (fixP, valP, seg)
*** 1593,1600 ****
case BFD_RELOC_D10V_10_PCREL_L:
case BFD_RELOC_D10V_10_PCREL_R:
case BFD_RELOC_D10V_18_PCREL:
case BFD_RELOC_D10V_18:
! /* Instruction addresses are always right-shifted by 2. */
value >>= AT_WORD_RIGHT_SHIFT;
if (fixP->fx_size == 2)
bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
--- 1753,1774 ----
case BFD_RELOC_D10V_10_PCREL_L:
case BFD_RELOC_D10V_10_PCREL_R:
case BFD_RELOC_D10V_18_PCREL:
+ /* If the fix is relative to a global symbol, not a section
+ symbol, then ignore the offset.
+ XXX - Do we have to worry about branches to a symbol + offset ? */
+ if (fixP->fx_addsy != NULL
+ && S_IS_EXTERN (fixP->fx_addsy) )
+ {
+ segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
+ segment_info_type *segf = seg_info(fseg);
+
+ if ( segf && segf->sym != fixP->fx_addsy)
+ value = 0;
+ }
+ /* Drop through. */
case BFD_RELOC_D10V_18:
!
! /* instruction addresses are always right-shifted by 2 */
value >>= AT_WORD_RIGHT_SHIFT;
if (fixP->fx_size == 2)
bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
*************** md_apply_fix3 (fixP, valP, seg)
*** 1605,1612 ****
rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep");
repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi");
if ((insn & FM11) == FM11
! && ( (repi != NULL && (insn & repi->mask) == (unsigned) repi->opcode)
! || (rep != NULL && (insn & rep->mask) == (unsigned) rep->opcode))
&& value < 4)
as_fatal
(_("line %d: rep or repi must include at least 4 instructions"),
--- 1779,1786 ----
rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep");
repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi");
if ((insn & FM11) == FM11
! && (repi != NULL && (insn & repi->mask) == repi->opcode
! || rep != NULL && (insn & rep->mask) == rep->opcode)
&& value < 4)
as_fatal
(_("line %d: rep or repi must include at least 4 instructions"),
*************** md_apply_fix3 (fixP, valP, seg)
*** 1639,1645 ****
stab directive is output. Because the D10V assembler sometimes
saves short instructions to see if it can package them with the
next instruction, there may be a short instruction that still needs
! to be written.
NOTE: accesses a global, etype.
NOTE: invoked by various macros such as md_cleanup: see. */
--- 1813,1819 ----
stab directive is output. Because the D10V assembler sometimes
saves short instructions to see if it can package them with the
next instruction, there may be a short instruction that still needs
! written.
NOTE: accesses a global, etype.
NOTE: invoked by various macros such as md_cleanup: see. */
*************** d10v_cleanup ()
*** 1656,1663 ****
debugging information, though, we write out the pending
instruction only if the --no-gstabs-packing command line switch
has been specified. */
! if (prev_opcode
! && etype == PACK_UNSPEC
&& (! outputting_stabs_line_debug || ! flag_allow_gstabs_packing))
{
seg = now_seg;
--- 1830,1836 ----
debugging information, though, we write out the pending
instruction only if the --no-gstabs-packing command line switch
has been specified. */
! if (prev_opcode && etype == PACK_UNSPEC
&& (!outputting_stabs_line_debug || !flag_allow_gstabs_packing))
{
seg = now_seg;
*************** d10v_cleanup ()
*** 1674,1688 ****
return 1;
}
! /* Like normal .word, except support @word. */
! /* Clobbers input_line_pointer, checks end-of-line. */
!
static void
! d10v_dot_word (dummy)
! int dummy ATTRIBUTE_UNUSED;
{
expressionS exp;
char *p;
if (is_it_end_of_statement ())
{
--- 1844,1859 ----
return 1;
}
! /* Like normal .word, except support @word */
! /* clobbers input_line_pointer, checks end-of-line. */
static void
! d10v_dot_word (nbytes)
! register int nbytes; /* 1=.byte, 2=.word, 4=.long */
{
expressionS exp;
+ bfd_reloc_code_real_type reloc;
char *p;
+ int offset;
if (is_it_end_of_statement ())
{
*************** d10v_dot_word (dummy)
*** 1711,1726 ****
demand_empty_rest_of_line ();
}
- /* Mitsubishi asked that we support some old syntax that apparently
- had immediate operands starting with '#'. This is in some of their
- sample code but is not documented (although it appears in some
- examples in their assembler manual). For now, we'll solve this
- compatibility problem by simply ignoring any '#' at the beginning
- of an operand. */
! /* Operands that begin with '#' should fall through to here. */
! /* From expr.c. */
void
md_operand (expressionP)
expressionS *expressionP;
--- 1882,1898 ----
demand_empty_rest_of_line ();
}
! /* Mitsubishi asked that we support some old syntax that apparently */
! /* had immediate operands starting with '#'. This is in some of their */
! /* sample code but is not documented (although it appears in some */
! /* examples in their assembler manual). For now, we'll solve this */
! /* compatibility problem by simply ignoring any '#' at the beginning */
! /* of an operand. */
+ /* operands that begin with '#' should fall through to here */
+ /* from expr.c */
+
void
md_operand (expressionP)
expressionS *expressionP;
*************** d10v_fix_adjustable (fixP)
*** 1745,1751 ****
if (S_IS_WEAK (fixP->fx_addsy))
return 0;
! /* We need the symbol name for the VTABLE entries. */
if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
return 0;
--- 1918,1924 ----
if (S_IS_WEAK (fixP->fx_addsy))
return 0;
! /* We need the symbol name for the VTABLE entries */
if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
return 0;
*************** d10v_fix_adjustable (fixP)
*** 1755,1761 ****
int
d10v_force_relocation (fixp)
! fixS *fixp;
{
if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
--- 1928,1934 ----
int
d10v_force_relocation (fixp)
! struct fix *fixp;
{
if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
Index: config/tc-d10v.h
===================================================================
RCS file: /cvs/cvsfiles/devo/gas/config/tc-d10v.h,v
retrieving revision 1.19
diff -d -c -p -b -w -B -r1.19 tc-d10v.h
*** tc-d10v.h 2001/11/25 23:42:22 1.19
--- tc-d10v.h 2001/12/11 15:33:06
***************
*** 34,39 ****
--- 34,41 ----
#define TARGET_FORMAT "elf32-d10v"
+ #define MD_APPLY_FIX3
+
/* Call md_pcrel_from_section, not md_pcrel_from. */
#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section(FIXP, SEC)
long md_pcrel_from_section PARAMS ((fixS *, segT));
*************** int d10v_cleanup PARAMS ((void));
*** 59,66 ****
} while (0)
#define obj_fix_adjustable(fixP) d10v_fix_adjustable(fixP)
- boolean d10v_fix_adjustable PARAMS ((fixS *));
#define TC_FORCE_RELOCATION(fixp) d10v_force_relocation(fixp)
! extern int d10v_force_relocation PARAMS ((fixS *));
#define md_flush_pending_output d10v_cleanup
--- 61,67 ----
} while (0)
#define obj_fix_adjustable(fixP) d10v_fix_adjustable(fixP)
#define TC_FORCE_RELOCATION(fixp) d10v_force_relocation(fixp)
! extern int d10v_force_relocation PARAMS ((struct fix *));
#define md_flush_pending_output d10v_cleanup
Alan Matsuoka
GCC Engineering
Red Hat Canada, Ltd
mailto:alanm@redhat.com Tel: (416) 482-2661 x250 / Fax: (416) 482-6299