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[AratiD@kpit.com: [ PATCH] : SH Assembler generates incorrect opcode for PCMP instructions]
- From: Daniel Jacobowitz <drow at mvista dot com>
- To: binutils at sources dot redhat dot com
- Date: Sun, 22 Sep 2002 13:30:52 -0400
- Subject: [AratiD@kpit.com: [ PATCH] : SH Assembler generates incorrect opcode for PCMP instructions]
This patch has been sitting in my mailbox for eight months; as far as I
can see the problem still exists. Should reg_n be initialized inside
of the loop instead of outside? Or Arati's fix applied?
I'd appreciate it if an SH maintainer would comment.
----- Forwarded message from Arati Dikey <AratiD@kpit.com> -----
Date: Thu, 17 Jan 2002 18:10:09 +0530
From: "Arati Dikey" <AratiD@kpit.com>
Subject: [ PATCH] : SH Assembler generates incorrect opcode for PCMP instructions
To: <binutils@sources.redhat.com>
Hi !
The SH assembler generates incorrect opcodes for the parallel PCMP
instruction.
Basically, its last nibble is a copy of the previous instruction's
second nibble
when working in Big Endian format.
For example,
test.s
movs.w @-R5, A0
PCMP X0,Y0
generates opcodes
f5 70
f8 00 84 05
instead of
f8 00 84 00
The following patch corrects this. I have also verified that it does not
cause any
side effect on other DSP instructions.
Regards,
Arati Dikey
--- tc-sh.c.orig Thu Dec 6 11:34:18 2001
+++ tc-sh.c Thu Jan 17 16:41:28 2002
@@ -1769,7 +1769,10 @@
if (field_b)
as_bad (_("multiple parallel processing specifications"));
field_b = ((opcode->nibbles[2] << 12) + (opcode->nibbles[3] <<
8)
- + (reg_x << 6) + (reg_y << 4) + reg_n);
+ + (reg_x << 6) + (reg_y << 4) );
+
+ if (strcmp (opcode->name, "pcmp") != 0)
+ field_b += reg_n;
break;
case PDC:
if (cond)
----- End forwarded message -----
--
Daniel Jacobowitz
MontaVista Software Debian GNU/Linux Developer