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Re: Is MIPS branch delay insn identification ever used?
- From: cgd at broadcom dot com
- To: jg-lists at jguk dot org
- Cc: binutils <binutils at sources dot redhat dot com>
- Date: 31 Mar 2003 09:11:24 -0800
- Subject: Re: Is MIPS branch delay insn identification ever used?
- References: <3E887074.5090500@jguk.org><mailpost.1049129114.27296@news-sj1-1>
At Mon, 31 Mar 2003 16:45:15 +0000 (UTC), "J. Grant" wrote:
> In mips-dis.c near the end of print_insn_mips(); there are several lines
> related to branching and the instruction type.
Yup. To arrange thigns so that delay slots instructions are actually
printed (even if they start a series of 2+ nops 8-).
> Is the plan to support some disassembler instruction re-ordering around
> branch instructions?
Not that I know of. IMO, that would be very, very undesirable in an
actual disassembler. My view is that you want the disassembler
to... disassemble what's there, not creatively reinterpret it. 8-)
(In something that, say, outputs pseudo code that one could
re-compile, yeah, it seems like a reasonable thing to do... which
sounds like what you're doing.)
Gotta wonder "why do you ask?"
cgd
--
Chris Demetriou Broadcom Corporation
Principal Design Engineer Broadband Processor Business Unit
Any opinions expressed in this message are mine, not necessarily Broadcom's.