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[rfa] Add iq2000 family to src/cpu


Hello,

This adds the Vitesse iq2000 family to binutils' src/cpu directory. Ok?

Andrew
2003-06-03  Andrew Cagney  <cagney@redhat.com>

	Contributed by Red Hat.
	* iq2000.cpu: New file.  Written by Ben Elliston, Jeff Johnston,
	Stan Cox, and Frank Ch. Eigler.
	* iq2000.opc: New file.  Written by Ben Elliston, Frank
	Ch. Eigler, Chris Moller, Jeff Johnston, and Stan Cox.
	* iq2000m.cpu: New file.  Written by Jeff Johnston.
	* iq10.cpu: New file.  Written by Jeff Johnston.

Index: iq10.cpu
===================================================================
RCS file: iq10.cpu
diff -N iq10.cpu
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ iq10.cpu	3 Jun 2003 18:39:07 -0000
@@ -0,0 +1,1111 @@
+; IQ10-only CPU description. -*- Scheme -*-
+;
+; Copyright 2001, 2002 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc; developed under contract from Vitesse.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 2 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+
+; Instructions.
+
+(dni andoui-q10 "iq10 and upper ones immediate" (MACH10 USES-RS USES-RT)
+     "andoui $rt,$rs,$hi16"
+     (+ OP10_ANDOUI rs rt hi16)
+     (set rt (and rs (or (sll hi16 16) #xFFFF)))
+     ())
+
+(dni andoui2-q10 "iq10 and upper ones immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT)
+     "andoui ${rt-rs},$hi16"
+     (+ OP10_ANDOUI rt-rs hi16)
+     (set rt-rs (and rt-rs (or (sll hi16 16) #xFFFF)))
+     ())
+
+(dni orui-q10 "or upper immediate" (MACH10 USES-RS USES-RT)
+     "orui $rt,$rs,$hi16"
+     (+ OP10_ORUI rs rt hi16)
+     (set rt (or rs (sll hi16 16)))
+     ())
+
+(dni orui2-q10 "or upper immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT)
+     "orui ${rt-rs},$hi16"
+     (+ OP10_ORUI rt-rs hi16)
+     (set rt-rs (or rt-rs (sll hi16 16)))
+     ())
+
+(dni mrgbq10 "merge bytes" (MACH10 USES-RD USES-RS USES-RT)
+     "mrgb $rd,$rs,$rt,$maskq10"
+     (+ OP_SPECIAL rs rt rd maskq10 FUNC_MRGB)
+     (sequence ((SI temp))
+	       (if (bitclear? mask 0)
+		   (set temp (and rs #xFF))
+		   (set temp (and rt #xFF)))
+	       (if (bitclear? mask 1)
+		   (set temp (or temp (and rs #xFF00)))
+		   (set temp (or temp (and rt #xFF00))))
+	       (if (bitclear? mask 2)
+		   (set temp (or temp (and rs #xFF0000)))
+		   (set temp (or temp (and rt #xFF0000))))
+	       (if (bitclear? mask 3)
+		   (set temp (or temp (and rs #xFF000000)))
+		   (set temp (or temp (and rt #xFF000000))))
+	       (set rd temp))
+     ())
+
+(dni mrgbq102 "merge bytes" (ALIAS NO-DIS MACH10 USES-RD USES-RS USES-RT)
+     "mrgb ${rd-rs},$rt,$maskq10"
+     (+ OP_SPECIAL rt rd-rs maskq10 FUNC_MRGB)
+     (sequence ((SI temp))
+	       (if (bitclear? mask 0)
+		   (set temp (and rd-rs #xFF))
+		   (set temp (and rt #xFF)))
+	       (if (bitclear? mask 1)
+		   (set temp (or temp (and rd-rs #xFF00)))
+		   (set temp (or temp (and rt #xFF00))))
+	       (if (bitclear? mask 2)
+		   (set temp (or temp (and rd-rs #xFF0000)))
+		   (set temp (or temp (and rt #xFF0000))))
+	       (if (bitclear? mask 3)
+		   (set temp (or temp (and rd-rs #xFF000000)))
+		   (set temp (or temp (and rt #xFF000000))))
+	       (set rd-rs temp))
+     ())
+
+; In the future, we'll want the j & jal to use the 21 bit target, with 
+; the upper five bits shifted up.  For now, give 'em the 16 bit target.
+
+(dni jq10 "jump" (MACH10)
+     "j $jmptarg"
+     (+ OP_J (f-rs 0) (f-rt 0) jmptarg)
+;     "j $jmptargq10"
+;     (+ OP_J upper-5-jmptargq10 (f-rt 0) lower-16-jmptargq10)
+     (delay 1 (set pc jmptarg))
+     ())
+
+(dni jalq10 "jump and link" (MACH10 USES-RT)
+     "jal $rt,$jmptarg"
+     (+ OP_JAL (f-rs 0) rt jmptarg)
+;     "jal $rt,$jmptargq10"
+;     (+ OP_JAL upper-5-jmptargq10 rt lower-16-jmptargq10)
+     (delay 1
+	    (sequence ()
+		      (set rt (add pc 8))
+		      (set pc jmptarg)))
+     ())
+
+(dni jalq10-2 "jump and link, implied r31" (MACH10 USES-RT)
+     "jal $jmptarg"
+     (+ OP_JAL (f-rs 0) (f-rt 31) jmptarg)
+     (delay 1
+	    (sequence ()
+		      (set rt (add pc 8))
+		      (set pc jmptarg)))
+     ())
+
+; Branch instructions.
+
+(dni bbil "branch bit immediate likely" (MACH10 USES-RS)
+     "bbil $rs($bitnum),$offset"
+     (+ OP10_BBIL rs bitnum offset)
+     (if (bitset? rs bitnum)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+(dni bbinl "branch bit immediate negated likely" (MACH10 USES-RS)
+     "bbinl $rs($bitnum),$offset"
+     (+ OP10_BBINL rs bitnum offset)
+     (if (bitclear? rs bitnum)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+(dni bbvl "branch bit variable likely" (MACH10 USES-RS USES-RT)
+     "bbvl $rs,$rt,$offset"
+     (+ OP10_BBVL rs rt offset)
+     (if (bitset? rs (and rt #x1F))
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+(dni bbvnl "branch bit variable negated likely" (MACH10 USES-RS USES-RT)
+     "bbvnl $rs,$rt,$offset"
+     (+ OP10_BBVNL rs rt offset)
+     (if (bitclear? rs (and rt #x1F))
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+(dni bgtzal "branch if greater than zero and link" (MACH10 USES-RS USES-R31)
+     "bgtzal $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGTZAL offset)
+     (if (gt rs 0)
+	 (sequence ()
+		   (set (reg h-gr 31) (add pc 8))
+		   (delay 1 (set pc offset))))
+     ())
+
+(dni bgtzall
+     "branch if greater than zero and link likely" (MACH10 USES-RS USES-R31)
+     "bgtzall $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGTZALL offset)
+     (if (gt rs 0)
+	 (sequence ()
+		   (set (reg h-gr 31) (add pc 8))
+		   (delay 1 (set pc offset)))
+	 (skip 1))
+     ())
+
+(dni blezal "branch if less than or equal to zero and link" (MACH10 USES-RS USES-R31)
+     "blezal $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLEZAL offset)
+     (if (le rs 0)
+	 (sequence ()
+		   (set (reg h-gr 31) (add pc 8))
+		   (delay 1 (set pc offset))))
+     ())
+
+(dni blezall
+     "branch if less than or equal to zero and link likely" (MACH10 USES-RS USES-R31)
+     "blezall $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLEZALL offset)
+     (if (le rs 0)
+	 (sequence ()
+		   (set (reg h-gr 31) (add pc 8))
+		   (delay 1 (set pc offset)))
+	 (skip 1))
+     ())
+
+(dni bgtz-q10 "branch if greater than zero" (MACH10 USES-RS)
+     "bgtz $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGTZ offset)
+     (if (gt rs 0)
+	 (delay 1 (set pc offset)))
+     ())
+
+(dni bgtzl-q10 "branch if greater than zero likely" (MACH10 USES-RS)
+     "bgtzl $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGTZL offset)
+     (if (gt rs 0)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+
+(dni blez-q10 "branch if less than or equal to zero" (MACH10 USES-RS)
+     "blez $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLEZ offset)
+     (if (le rs 0)
+	 (delay 1 (set pc offset)))
+     ())
+
+(dni blezl-q10 "branch if less than or equal to zero likely" (MACH10 USES-RS)
+     "blezl $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLEZL offset)
+     (if (le rs 0)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+(dni bmb-q10 "branch if matching byte-lane" (MACH10 USES-RS USES-RT)
+     "bmb $rs,$rt,$offset"
+     (+ OP10_BMB rs rt offset)
+     (sequence ((BI branch?))
+	       (set branch? 0)
+	       (if (eq (and rs #xFF) (and rt #xFF))
+		   (set branch? 1))
+	       (if (eq (and rs #xFF00) (and rt #xFF00))
+		   (set branch? 1))
+	       (if (eq (and rs #xFF0000) (and rt #xFF0000))
+		   (set branch? 1))
+	       (if (eq (and rs #xFF000000) (and rt #xFF000000))
+		   (set branch? 1))
+	       (if branch?
+		   (delay 1 (set pc offset))))
+     ())
+
+(dni bmbl "branch if matching byte-lane likely" (MACH10 USES-RS USES-RT)
+     "bmbl $rs,$rt,$offset"
+     (+ OP10_BMBL rs rt offset)
+     (sequence ((BI branch?))
+	       (set branch? 0)
+	       (if (eq (and rs #xFF) (and rt #xFF))
+		   (set branch? 1))
+	       (if (eq (and rs #xFF00) (and rt #xFF00))
+		   (set branch? 1))
+	       (if (eq (and rs #xFF0000) (and rt #xFF0000))
+		   (set branch? 1))
+	       (if (eq (and rs #xFF000000) (and rt #xFF000000))
+		   (set branch? 1))
+	       (if branch?
+		   (delay 1 (set pc offset))
+		   (skip 1)))
+     ())
+
+(dni bri "branch if register invalid" (MACH10 USES-RS)
+     "bri $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BRI offset)
+     (if (gt rs 0)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+(dni brv "branch if register invalid" (MACH10 USES-RS)
+     "brv $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BRV offset)
+     (if (gt rs 0)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+; debug instructions
+
+(dni bctx "branch if the current context == instruction[21]" (MACH10 USES-RS)
+     "bctx $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BCTX offset)
+     (delay 1 (set pc offset))
+     ())
+
+(dni yield "unconditional yield to the other context" (MACH10)
+     "yield"
+     (+ OP_SPECIAL (f-rs 0) (f-rt 0) (f-rd 0) (f-shamt 0) FUNC10_YIELD)
+     (unimp yield)
+     ())
+
+; Special instructions.
+
+(dni crc32 "CRC, 32 bit input" (MACH10 USES-RD USES-RS USES-RT)
+     "crc32 $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32)
+     (unimp crc32)
+     ())
+
+(dni crc32b "CRC, 8 bit input" (MACH10 USES-RD USES-RS USES-RT)
+     "crc32b $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32B)
+     (unimp crc32b)
+     ())
+
+(dni cnt1s "Count ones" (MACH10 USES-RD USES-RS)
+     "cnt1s $rd,$rs"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC10_CNT1S)
+     (unimp crcp)
+     ())
+
+
+; Special Instructions
+
+(dni avail "Mark Header Buffer Available" (MACH10 USES-RD)
+     "avail $rd"
+     (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_AVAIL)
+     (unimp avail)
+     ())
+
+(dni free "Mark Header Buffer Free" (MACH10 USES-RS USES-RD)
+     "free $rd,$rs"
+     (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_FREE)
+     (unimp free)
+     ())
+
+(dni tstod "Test Header Buffer Order Dependency" (MACH10 USES-RS USES-RD)
+     "tstod $rd,$rs"
+     (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_TSTOD)
+     (unimp tstod)
+     ())
+
+(dni cmphdr "Get a Complete Header" (MACH10 USES-RD)
+     "cmphdr $rd"
+     (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_CMPHDR)
+     (unimp cmphdr)
+     ())
+
+(dni mcid "Allocate a Multicast ID" (MACH10 USES-RD USES-RT)
+     "mcid $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_MCID)
+     (unimp mcid)
+     ())
+
+(dni dba "Allocate a Data Buffer Pointer" (MACH10 USES-RD)
+     "dba $rd"
+     (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_DBA)
+     (unimp dba)
+     ())
+
+(dni dbd "Deallocate a Data Buffer Pointer" (MACH10 USES-RS USES-RT USES-RD)
+     "dbd $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_DBD)
+     (unimp dbd)
+     ())
+
+(dni dpwt "DSTN_PORT Write" (MACH10 USES-RS USES-RD)
+     "dpwt $rd,$rs"
+     (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_DPWT)
+     (unimp dpwt)
+     ())
+
+; Architectural and coprocessor instructions.
+
+(dni chkhdrq10 "" (MACH10 USES-RS USES-RD)
+     "chkhdr $rd,$rs"
+     (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_CHKHDR)
+     (unimp chkhdr)
+     ())
+
+; Coprocessor DMA Instructions (IQ10)
+
+(dni rba "Read Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD)
+     "rba $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBA)
+     (unimp rba)
+     ())
+
+(dni rbal "Read Bytes Absolute and Lock" (MACH10 USES-RS USES-RT USES-RD)
+     "rbal $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBAL)
+     (unimp rbal)
+     ())
+
+(dni rbar "Read Bytes Absolute and Release" (MACH10 USES-RS USES-RT USES-RD)
+     "rbar $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBAR)
+     (unimp rbar)
+     ())
+
+(dni wba "Write Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD)
+     "wba $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBA)
+     (unimp wba)
+     ())
+
+(dni wbau "Write Bytes Absolute and Unlock" (MACH10 USES-RS USES-RT USES-RD)
+     "wbau $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBAU)
+     (unimp wbau)
+     ())
+
+(dni wbac "Write Bytes Absolute Cacheable" (MACH10 USES-RS USES-RT USES-RD)
+     "wbac $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBAC)
+     (unimp wbac)
+     ())
+
+(dni rbi "Read Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT)
+     "rbi $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_RBI bytecount)
+     (unimp rbi)
+     ())
+
+(dni rbil "Read Bytes Immediate and Lock" (MACH10 USES-RD USES-RS USES-RT)
+     "rbil $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_RBIL bytecount)
+     (unimp rbil)
+     ())
+
+(dni rbir "Read Bytes Immediate and Release" (MACH10 USES-RD USES-RS USES-RT)
+     "rbir $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_RBIR bytecount)
+     (unimp rbir)
+     ())
+
+(dni wbi "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT)
+     "wbi $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_WBI bytecount)
+     (unimp wbi)
+     ())
+
+(dni wbic "Write Bytes Immediate Cacheable" (MACH10 USES-RD USES-RS USES-RT)
+     "wbic $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_WBIC bytecount)
+     (unimp wbic)
+     ())
+
+(dni wbiu "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT)
+     "wbiu $rd,$rs,$rt,$bytecount"
+     (+ OP_COP3 rs rt rd FUNC10_WBIU bytecount)
+     (unimp wbiu)
+     ())
+
+(dni pkrli "Packet Release Immediate" (MACH10 USES-RD USES-RS USES-RT)
+     "pkrli $rd,$rs,$rt,$bytecount"
+     (+ OP_COP2 rs rt rd FUNC10_PKRLI bytecount)
+     (unimp pkrli)
+     ())
+
+(dni pkrlih "Packet Release Immediate and Hold" (MACH10 USES-RD USES-RS USES-RT)
+     "pkrlih $rd,$rs,$rt,$bytecount"
+     (+ OP_COP2 rs rt rd FUNC10_PKRLIH bytecount)
+     (unimp pkrlih)
+     ())
+
+(dni pkrliu "Packet Release Immediate Unconditional" (MACH10 USES-RD USES-RS USES-RT)
+     "pkrliu $rd,$rs,$rt,$bytecount"
+     (+ OP_COP2 rs rt rd FUNC10_PKRLIU bytecount)
+     (unimp pkrliu)
+     ())
+
+(dni pkrlic "Packet Release Immediate Continue" (MACH10 USES-RD USES-RS USES-RT)
+     "pkrlic $rd,$rs,$rt,$bytecount"
+     (+ OP_COP2 rs rt rd FUNC10_PKRLIC bytecount)
+     (unimp pkrlic)
+     ())
+
+(dni pkrla "Packet Release Absolute" (MACH10 USES-RS USES-RT USES-RD)
+     "pkrla $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLA)
+     (unimp pkrla)
+     ())
+
+(dni pkrlau "Packet Release Absolute Unconditional" (MACH10 USES-RS USES-RT USES-RD)
+     "pkrlau $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLAU)
+     (unimp pkrlau)
+     ())
+
+(dni pkrlah "Packet Release Absolute and Hold" (MACH10 USES-RS USES-RT USES-RD)
+     "pkrlah $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLAH)
+     (unimp pkrlah)
+     ())
+
+(dni pkrlac "Packet Release Absolute Continue" (MACH10 USES-RS USES-RT USES-RD)
+     "pkrlac $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLAC)
+     (unimp pkrlac)
+     ())
+
+; Main Memory Access Instructions
+
+(dni lock "lock memory" (MACH10 USES-RD USES-RT)
+     "lock $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_LOCK)
+     (unimp lock)
+     ())
+
+(dni unlk "unlock memory" (MACH10 USES-RT USES-RD)
+     "unlk $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_UNLK)
+     (unimp unlk)
+     ())
+     
+(dni swrd "Single Word Read" (MACH10 USES-RT USES-RD)
+     "swrd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_SWRD)
+     (unimp swrd)
+     ())
+
+(dni swrdl "Single Word Read and Lock" (MACH10 USES-RT USES-RD)
+     "swrdl $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_SWRDL)
+     (unimp swrdl)
+     ())
+
+(dni swwr "Single Word Write" (MACH10 USES-RS USES-RT USES-RD)
+     "swwr $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_SWWR)
+     (unimp swwr)
+     ())
+
+(dni swwru "Single Word Write and Unlock" (MACH10 USES-RS USES-RT USES-RD)
+     "swwru $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_SWWRU)
+     (unimp swwru)
+     ())
+
+(dni dwrd "Double Word Read" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "dwrd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_DWRD)
+     (unimp dwrd)
+     ())
+
+(dni dwrdl "Double Word Read and Lock" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "dwrdl $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_DWRDL)
+     (unimp dwrdl)
+     ())
+
+; CAM access instructions (IQ10)
+
+(dni cam36 "CAM Access in 36-bit Mode" (MACH10 USES-RT USES-RD)
+     "cam36 $rd,$rt,${cam-z},${cam-y}"
+     (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM36 cam-z cam-y)
+     (unimp cam36)
+     ())
+
+(dni cam72 "CAM Access in 72-bit Mode" (MACH10 USES-RT USES-RD)
+     "cam72 $rd,$rt,${cam-y},${cam-z}"
+     (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM72 cam-z cam-y)
+     (unimp cam72)
+     ())
+
+(dni cam144 "CAM Access in 144-bit Mode" (MACH10 USES-RT USES-RD)
+     "cam144 $rd,$rt,${cam-y},${cam-z}"
+     (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM144 cam-z cam-y)
+     (unimp cam144)
+     ())
+
+(dni cam288 "CAM Access in 288-bit Mode" (MACH10 USES-RT USES-RD)
+     "cam288 $rd,$rt,${cam-y},${cam-z}"
+     (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM288 cam-z cam-y)
+     (unimp cam288)
+     ())
+
+; Counter manager instructions (IQ10)
+
+(dni cm32and "Counter Manager And" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32and $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32AND)
+     (unimp cm32and)
+     ())
+
+(dni cm32andn "Counter Manager And With Inverse" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32andn $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32ANDN)
+     (unimp cm32andn)
+     ())
+
+(dni cm32or "Counter Manager Or" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32or $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32OR)
+     (unimp cm32or)
+     ())
+
+(dni cm32ra "Counter Manager 32-bit Rolling Add" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32ra $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 2) FUNC10_CM32RA)
+     (unimp cm32ra)
+     ())
+
+(dni cm32rd "Counter Manager 32-bit Rolling Decrement" (MACH10 USES-RT USES-RD)
+     "cm32rd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32RD)
+     (unimp cm32rd)
+     ())
+
+(dni cm32ri "Counter Manager 32-bit Rolling Increment" (MACH10 USES-RT USES-RD)
+     "cm32ri $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32RI)
+     (unimp cm32ri)
+     ())
+
+(dni cm32rs "Counter Manager 32-bit Rolling Subtract" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32rs $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-shamt 2) FUNC10_CM32RS)
+     (unimp cm32rs)
+     ())
+
+(dni cm32sa "Counter Manager 32-bit Saturating Add" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32sa $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SA)
+     (unimp cm32sa)
+     ())
+
+(dni cm32sd "Counter Manager 32-bit Saturating Decrement" (MACH10 USES-RT USES-RD)
+     "cm32sd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SD)
+     (unimp cm32sd)
+     ())
+
+(dni cm32si "Counter Manager 32-bit Saturating Increment" (MACH10 USES-RT USES-RD)
+     "cm32si $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SI)
+     (unimp cm32si)
+     ())
+
+(dni cm32ss "Counter Manager 32-bit Saturating Subtract" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32ss $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SS)
+     (unimp cm32ss)
+     ())
+
+(dni cm32xor "Counter Manager Xor" (MACH10 USES-RS USES-RT USES-RD)
+     "cm32xor $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32XOR)
+     (unimp cm32xor)
+     ())
+
+(dni cm64clr "Counter Manager Clear" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "cm64clr $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64CLR)
+     (unimp cm64clr)
+     ())
+
+(dni cm64ra "Counter Manager 64-bit Rolling Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64ra $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RA)
+     (unimp cm64ra)
+     ())
+
+(dni cm64rd "Counter Manager 64-bit Rolling Decrement" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "cm64rd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RD)
+     (unimp cm64rd)
+     ())
+
+(dni cm64ri "Counter Manager 32-bit Rolling Increment" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "cm64ri $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RI)
+     (unimp cm64ri)
+     ())
+
+(dni cm64ria2 "Counter Manager 32/32 Rolling Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64ria2 $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RIA2)
+     (unimp cm64ria2)
+     ())
+
+(dni cm64rs "Counter Manager 64-bit Rolling Subtract" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64rs $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RS)
+     (unimp cm64rs)
+     ())
+
+(dni cm64sa "Counter Manager 64-bit Saturating Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64sa $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SA)
+     (unimp cm64sa)
+     ())
+
+(dni cm64sd "Counter Manager 64-bit Saturating Decrement" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "cm64sd $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SD)
+     (unimp cm64sd)
+     ())
+
+(dni cm64si "Counter Manager 64-bit Saturating Increment" (MACH10 EVEN-REG-NUM USES-RT USES-RD)
+     "cm64si $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SI)
+     (unimp cm64si)
+     ())
+
+(dni cm64sia2 "Counter Manager 32/32 Saturating Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64sia2 $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SIA2)
+     (unimp cm64sia2)
+     ())
+
+(dni cm64ss "Counter Manager 64-bit Saturating Subtract" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm64ss $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SS)
+     (unimp cm64ss)
+     ())
+
+(dni cm128ria2 "Counter Manager 128-bit 64/64 Rolling Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm128ria2 $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128RIA2)
+     (unimp cm128ria2)
+     ())
+
+(dni cm128ria3 "Counter Manager 128-bit 32/32/64 Rolling Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm128ria3 $rd,$rs,$rt,${cm-3z}"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128RIA3 cm-3z)
+     (unimp cm128ria3)
+     ())
+
+(dni cm128ria4 "Counter Manager 128-bit 32/32/32/32 Rolling Inc/Add" (MACH10 USES-RS USES-RT USES-RD)
+     "cm128ria4 $rd,$rs,$rt,${cm-4z}"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128RIA4 cm-4z)
+     (unimp cm128ria4)
+     ())
+
+(dni cm128sia2 "Counter Manager 128-bit 64/64 Saturating Inc/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm128sia2 $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128SIA2)
+     (unimp cm128sia2)
+     ())
+
+(dni cm128sia3 "Counter Manager 128-bit 32/32/64 Saturating Inc/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD)
+     "cm128sia3 $rd,$rs,$rt,${cm-3z}"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128SIA3 cm-3z)
+     (unimp cm128sia3)
+     ())
+
+(dni cm128sia4 "Counter Manager 128-bit 32/32/32/32 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD)
+     "cm128sia4 $rd,$rs,$rt,${cm-4z}"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128SIA4 cm-4z)
+     (unimp cm128sia4)
+     ())
+
+(dni cm128vsa "Counter Manager Continuous State Dual Leaky Token Bucket Policing" (MACH10 USES-RS USES-RT USES-RD)
+     "cm128vsa $rd,$rs,$rt"
+     (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128VSA)
+     (unimp cm128vsa)
+     ())
+
+; Coprocessor Data Movement Instructions
+
+; Note that we don't set the USES-RD or USES-RT attributes for many of the following 
+; instructions, as it's the COP register that's being specified.
+
+; ??? Is YIELD-INSN the right attribute for IQ10?  The IQ2000 used the attribute to warn about 
+; yielding instructions in a delay slot, but that's not relevant in IQ10.  What *is* relevant 
+; (and unique to IQ10) is instructions that yield if the destination register is accessed 
+; before the value is there, causing a yield.
+
+(dni cfc "copy from coprocessor control register" (MACH10 LOAD-DELAY USES-RD YIELD-INSN)
+     "cfc $rd,$rt"
+     (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_CFC)
+     (unimp cfc)
+     ())
+
+(dni ctc "copy to coprocessor control register" (MACH10 USES-RS)
+     "ctc $rs,$rt"
+     (+ OP_COP3 rs rt (f-rd 0) (f-shamt 0) FUNC10_CTC)
+     (unimp ctc)
+     ())
+
+; Macros
+
+(dnmi m-avail "Mark Header Buffer Available" (MACH10 NO-DIS)
+     "avail"
+     (emit avail (f-rd 0))
+)
+
+(dnmi m-cam36 "CAM Access in 36-bit Mode" (MACH10 USES-RT USES-RD NO-DIS)
+     "cam36 $rd,$rt,${cam-z}"
+     (emit cam36 rd rt cam-z (f-cam-y 0))
+)
+
+(dnmi m-cam72 "CAM Access in 72-bit Mode" (MACH10 USES-RT USES-RD NO-DIS)
+     "cam72 $rd,$rt,${cam-z}"
+     (emit cam72 rd rt cam-z (f-cam-y 0))
+)
+
+(dnmi m-cam144 "CAM Access in 144-bit Mode" (MACH10 USES-RT USES-RD NO-DIS)
+     "cam144 $rd,$rt,${cam-z}"
+     (emit cam144 rd rt cam-z (f-cam-y 0))
+)
+
+(dnmi m-cam288 "CAM Access in 288-bit Mode" (MACH10 USES-RT USES-RD NO-DIS)
+     "cam288 $rd,$rt,${cam-z}"
+     (emit cam288 rd rt cam-z (f-cam-y 0))
+)
+
+(dnmi m-cm32read "Counter Manager 32-bit Rolling Add R0" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm32read $rd,$rt"
+     (emit cm32ra rd (f-rs 0) rt)
+)
+
+(dnmi m-cm64read "Counter Manager 64-bit Rolling Add R0" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64read $rd,$rt"
+     (emit cm64ra rd (f-rs 0) rt)
+)
+
+(dnmi m-cm32mlog "Counter Manager 32-bit or R0" (MACH10 USES-RS USES-RT NO-DIS)
+     "cm32mlog $rs,$rt"
+     (emit cm32or (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32and "Counter Manager And" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32and $rs,$rt"
+     (emit cm32and (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32andn "Counter Manager And With Inverse" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32andn $rs,$rt"
+     (emit cm32andn (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32or "Counter Manager Or" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32or $rs,$rt"
+     (emit cm32or (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32ra "Counter Manager 32-bit Rolling Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32ra $rs,$rt"
+     (emit cm32ra (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32rd "Counter Manager 32-bit Rolling Decrement" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm32rd $rt"
+     (emit cm32rd (f-rd 0) rt)
+)
+
+(dnmi m-cm32ri "Counter Manager 32-bit Rolling Increment" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm32ri $rt"
+     (emit cm32ri (f-rd 0) rt)
+)
+
+(dnmi m-cm32rs "Counter Manager 32-bit Rolling Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32rs $rs,$rt"
+     (emit cm32rs (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32sa "Counter Manager 32-bit Saturating Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32sa $rs,$rt"
+     (emit cm32sa (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32sd "Counter Manager 32-bit Saturating Decrement" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm32sd $rt"
+     (emit cm32sd (f-rd 0) rt)
+)
+
+(dnmi m-cm32si "Counter Manager 32-bit Saturating Increment" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm32si $rt"
+     (emit cm32si (f-rd 0) rt)
+)
+
+(dnmi m-cm32ss "Counter Manager 32-bit Saturating Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32ss $rs,$rt"
+     (emit cm32ss (f-rd 0) rs rt)
+)
+
+(dnmi m-cm32xor "Counter Manager Xor" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm32xor $rs,$rt"
+     (emit cm32xor (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64clr "Counter Manager Clear" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64clr $rt"
+     (emit cm64clr (f-rd 0) rt)
+)
+
+(dnmi m-cm64ra "Counter Manager 64-bit Rolling Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64ra $rs,$rt"
+     (emit cm64ra (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64rd "Counter Manager 64-bit Rolling Decrement" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64rd $rt"
+     (emit cm64rd (f-rd 0) rt)
+)
+
+(dnmi m-cm64ri "Counter Manager 32-bit Rolling Increment" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64ri $rt"
+     (emit cm64ri (f-rd 0) rt)
+)
+
+(dnmi m-cm64ria2 "Counter Manager 32/32 Rolling Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64ria2 $rs,$rt"
+     (emit cm64ria2 (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64rs "Counter Manager 64-bit Rolling Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64rs $rs,$rt"
+     (emit cm64rs (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64sa "Counter Manager 64-bit Saturating Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64sa $rs,$rt"
+     (emit cm64sa (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64sd "Counter Manager 64-bit Saturating Decrement" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64sd $rt"
+     (emit cm64sd (f-rd 0) rt)
+)
+
+(dnmi m-cm64si "Counter Manager 64-bit Saturating Increment" (MACH10 USES-RT USES-RD NO-DIS)
+     "cm64si $rt"
+     (emit cm64si (f-rd 0) rt)
+)
+
+(dnmi m-cm64sia2 "Counter Manager 32/32 Saturating Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64sia2 $rs,$rt"
+     (emit cm64sia2 (f-rd 0) rs rt)
+)
+
+(dnmi m-cm64ss "Counter Manager 64-bit Saturating Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm64ss $rs,$rt"
+     (emit cm64ss (f-rd 0) rs rt)
+)
+
+(dnmi m-cm128ria2 "Counter Manager 128-bit 64/64 Rolling Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128ria2 $rs,$rt"
+     (emit cm128ria2 (f-rd 0) rs rt)
+)
+
+(dnmi m-cm128ria3 "Counter Manager 128-bit 32/32/64 Rolling Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128ria3 $rs,$rt,${cm-3z}"
+     (emit cm128ria3 (f-rd 0) rs rt cm-3z)
+)
+
+(dnmi m-cm128ria4 "Counter Manager 128-bit 32/32/32/32 Rolling Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128ria4 $rs,$rt,${cm-4z}"
+     (emit cm128ria4 (f-rd 0) rs rt cm-4z)
+)
+
+(dnmi m-cm128sia2 "Counter Manager 128-bit 64/64 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128sia2 $rs,$rt"
+     (emit cm128sia2 (f-rd 0) rs rt)
+)
+
+(dnmi m-cm128sia3 "Counter Manager 128-bit 32/32/64 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128sia3 $rs,$rt,${cm-3z}"
+     (emit cm128sia3 (f-rd 0) rs rt cm-3z)
+)
+
+(dnmi m-cm128sia4 "Counter Manager 128-bit 32/32/32/32 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "cm128sia4 $rs,$rt,${cm-4z}"
+     (emit cm128sia4 (f-rd 0) rs rt cm-4z)
+)
+
+(dnmi m-cmphdr "Get a Complete Header" (MACH10 NO-DIS)
+     "cmphdr"
+     (emit cmphdr (f-rd 0))
+)
+
+(dnmi m-dbd "Deallocate a Data Buffer Pointer" (MACH10 USES-RD USES-RT NO-DIS)
+     "dbd $rd,$rt"
+     (emit dbd rd (f-rs 0) rt)
+)
+
+(dnmi m2-dbd "Deallocate a Data Buffer Pointer" (MACH10 USES-RT NO-DIS)
+     "dbd $rt"
+     (emit dbd (f-rd 0) (f-rs 0) rt)
+)
+
+(dnmi m-dpwt "DSTN_PORT Write" (MACH10 USES-RS NO-DIS)
+     "dpwt $rs"
+     (emit dpwt (f-rd 0) rs)
+)
+
+(dnmi m-free "" (MACH10 USES-RS USES-RD NO-DIS)
+     "free $rs"
+     (emit free (f-rd 0) rs)
+)
+
+;(dnmi m-jal "jump and link, implied r31" (MACH10 USES-RT NO-DIS)
+;     "jal $jmptarg"
+;     (emit jal (f-rt 31) jmptarg)
+;)
+
+(dnmi m-lock "lock memory" (MACH10 USES-RT NO-DIS)
+     "lock $rt"
+     (emit lock (f-rd 0) rt)
+)
+
+(dnmi m-pkrla "Packet Release Absolute" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "pkrla $rs,$rt"
+     (emit pkrla (f-rd 0) rs rt)
+)
+
+(dnmi m-pkrlac "Packet Release Absolute Continue" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "pkrlac $rs,$rt"
+     (emit pkrlac (f-rd 0) rs rt)
+)
+
+(dnmi m-pkrlah "Packet Release Absolute and Hold" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "pkrlah $rs,$rt"
+     (emit pkrlah (f-rd 0) rs rt)
+)
+
+(dnmi m-pkrlau "Packet Release Absolute Unconditional" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "pkrlau $rs,$rt"
+     (emit pkrlau (f-rd 0) rs rt)
+)
+
+(dnmi m-pkrli "Packet Release Immediate" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "pkrli $rs,$rt,$bytecount"
+     (emit pkrli (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-pkrlic "Packet Release Immediate Continue" (MACH10 USES-RS USES-RT NO-DIS)
+     "pkrlic $rs,$rt,$bytecount"
+     (emit pkrlic (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-pkrlih "Packet Release Immediate and Hold" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "pkrlih $rs,$rt,$bytecount"
+     (emit pkrlih (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-pkrliu "Packet Release Immediate Unconditional" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "pkrliu $rs,$rt,$bytecount"
+     (emit pkrliu (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-rba "Read Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "rba $rs,$rt"
+     (emit rba (f-rd 0) rs rt)
+)
+
+(dnmi m-rbal "Read Bytes Absolute and Lock" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "rbal $rs,$rt"
+     (emit rbal (f-rd 0) rs rt)
+)
+
+(dnmi m-rbar "Read Bytes Absolute and Release" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "rbar $rs,$rt"
+     (emit rbar (f-rd 0) rs rt)
+)
+
+(dnmi m-rbi "Read Bytes Immediate" (MACH10 USES-RS USES-RT NO-DIS)
+     "rbi $rs,$rt,$bytecount"
+     (emit rbi (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-rbil "Read Bytes Immediate and Lock" (MACH10 USES-RS USES-RT NO-DIS)
+     "rbil $rs,$rt,$bytecount"
+     (emit rbil (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-rbir "Read Bytes Immediate and Release" (MACH10 USES-RS USES-RT NO-DIS)
+     "rbir $rs,$rt,$bytecount"
+     (emit rbir (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-swwr "Single Word Write" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "swwr $rs,$rt"
+     (emit swwr (f-rd 0) rs rt)
+)
+
+(dnmi m-swwru "Single Word Write and Unlock" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "swwru $rs,$rt"
+     (emit swwru (f-rd 0) rs rt)
+)
+
+(dnmi m-tstod "Test Header Buffer Order Dependency" (MACH10 USES-RS USES-RD NO-DIS)
+     "tstod $rs"
+     (emit tstod (f-rd 0) rs)
+)
+
+(dnmi m-unlk "" (MACH10 USES-RT USES-RD NO-DIS)
+     "unlk $rt"
+     (emit unlk (f-rd 0) rt)
+)
+     
+(dnmi m-wba "Write Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "wba $rs,$rt"
+     (emit wba (f-rd 0) rs rt)
+)
+
+(dnmi m-wbac "Write Bytes Absolute Cacheable" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "wbac $rs,$rt"
+     (emit wbac (f-rd 0) rs rt)
+)
+
+(dnmi m-wbau "Write Bytes Absolute and Unlock" (MACH10 USES-RS USES-RT USES-RD NO-DIS)
+     "wbau $rs,$rt"
+     (emit wbau (f-rd 0) rs rt)
+)
+
+(dnmi m-wbi "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "wbi $rs,$rt,$bytecount"
+     (emit wbi (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-wbic "Write Bytes Immediate Cacheable" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "wbic $rs,$rt,$bytecount"
+     (emit wbic (f-rd 0) rs rt bytecount)
+)
+
+(dnmi m-wbiu "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT NO-DIS)
+     "wbiu $rs,$rt,$bytecount"
+     (emit wbiu (f-rd 0) rs rt bytecount)
+)
+
Index: iq2000.cpu
===================================================================
RCS file: iq2000.cpu
diff -N iq2000.cpu
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ iq2000.cpu	3 Jun 2003 18:39:08 -0000
@@ -0,0 +1,1199 @@
+; IQ2000/IQ10 Common CPU description. -*- Scheme -*-
+;
+; Copyright 2000, 2001, 2002 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc; developed under contract from Vitesse.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 2 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+(include "simplify.inc")
+
+(define-arch
+  (name iq2000)
+  (comment "IQ2000 architecture")
+  (insn-lsb0? #t)
+  (machs iq2000 iq10)
+  (isas iq2000)
+)
+
+(define-isa
+  (name iq2000)
+  (comment "Basic IQ2000 instruction set")
+  (default-insn-word-bitsize 32)
+  (default-insn-bitsize 32)
+  (base-insn-bitsize 32)
+  (decode-assist (31 30 29 28 27 26))
+)
+
+(define-cpu
+  (name iq2000bf)
+  (comment "IQ2000 family")
+  (endian big)
+  (word-bitsize 32)
+  (file-transform "")
+)
+
+(define-cpu
+  (name iq10bf)
+  (comment "IQ10 coprocessor family")
+  (endian big)
+  (word-bitsize 32)
+  (file-transform "")
+
+)
+
+(define-mach
+  (name iq2000)
+  (comment "IQ2000 packet processing engine")
+  (cpu iq2000bf)
+  (isas iq2000)
+)
+
+(define-mach
+  (name iq10)
+  (comment "IQ10 coprocessor")
+  (cpu iq10bf)
+  (isas iq2000)
+)
+
+(define-model
+  (name iq2000)
+  (comment "IQ2000 microprocessor")
+  (mach iq2000)
+  (unit u-exec "Execution Unit" ()
+	1 1 ; issue done
+	() () () ())
+)
+
+(define-model
+  (name iq10)
+  (comment "IQ10 coprocessor")
+  (mach iq10)
+  (unit u-exec "Execution Unit" ()
+	1 1 ; issue done
+	() () () ())
+)
+
+; Macros to simplify MACH attribute specification.
+
+(define-pmacro MACH2000 (MACH iq2000))
+(define-pmacro MACH10 (MACH iq10))
+
+
+; Hardware elements.
+
+(define-hardware
+  (name h-pc)
+  (comment "program counter")
+  (attrs PC PROFILE (ISA iq2000))
+  (type pc)
+  (get () (c-call USI "get_h_pc"))
+  (set (newval) (c-call VOID "set_h_pc" newval))
+)
+; FIXME: it would be nice if the hardwired zero in R0 could be
+; specified as a virtual hardware element, with one less register in
+; the register file proper.
+
+(define-keyword
+  (name gr-names)
+  (print-name h-gr)
+  (values (r0 0)   (%0 0)   (r1 1)   (%1 1)   (r2 2)   (%2 2)   (r3 3)   (%3 3)  
+          (r4 4)   (%4 4)   (r5 5)   (%5 5)   (r6 6)   (%6 6)   (r7 7)   (%7 7)
+          (r8 8)   (%8 8)   (r9 9)   (%9 9)   (r10 10) (%10 10) (r11 11) (%11 11)
+          (r12 12) (%12 12) (r13 13) (%13 13) (r14 14) (%14 14) (r15 15) (%15 15) 
+          (r16 16) (%16 16) (r17 17) (%17 17) (r18 18) (%18 18) (r19 19) (%19 19) 
+          (r20 20) (%20 20) (r21 21) (%21 21) (r22 22) (%22 22) (r23 23) (%23 23)
+          (r24 24) (%24 24) (r25 25) (%25 25) (r26 26) (%26 26) (r27 27) (%27 27) 
+          (r28 28) (%28 28) (r29 29) (%29 29) (r30 30) (%30 30) (r31 31) (%31 31))
+)
+
+(define-hardware 
+  (name h-gr)
+  (comment "General purpose registers")
+;  (attrs (ISA iq2000) CACHE-ADDR)
+  (type register SI (32))
+  (indices extern-keyword gr-names)
+  (get (idx)
+       (cond SI
+	     ((eq idx 0) (const 0))
+	     (else (raw-reg h-gr idx))))
+  (set (idx newval)
+       (cond VOID
+	     ((eq idx 0) (nop))
+	     (else (set (raw-reg h-gr idx) newval))))
+)
+
+
+; Instruction fields.
+
+(dnf f-opcode   "opcode field"                  ()  31  6)
+(dnf f-rs       "register field Rs"             ()  25  5)
+(dnf f-rt       "register field Rt"             ()  20  5)
+(dnf f-rd       "register field Rd"             ()  15  5)
+(dnf f-shamt    "shift amount field"            ()  10  5)
+(dnf f-cp-op    "coprocessor op field"		()  10  3)
+(dnf f-cp-op-10 "coprocessor op field for CAM"  ()  10  5)
+(dnf f-cp-grp   "coprocessor group field"	()   7  2)
+(dnf f-func     "function field"                ()   5  6)
+(dnf f-imm      "immediate field"               ()  15 16)
+
+(define-multi-ifield
+  (name f-rd-rs)
+  (comment "register Rd implied from Rs")
+  (attrs)
+  (mode UINT)
+  (subfields f-rd f-rs)
+  (insert (sequence ()
+		    (set (ifield f-rd) (ifield f-rd-rs))
+		    (set (ifield f-rs) (ifield f-rd-rs))
+		     ))
+  (extract (sequence ()
+                     (set (ifield f-rd-rs) (ifield f-rs))
+                     ))
+)
+
+(define-multi-ifield
+  (name f-rd-rt)
+  (comment "register Rd implied from Rt")
+  (attrs)
+  (mode UINT)
+  (subfields f-rd f-rt)
+  (insert (sequence ()
+		    (set (ifield f-rd) (ifield f-rd-rt))
+		    (set (ifield f-rt) (ifield f-rd-rt))
+		     ))
+  (extract (sequence ()
+                     (set (ifield f-rd-rt) (ifield f-rt))
+                     ))
+)
+
+(define-multi-ifield
+  (name f-rt-rs)
+  (comment "register Rt implied from Rs")
+  (attrs)
+  (mode UINT)
+  (subfields f-rt f-rs)
+  (insert (sequence ()
+		    (set (ifield f-rt) (ifield f-rt-rs))
+		    (set (ifield f-rs) (ifield f-rt-rs))
+		     ))
+  (extract (sequence ()
+                     (set (ifield f-rd-rs) (ifield f-rs))
+                     ))
+)
+
+(df  f-jtarg "jump target field"               (ABS-ADDR) 15 16 UINT
+     ((value pc) (srl USI (and USI value #x03FFFF) 2))
+     ((value pc) (or USI (and USI pc #xF0000000) (sll USI value 2))))
+
+(df  f-jtargq10 "iq10 jump target field"       (ABS-ADDR) 20 21 UINT
+     ((value pc) (srl SI (and SI value #x7FFFFF) 2))
+     ((value pc) (or SI (and SI pc #xF0000000) (sll SI value 2))))
+
+(df  f-offset "pc offset field"                (PCREL-ADDR) 15 16 INT
+     ; Actually, this is relative to the address of the delay slot.
+     ((value pc) (sra SI (sub SI value pc) 2))
+     ((value pc) (add SI (sll SI value 2) (add pc 4))))
+
+; Instruction fields that scarcely appear in instructions.
+
+(dnf f-count   "count field"        ()   15  7)
+(dnf f-bytecount "byte count field" ()    7  8)
+(dnf f-index   "index field"        ()    8  9)
+(dnf f-mask    "mask field"         ()    9  4)
+(dnf f-maskq10 "iq10 mask field"    ()   10  5)
+(dnf f-maskl   "mask left field"    ()    4  5)
+(dnf f-excode  "execcode field"     ()   25 20)
+(dnf f-rsrvd   "reserved field"     ()   25 10)
+(dnf f-10-11   "bits 10:0"          ()   10 11)
+(dnf f-24-19   "bits 24:6"          ()   24 19)
+(dnf f-5       "bit 5"              ()    5  1)
+(dnf f-10      "bit 10"             ()   10  1)
+(dnf f-25      "bit 25"             ()   25  1)
+(dnf f-cam-z   "cam global mask z"  ()    5  3)
+(dnf f-cam-y   "cam operation y"    ()    2  3)
+(dnf f-cm-3func "CM 3 bit fn field" ()    5  3)
+(dnf f-cm-4func "CM 4 bit fn field" ()    5  4)
+(dnf f-cm-3z   "CM 3Z field"        ()    1  2)
+(dnf f-cm-4z   "CM 4Z field"        ()    2  3)
+
+
+; Enumerations.
+
+(define-normal-insn-enum
+  opcodes "primary opcodes" () OP_ f-opcode
+  (("SPECIAL" 0) ("REGIMM" 1) ("J"     2) ("JAL"    3) ("BEQ"    4) ("BNE"   5) ("BLEZ"   6) ("BGTZ"    7) 
+   ("ADDI"    8) ("ADDIU"  9) ("SLTI" 10) ("SLTIU" 11) ("ANDI"  12) ("ORI"  13) ("XORI"  14) ("LUI"    15)
+   ("COP0"   16) ("COP1"  17) ("COP2" 18) ("COP3"  19) ("BEQL"  20) ("BNEL" 21) ("BLEZL" 22) ("BGTZL"  23) 
+   ("BMB0"   24) ("BMB1"  25) ("BMB2" 26) ("BMB3"  27) ("BBI"   28) ("BBV"  29) ("BBIN"  30) ("BBVN"   31) 
+   ("LB"     32) ("LH"    33)             ("LW"    35) ("LBU"   36) ("LHU"  37)              ("RAM"    39)  
+   ("SB"     40) ("SH"    41)             ("SW"    43) ("ANDOI" 44) ("BMB"  45)              ("ORUI"   47) 
+   ("LDW"    48) 
+   ("SDW"    56)                                                                             ("ANDOUI" 63))
+)
+
+(define-normal-insn-enum
+  q10_opcodes "iq10-only primary opcodes" () OP10_ f-opcode
+  (("BMB" 6) ("ORUI" 15) ("BMBL" 22) ("ANDOUI" 47) ("BBIL" 60) ("BBVL" 61) ("BBINL" 62) ("BBVNL" 63))
+)
+
+(define-normal-insn-enum
+  regimm-functions "branch sub-opcodes" () FUNC_ f-rt
+  (("BLTZ"    0) ("BGEZ"    1) ("BLTZL"    2) ("BGEZL"    3) ("BLEZ"    4) ("BGTZ"    5) ("BLEZL"    6) ("BGTZL"    7) 
+   ("BRI"     8) ("BRV"     9)                               ("BCTX"   12) 
+   ("BLTZAL" 16) ("BGEZAL" 17) ("BLTZALL" 18) ("BGEZALL" 19) ("BLEZAL" 20) ("BGTZAL" 21) ("BLEZALL" 22) ("BGTZALL" 23))
+)
+
+(define-normal-insn-enum
+  functions "function sub-opcodes" () FUNC_ f-func
+  (("SLL"  0) ("SLMV"   1) ("SRL"  2) ("SRA"   3) ("SLLV"     4) ("SRMV"   5) ("SRLV"   6) ("SRAV" 7) 
+   ("JR"   8) ("JALR"   9) ("JCR" 10)             ("SYSCALL" 12) ("BREAK" 13) ("SLEEP" 14)
+   ("ADD" 32) ("ADDU"  33) ("SUB" 34) ("SUBU" 35) ("AND"     36) ("OR"    37) ("XOR"   38) ("NOR" 39) 
+              ("ADO16" 41) ("SLT" 42) ("SLTU" 43)                ("MRGB"  45))
+)
+
+; iq10 special function sub-opcodes
+(define-normal-insn-enum
+  q10s_functions "iq10-only special function sub-opcodes" () FUNC10_ f-func
+  (("YIELD" 14) ("CNT1S" 46))
+)
+
+; coprocessor opcodes in concert with f-cp-grp
+(define-normal-insn-enum
+  cop_functions "iq10 function sub-opcodes" () FUNC10_ f-func
+  (("CFC"    0) ("LOCK"    1) ("CTC"     2) ("UNLK"    3) ("SWRD"    4) ("SWRDL"   5) ("SWWR"    6) ("SWWRU"  7) 
+   ("RBA"    8) ("RBAL"    9) ("RBAR"   10)               ("DWRD"   12) ("DWRDL"  13) 
+   ("WBA"   16) ("WBAU"   17) ("WBAC"   18)               ("CRC32"  20) ("CRC32B" 21) 
+   ("MCID"  32) ("DBD"    33) ("DBA"    34) ("DPWT"   35) ("AVAIL"  36) ("FREE"   37) ("CHKHDR" 38) ("TSTOD" 39)
+   ("PKRLA" 40) ("PKRLAU" 41) ("PKRLAH" 42) ("PKRLAC" 43) ("CMPHDR" 44) 
+
+   ("CM64RS"  0) ("CM64RD"  1)                                ("CM64RI"    4) ("CM64CLR"    5)
+   ("CM64SS"  8) ("CM64SD"  9)                                ("CM64SI"   12) 
+   ("CM64RA" 16)                                              ("CM64RIA2" 20) ("CM128RIA2" 21)
+   ("CM64SA" 24)                                              ("CM64SIA2" 28) ("CM128SIA2" 29)
+   ("CM32RS" 32) ("CM32RD" 33) ("CM32XOR" 34) ("CM32ANDN" 35) ("CM32RI"   36)                  ("CM128VSA" 38)
+   ("CM32SS" 40) ("CM32SD" 41) ("CM32OR"  42) ("CM32AND"  43) ("CM32SI"   44) 
+   ("CM32RA" 48)  
+   ("CM32SA" 56) )
+)
+
+; coprocessor opcodes in concert with f-cp-grp
+(define-normal-insn-enum
+  cop_cm128_4functions "iq10 function sub-opcodes" () FUNC10_ f-cm-4func
+  (("CM128RIA3" 4) ("CM128SIA3" 6))
+)
+
+(define-normal-insn-enum
+  cop_cm128_3functions "iq10 function sub-opcodes" () FUNC10_ f-cm-3func
+  (("CM128RIA4" 6) ("CM128SIA4" 7))
+)
+
+(define-normal-insn-enum
+   cop2_functions "iq10 coprocessor sub-opcodes" () FUNC10_ f-cp-op
+   (("PKRLI" 0) ("PKRLIU" 1) ("PKRLIH" 2) ("PKRLIC" 3) ("RBIR" 1) ("RBI" 2) ("RBIL" 3) ("WBIC" 5) ("WBI" 6) ("WBIU" 7))
+)
+
+(define-normal-insn-enum
+   cop3_cam_functions "iq10 coprocessor cam sub-opcodes" () FUNC10_ f-cp-op-10
+   (("CAM36" 16) ("CAM72" 17) ("CAM144" 18) ("CAM288" 19))
+)
+
+
+; Attributes.
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name YIELD-INSN)
+  (comment "insn generates a context yield")
+)
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name LOAD-DELAY)
+  (comment "insn has a load delay")
+)
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name EVEN-REG-NUM)
+  (comment "insn requires an even numbered register in rt(2000) or rd(10)")
+)
+
+(define-attr
+  (for insn)
+  (type boolean)
+  (name UNSUPPORTED)
+  (comment "insn is unsupported")
+)
+
+(define-pmacro (define-reg-use-attr regfield)
+  (define-attr
+    (for insn)
+    (type boolean)
+    (name (.sym USES- (.upcase regfield)))
+    (comment ("insn accesses register operand " regfield))))
+
+(define-reg-use-attr rd)
+(define-reg-use-attr rs)
+(define-reg-use-attr rt)
+(define-reg-use-attr r31)
+
+
+; Operands.
+
+(dnop rs       "register Rs"             () h-gr    f-rs)
+(dnop rt       "register Rt"             () h-gr    f-rt)
+(dnop rd       "register Rd"             () h-gr    f-rd)
+(dnop rd-rs    "register Rd from Rs"     () h-gr    f-rd-rs)
+(dnop rd-rt    "register Rd from Rt"     () h-gr    f-rd-rt)
+(dnop rt-rs    "register Rt from Rs"     () h-gr    f-rt-rs)
+(dnop shamt    "shift amount"            () h-uint  f-shamt)
+(define-operand (name imm) (comment "immediate") (attrs)
+   (type h-uint) (index f-imm) (handlers (parse "imm")))
+(dnop offset   "pc-relative offset"      () h-iaddr f-offset)
+(dnop baseoff  "base register offset"    () h-iaddr f-imm)
+(dnop jmptarg  "jump target"             () h-iaddr f-jtarg)
+(dnop mask     "mask"                    () h-uint  f-mask)
+(dnop maskq10  "iq10 mask"               () h-uint  f-maskq10)
+(dnop maskl    "mask left"               () h-uint  f-maskl)
+(dnop count    "count"                   () h-uint  f-count)
+(dnop index    "index"                   () h-uint  f-index)
+(dnop execode  "execcode"                () h-uint  f-excode)
+(dnop bytecount "byte count"             () h-uint  f-bytecount)
+(dnop cam-y     "cam global opn y"       () h-uint  f-cam-y)
+(dnop cam-z     "cam global mask z"      () h-uint  f-cam-z)
+(dnop cm-3func  "CM 3 bit fn field"      () h-uint  f-cm-3func)
+(dnop cm-4func  "CM 4 bit fn field"      () h-uint  f-cm-4func)
+(dnop cm-3z     "CM 3 bit Z field"       () h-uint  f-cm-3z)
+(dnop cm-4z     "CM 4 bit Z field"       () h-uint  f-cm-4z)
+
+; Aliases for the rs and rt operands. This just makes the load/store
+; insns easier to compare with the instruction set documentation.
+
+(dnop base    "base register"                  () h-gr   f-rs)
+(dnop maskr   "mask right"                     () h-uint f-rs)
+(dnop bitnum  "bit number"                     () h-uint f-rt)
+
+; For high(foo).
+(define-operand
+  (name hi16)
+  (comment "high 16 bit immediate")
+  (attrs)
+  (type h-uint)
+  (index f-imm)
+  (handlers (parse "hi16"))
+)
+
+; For low(foo).
+(define-operand
+  (name lo16)
+  (comment "16 bit signed immediate, for low")
+  (attrs)
+  (type h-uint)
+  (index f-imm)
+  (handlers (parse "lo16"))
+)
+
+; For negated imm.
+(define-operand
+  (name mlo16)
+  (comment "negated 16 bit signed immediate")
+  (attrs)
+  (type h-uint)
+  (index f-imm)
+  (handlers (parse "mlo16"))
+)
+
+; For iq10 jmps
+; In the future, we'll want the j & jal to use the 21 bit target, with 
+; the upper five bits shifted up.  For now, don't use this.
+(define-operand
+  (name jmptargq10)
+  (comment "iq10 21-bit jump offset")
+  (attrs)
+  (type h-iaddr)
+  (index f-jtargq10)
+  (handlers (parse "jtargq10"))
+)
+
+
+; Instructions.
+
+; A pmacro for use in semantic bodies of unimplemented insns.
+(define-pmacro (unimp mnemonic) (nop))
+
+(define-pmacro (bitset? value bit-num)
+  (and value (sll 1 bit-num)))
+
+(define-pmacro (bitclear? value bit-num)
+  (not (bitset? value bit-num)))
+
+; Arithmetic/logic instructions.
+
+(dni add2 "add registers" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "add ${rd-rs},$rt"
+     (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_ADD)
+     (set rd-rs (add rt rd-rs))
+     ())
+
+(dni add "add registers" (USES-RD USES-RS USES-RT)
+     "add $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADD)
+     (set rd (add rs rt))
+     ())
+
+
+(dni addi2 "add immediate" (ALIAS NO-DIS USES-RS USES-RT)
+     "addi ${rt-rs},$lo16"
+     (+ OP_ADDI rt-rs lo16)
+     (set rt-rs (add rt-rs (ext SI (trunc HI lo16))))
+     ())
+
+(dni addi "add immediate" (USES-RS USES-RT)
+     "addi $rt,$rs,$lo16"
+     (+ OP_ADDI rs rt lo16)
+     (set rt (add rs (ext SI (trunc HI lo16))))
+     ())
+
+(dni addiu2 "add immediate unsigned" (ALIAS NO-DIS USES-RS USES-RT)
+     "addiu ${rt-rs},$lo16"
+     (+ OP_ADDIU rt-rs lo16)
+     (set rt-rs (add rt-rs (ext SI (trunc HI lo16))))
+     ())
+
+(dni addiu "add immediate unsigned" (USES-RS USES-RT)
+     "addiu $rt,$rs,$lo16"
+     (+ OP_ADDIU rs rt lo16)
+     (set rt (add rs (ext SI (trunc HI lo16))))
+     ())
+
+(dni addu2 "add unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "addu ${rd-rs},$rt"
+     (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADDU)
+     (set rd-rs (add rd-rs rt))
+     ())
+
+(dni addu "add unsigned" (USES-RD USES-RS USES-RT)
+     "addu $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADDU)
+     (set rd (add rs rt))
+     ())
+
+(dni ado162 "add 16, ones complement" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "ado16 ${rd-rs},$rt"
+     (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADO16)
+     (sequence ((HI high) (HI low))
+	       (set low (add HI (and HI rd-rs #xFFFF) (and HI rt #xFFFF)))
+	       (set high (add HI (srl rd-rs 16) (srl rt 16)))
+	       (set rd-rs (or SI (sll SI high 16) low)))
+     ())
+
+(dni ado16 "add 16, ones complement" (USES-RD USES-RS USES-RT)
+     "ado16 $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADO16)
+     (sequence ((HI high) (HI low))
+	       (set low (add HI (and HI rs #xFFFF) (and HI rt #xFFFF)))
+	       (set high (add HI (srl rs 16) (srl rt 16)))
+	       (set rd (or SI (sll SI high 16) low)))
+     ())
+
+(dni and2 "and register" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "and ${rd-rs},$rt"
+     (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_AND)
+     (set rd-rs (and rd-rs rt))
+     ())
+
+(dni and "and register" (USES-RD USES-RS USES-RT)
+     "and $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_AND)
+     (set rd (and rs rt))
+     ())
+
+(dni andi2 "and immediate" (ALIAS NO-DIS USES-RS USES-RT)
+     "andi ${rt-rs},$lo16"
+     (+ OP_ANDI rt-rs lo16)
+     (set rt-rs (and rt-rs (zext SI lo16)))
+     ())
+
+(dni andi "and immediate" (USES-RS USES-RT)
+     "andi $rt,$rs,$lo16"
+     (+ OP_ANDI rs rt lo16)
+     (set rt (and rs (zext SI lo16)))
+     ())
+
+(dni andoi2 "and ones immediate" (ALIAS NO-DIS USES-RS USES-RT)
+     "andoi ${rt-rs},$lo16"
+     (+ OP_ANDOI rt-rs lo16)
+     (set rt-rs (and rt-rs (or #xFFFF0000 (ext SI (trunc HI lo16)))))
+     ())
+
+(dni andoi "and ones immediate" (USES-RS USES-RT)
+     "andoi $rt,$rs,$lo16"
+     (+ OP_ANDOI rs rt lo16)
+     (set rt (and rs (or #xFFFF0000 (ext SI (trunc HI lo16)))))
+     ())
+
+(dni nor2 "nor" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "nor ${rd-rs},$rt"
+     (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_NOR)
+     (set rd-rs (inv (or rd-rs rt)))
+     ())
+
+(dni nor "nor" (USES-RD USES-RS USES-RT)
+     "nor $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_NOR)
+     (set rd (inv (or rs rt)))
+     ())
+
+(dni or2 "or" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "or ${rd-rs},$rt"
+     (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_OR)
+     (set rd-rs (or rd-rs rt))
+     ())
+
+(dni or "or" (USES-RD USES-RS USES-RT)
+     "or $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_OR)
+     (set rd (or rs rt))
+     ())
+
+(dni ori2 "or immediate" (ALIAS NO-DIS USES-RS USES-RT)
+     "ori ${rt-rs},$lo16"
+     (+ OP_ORI rt-rs lo16)
+     (set rt-rs (or rt-rs (zext SI lo16)))
+     ())
+
+(dni ori "or immediate" (USES-RS USES-RT)
+     "ori $rt,$rs,$lo16"
+     (+ OP_ORI rs rt lo16)
+     (set rt (or rs (zext SI lo16)))
+     ())
+
+(dni ram "rotate and mask" (USES-RD USES-RT)
+     "ram $rd,$rt,$shamt,$maskl,$maskr"
+     (+ OP_RAM maskr rt rd shamt (f-5 0) maskl)
+     (sequence ()
+	       (set rd (ror rt shamt))
+	       (set rd (and rd (srl #xFFFFFFFF maskl)))
+	       (set rd (and rd (sll #xFFFFFFFF maskr))))
+     ())
+
+(dni sll "shift left logical" (USES-RD USES-RT)
+     "sll $rd,$rt,$shamt"
+     (+ OP_SPECIAL (f-rs 0) rt rd shamt (f-func 0))
+     (set rd (sll rt shamt))
+     ())
+
+(dni sllv2 "shift left logical variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "sllv ${rd-rt},$rs"
+     (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SLLV)
+     (set rd-rt (sll rd-rt (and rs #x1F)))
+     ())
+
+(dni sllv "shift left logical variable" (USES-RD USES-RS USES-RT)
+     "sllv $rd,$rt,$rs"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLLV)
+     (set rd (sll rt (and rs #x1F)))
+     ())
+
+(dni slmv2 "shift left and mask variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "slmv ${rd-rt},$rs,$shamt"
+     (+ OP_SPECIAL rs rd-rt shamt FUNC_SLMV)
+     (set rd-rt (and (sll rd-rt shamt) (srl #xFFFFFFFF rs)))
+     ())
+
+(dni slmv "shift left and mask variable" (USES-RD USES-RS USES-RT)
+     "slmv $rd,$rt,$rs,$shamt"
+     (+ OP_SPECIAL rs rt rd shamt FUNC_SLMV)
+     (set rd (and (sll rt shamt) (srl #xFFFFFFFF rs)))
+     ())
+
+(dni slt2 "set if less than" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "slt ${rd-rs},$rt"
+     (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SLT)
+     (if (lt rd-rs rt)
+	 (set rd-rs 1)
+	 (set rd-rs 0))
+     ())
+
+(dni slt "set if less than" (USES-RD USES-RS USES-RT)
+     "slt $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLT)
+     (if (lt rs rt)
+	 (set rd 1)
+	 (set rd 0))
+     ())
+
+(dni slti2 "set if less than immediate" (ALIAS NO-DIS USES-RS USES-RT)
+     "slti ${rt-rs},$imm"
+     (+ OP_SLTI rt-rs imm)
+     (if (lt rt-rs (ext SI (trunc HI imm)))
+	 (set rt-rs 1)
+	 (set rt-rs 0))
+     ())
+
+(dni slti "set if less than immediate" (USES-RS USES-RT)
+     "slti $rt,$rs,$imm"
+     (+ OP_SLTI rs rt imm)
+     (if (lt rs (ext SI (trunc HI imm)))
+	 (set rt 1)
+	 (set rt 0))
+     ())
+
+(dni sltiu2 "set if less than immediate unsigned" (ALIAS NO-DIS USES-RS USES-RT)
+     "sltiu ${rt-rs},$imm"
+     (+ OP_SLTIU rt-rs imm)
+     (if (ltu rt-rs (ext SI (trunc HI imm)))
+	 (set rt-rs 1)
+	 (set rt-rs 0))
+     ())
+
+(dni sltiu "set if less than immediate unsigned" (USES-RS USES-RT)
+     "sltiu $rt,$rs,$imm"
+     (+ OP_SLTIU rs rt imm)
+     (if (ltu rs (ext SI (trunc HI imm)))
+	 (set rt 1)
+	 (set rt 0))
+     ())
+
+(dni sltu2 "set if less than unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "sltu ${rd-rs},$rt"
+     (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_SLTU)
+     (if (ltu rd-rs rt)
+	 (set rd-rs 1)
+	 (set rd-rs 0))
+     ())
+
+(dni sltu "set if less than unsigned" (USES-RD USES-RS USES-RT)
+     "sltu $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLTU)
+     (if (ltu rs rt)
+	 (set rd 1)
+	 (set rd 0))
+     ())
+
+(dni sra2 "shift right arithmetic" (ALIAS NO-DIS USES-RD USES-RT)
+     "sra ${rd-rt},$shamt"
+     (+ OP_SPECIAL (f-rs 0) rd-rt shamt FUNC_SRA)
+     (set rd-rt (sra rd-rt shamt))
+     ())
+
+(dni sra "shift right arithmetic" (USES-RD USES-RT)
+     "sra $rd,$rt,$shamt"
+     (+ OP_SPECIAL (f-rs 0) rt rd shamt FUNC_SRA)
+     (set rd (sra rt shamt))
+     ())
+
+(dni srav2 "shift right arithmetic variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "srav ${rd-rt},$rs"
+     (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SRAV)
+     (set rd-rt (sra rd-rt (and rs #x1F)))
+     ())
+
+(dni srav "shift right arithmetic variable" (USES-RD USES-RS USES-RT)
+     "srav $rd,$rt,$rs"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SRAV)
+     (set rd (sra rt (and rs #x1F)))
+     ())
+
+(dni srl "shift right logical" (USES-RD USES-RT)
+     "srl $rd,$rt,$shamt"
+     (+ OP_SPECIAL (f-rs 0) rt rd shamt FUNC_SRL)
+     (set rd (srl rt shamt))
+     ())
+
+(dni srlv2 "shift right logical variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "srlv ${rd-rt},$rs"
+     (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SRLV)
+     (set rd-rt (srl rd-rt (and rs #x1F)))
+     ())
+
+(dni srlv "shift right logical variable" (USES-RD USES-RS USES-RT)
+     "srlv $rd,$rt,$rs"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SRLV)
+     (set rd (srl rt (and rs #x1F)))
+     ())
+
+(dni srmv2 "shift right and mask variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "srmv ${rd-rt},$rs,$shamt"
+     (+ OP_SPECIAL rs rd-rt shamt FUNC_SRMV)
+     (set rd-rt (and (srl rd-rt shamt) (sll #xFFFFFFFF rs)))
+     ())
+
+(dni srmv "shift right and mask variable" (USES-RD USES-RS USES-RT)
+     "srmv $rd,$rt,$rs,$shamt"
+     (+ OP_SPECIAL rs rt rd shamt FUNC_SRMV)
+     (set rd (and (srl rt shamt) (sll #xFFFFFFFF rs)))
+     ())
+
+(dni sub2 "subtract" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "sub ${rd-rs},$rt"
+     (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SUB)
+     (set rd-rs (sub rd-rs rt))
+     ())
+
+(dni sub "subtract" (USES-RD USES-RS USES-RT)
+     "sub $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SUB)
+     (set rd (sub rs rt))
+     ())
+
+(dni subu2 "subtract unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "subu ${rd-rs},$rt"
+     (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SUBU)
+     (set rd-rs (sub rd-rs rt))
+     ())
+
+(dni subu "subtract unsigned" (USES-RD USES-RS USES-RT)
+     "subu $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SUBU)
+     (set rd (sub rs rt))
+     ())
+
+(dni xor2 "exclusive or" (ALIAS NO-DIS USES-RD USES-RS USES-RT)
+     "xor ${rd-rs},$rt"
+     (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_XOR)
+     (set rd-rs (xor rd-rs rt))
+     ())
+
+(dni xor "exclusive or" (USES-RD USES-RS USES-RT)
+     "xor $rd,$rs,$rt"
+     (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_XOR)
+     (set rd (xor rs rt))
+     ())
+
+(dni xori2 "exclusive or immediate" (ALIAS NO-DIS USES-RS USES-RT)
+     "xori ${rt-rs},$lo16"
+     (+ OP_XORI rt-rs lo16)
+     (set rt-rs (xor rt-rs (zext SI lo16)))
+     ())
+
+(dni xori "exclusive or immediate" (USES-RS USES-RT)
+     "xori $rt,$rs,$lo16"
+     (+ OP_XORI rs rt lo16)
+     (set rt (xor rs (zext SI lo16)))
+     ())
+
+
+; Branch instructions.
+
+(dni bbi "branch bit immediate" (USES-RS)
+     "bbi $rs($bitnum),$offset"
+     (+ OP_BBI rs bitnum offset)
+     (if (bitset? rs bitnum)
+	 (delay 1 (set pc offset)))
+     ())
+
+(dni bbin "branch bit immediate negated" (USES-RS)
+     "bbin $rs($bitnum),$offset"
+     (+ OP_BBIN rs bitnum offset)
+     (if (bitclear? rs bitnum)
+	 (delay 1 (set pc offset)))
+     ())
+
+(dni bbv "branch bit variable" (USES-RS USES-RT)
+     "bbv $rs,$rt,$offset"
+     (+ OP_BBV rs rt offset)
+     (if (bitset? rs (and rt #x1F))
+	 (delay 1 (set pc offset)))
+     ())
+
+(dni bbvn "branch bit variable negated" (USES-RS USES-RT)
+     "bbvn $rs,$rt,$offset"
+     (+ OP_BBVN rs rt offset)
+     (if (bitclear? rs (and rt #x1F))
+	 (delay 1 (set pc offset)))
+     ())
+
+(dni beq "branch if equal" (USES-RS USES-RT)
+     "beq $rs,$rt,$offset"
+     (+ OP_BEQ rs rt offset)
+     (if (eq rs rt)
+	 (delay 1 (set pc offset)))
+     ())
+
+(dni beql "branch if equal likely" (USES-RS USES-RT)
+     "beql $rs,$rt,$offset"
+     (+ OP_BEQL rs rt offset)
+     (if (eq rs rt)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+(dni bgez "branch if greater than or equal to zero" (USES-RS)
+     "bgez $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGEZ offset)
+     (if (ge rs 0)
+	 (delay 1 (set pc offset)))
+     ())
+
+(dni bgezal "branch if greater than or equal to zero and link" (USES-RS USES-R31)
+     "bgezal $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGEZAL offset)
+     (if (ge rs 0)
+	 (sequence ()
+		   (set (reg h-gr 31) (add pc 8))
+		   (delay 1 (set pc offset))))
+     ())
+
+(dni bgezall
+     "branch if greater than equal to zero and link likely" (USES-RS USES-R31)
+     "bgezall $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGEZALL offset)
+     (if (ge rs 0)
+	 (sequence ()
+		   (set (reg h-gr 31) (add pc 8))
+		   (delay 1 (set pc offset)))
+	 (skip 1))
+     ())
+
+(dni bgezl "branch if greater or equal to zero likely" (USES-RS)
+     "bgezl $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BGEZL offset)
+     (if (ge rs 0)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+(dni bltz "branch if less than zero" (USES-RS)
+     "bltz $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLTZ offset)
+     (if (lt rs 0)
+	 (delay 1 (set pc offset)))
+     ())
+
+(dni bltzl "branch if less than zero likely" (USES-RS)
+     "bltzl $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLTZL offset)
+     (if (lt rs 0)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+(dni bltzal "branch if less than zero and link" (USES-RS USES-R31)
+     "bltzal $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLTZAL offset)
+     (if (lt rs 0)
+	 (sequence ()
+		   (set (reg h-gr 31) (add pc 8))
+		   (delay 1 (set pc offset))))
+     ())
+
+(dni bltzall "branch if less than zero and link likely" (USES-RS USES-R31)
+     "bltzall $rs,$offset"
+     (+ OP_REGIMM rs FUNC_BLTZALL offset)
+     (if (lt rs 0)
+	 (sequence ()
+		   (set (reg h-gr 31) (add pc 8))
+		   (delay 1 (set pc offset)))
+	 (skip 1))
+     ())
+
+(dni bmb0 "branch if matching byte-lane 0" (USES-RS USES-RT)
+     "bmb0 $rs,$rt,$offset"
+     (+ OP_BMB0 rs rt offset)
+     (if (eq (and rs #xFF) (and rt #xFF))
+	 (delay 1 (set pc offset)))
+     ())
+
+(dni bmb1 "branch if matching byte-lane 1" (USES-RS USES-RT)
+     "bmb1 $rs,$rt,$offset"
+     (+ OP_BMB1 rs rt offset)
+     (if (eq (and rs #xFF00) (and rt #xFF00))
+	 (delay 1 (set pc offset)))
+     ())
+
+(dni bmb2 "branch if matching byte-lane 2" (USES-RS USES-RT)
+     "bmb2 $rs,$rt,$offset"
+     (+ OP_BMB2 rs rt offset)
+     (if (eq (and rs #xFF0000) (and rt #xFF0000))
+	 (delay 1 (set pc offset)))
+     ())
+
+(dni bmb3 "branch if matching byte-lane 3" (USES-RS USES-RT)
+     "bmb3 $rs,$rt,$offset"
+     (+ OP_BMB3 rs rt offset)
+     (if (eq (and rs #xFF000000) (and rt #xFF000000))
+	 (delay 1 (set pc offset)))
+     ())
+
+(dni bne "branch if not equal" (USES-RS USES-RT)
+     "bne $rs,$rt,$offset"
+     (+ OP_BNE rs rt offset)
+     (if (ne rs rt)
+	 (delay 1 (set pc offset)))
+     ())
+
+(dni bnel "branch if not equal likely" (USES-RS USES-RT)
+     "bnel $rs,$rt,$offset"
+     (+ OP_BNEL rs rt offset)
+     (if (ne rs rt)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+
+
+
+; Jump instructions.
+; Might as well jump!
+
+(dni jalr "jump and link register" (USES-RD USES-RS)
+     "jalr $rd,$rs"
+     (+ OP_SPECIAL rs (f-rt 0) rd (f-shamt 0) FUNC_JALR)
+     (delay 1
+	    (sequence ()
+		      (set rd (add pc 8))
+		      (set pc rs)))
+     ())
+
+(dni jr "jump register" (USES-RS)
+     "jr $rs"
+     (+ OP_SPECIAL rs (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_JR)
+     (delay 1 (set pc rs))
+     ())
+
+
+; Load instructions.
+
+(dni lb "load byte" (LOAD-DELAY USES-RS USES-RT)
+     "lb $rt,$lo16($base)"
+     (+ OP_LB base rt lo16)
+     (set rt (ext WI (mem QI (add base (ext SI (trunc HI lo16))))))
+;     (sequence ((SI addr) (SI word))
+;	       (set addr (add base lo16))
+;	       (set word (mem SI (and addr (inv 3))))
+;	       (set word (srl word (sll (and addr 2) 3)))
+;	       (set rt (ext SI word)))
+     ())
+
+(dni lbu "load byte unsigned" (LOAD-DELAY USES-RS USES-RT)
+     "lbu $rt,$lo16($base)"
+     (+ OP_LBU base rt lo16)
+     (set rt (zext WI (mem QI (add base (ext SI (trunc HI lo16))))))
+;     (sequence ((SI addr) (SI word))
+;	       (set addr (add base lo16))
+;	       (set word (mem SI (and addr (inv 3))))
+;	       (set rt (srl word (sll (and addr 2) 3))))
+     ())
+
+(dni lh "load half word" (LOAD-DELAY USES-RS USES-RT)
+     "lh $rt,$lo16($base)"
+     (+ OP_LH base rt lo16)
+     (set rt (ext WI (mem HI (add base (ext SI (trunc HI lo16))))))
+;     (sequence ((SI addr) (HI word))
+;	       (set addr (add base lo16))
+;	       (set word (mem SI (and addr (inv 3))))
+;	       (set word (srl word (sll (and addr 1) 4)))
+;	       (set rt (ext SI word)))
+     ())
+
+(dni lhu "load half word unsigned" (LOAD-DELAY USES-RS USES-RT)
+     "lhu $rt,$lo16($base)"
+     (+ OP_LHU base rt lo16)
+     (set rt (zext WI (mem HI (add base (ext SI (trunc HI lo16))))))
+;     (sequence ((SI addr) (SI word))
+;	       (set addr (add base lo16))
+;	       (set word (mem SI (and addr (inv 3))))
+;	       (set rt (srl word (sll (and addr 1) 4))))
+     ())
+
+(dni lui "load upper immediate" (USES-RT)
+     "lui $rt,$hi16"
+     (+ OP_LUI (f-rs 0) rt hi16)
+     (set rt (sll hi16 16))
+     ())
+
+(dni lw "load word" (LOAD-DELAY USES-RS USES-RT)
+    "lw $rt,$lo16($base)"
+    (+ OP_LW base rt lo16)
+    (set rt (mem SI (add base (ext SI (trunc HI lo16)))))
+    ())
+
+
+; Store instructions.
+
+(dni sb "store byte" (USES-RS USES-RT)
+     "sb $rt,$lo16($base)"
+     (+ OP_SB base rt lo16)
+     (set (mem QI (add base (ext SI (trunc HI lo16)))) (and QI rt #xFF))
+     ())
+
+(dni sh "store half word" (USES-RS USES-RT)
+     "sh $rt,$lo16($base)"
+     (+ OP_SH base rt lo16)
+     (set (mem HI (add base (ext SI (trunc HI lo16)))) (and HI rt #xFFFF))
+     ())
+
+(dni sw "store word" (USES-RS USES-RT)
+     "sw $rt,$lo16($base)"
+     (+ OP_SW base rt lo16)
+     (set (mem SI (add base (ext SI (trunc HI lo16)))) rt)
+     ())
+
+
+; Special instructions for simulation/debugging
+(dni break "breakpoint" ()
+     "break"
+     (+ OP_SPECIAL (f-rs 0) (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_BREAK)
+     (c-call VOID "do_break" pc)
+     ())
+
+(dni syscall "system call" (YIELD-INSN)
+     "syscall"
+     (+ OP_SPECIAL execode (f-func 12))
+     (c-call VOID "do_syscall")
+     ())
+
+; Macro instructions, common to iq10 & iq2000
+
+(dnmi nop "nop" ()
+      "nop"
+      (emit sll (rd 0) (rt 0) (shamt 0))
+)
+
+(dnmi li "load immediate" (USES-RS NO-DIS)
+      "li $rs,$imm"
+      (emit ori (rt 0) rs imm)
+)
+
+(dnmi move "move" (USES-RD USES-RT NO-DIS)
+      "move $rd,$rt"
+      (emit or rd (rs 0) rt)
+)
+
+(dnmi lb-base-0 "load byte - implied base 0" (USES-RT NO-DIS)
+      "lb $rt,$lo16"
+      (emit lb rt lo16 (base 0))
+)
+
+(dnmi lbu-base-0 "load byte unsigned - implied base 0" (USES-RT NO-DIS)
+      "lbu $rt,$lo16"
+      (emit lbu rt lo16 (base 0))
+)
+
+(dnmi lh-base-0 "load half - implied base 0" (USES-RT NO-DIS)
+      "lh $rt,$lo16"
+      (emit lh rt lo16 (base 0))
+)
+
+(dnmi lw-base-0 "load word - implied base 0" (USES-RT NO-DIS)
+      "lw $rt,$lo16"
+      (emit lw rt lo16 (base 0))
+)
+
+(dnmi m-add "add immediate" (USES-RS USES-RT NO-DIS)
+      "add $rt,$rs,$lo16"
+      (emit addi rt rs lo16))
+
+(dnmi m-addu "add immediate unsigned" (USES-RS USES-RT NO-DIS)
+      "addu $rt,$rs,$lo16"
+      (emit addiu rt rs lo16)
+)
+
+(dnmi m-and "and immediate" (USES-RS USES-RT NO-DIS)
+      "and $rt,$rs,$lo16"
+      (emit andi rt rs lo16)
+)
+
+(dnmi m-j "jump register" (USES-RS NO-DIS)
+      "j $rs"
+      (emit jr rs)
+)
+
+(dnmi m-or "or immediate" (USES-RS USES-RT NO-DIS)
+      "or $rt,$rs,$lo16"
+      (emit ori rt rs lo16)
+)
+
+(dnmi m-sll "shift left logical" (USES-RD USES-RT USES-RS NO-DIS)
+      "sll $rd,$rt,$rs"
+      (emit sllv rd rt rs)
+)
+
+(dnmi m-slt "slt immediate" (USES-RS USES-RT NO-DIS)
+      "slt $rt,$rs,$imm"
+      (emit slti rt rs imm)
+)
+
+(dnmi m-sltu "sltu immediate" (USES-RS USES-RT NO-DIS)
+      "sltu $rt,$rs,$imm"
+      (emit sltiu rt rs imm)
+)
+
+(dnmi m-sra "shift right arithmetic" (USES-RD USES-RT USES-RS NO-DIS)
+      "sra $rd,$rt,$rs"
+      (emit srav rd rt rs)
+)
+
+(dnmi m-srl "shift right logical" (USES-RD USES-RT USES-RS NO-DIS)
+      "srl $rd,$rt,$rs"
+      (emit srlv rd rt rs)
+)
+
+(dnmi not "not" (USES-RD USES-RT NO-DIS)
+      "not $rd,$rt"
+      (emit nor rd (rs 0) rt)
+)
+
+(dnmi subi "sub immediate" (USES-RS USES-RT NO-DIS)
+      "subi $rt,$rs,$mlo16"
+      (emit addiu rt rs mlo16)
+)      
+
+(dnmi m-sub "subtract immediate" (USES-RS USES-RT NO-DIS)
+      "sub $rt,$rs,$mlo16"
+      (emit addiu rt rs mlo16)
+)
+
+(dnmi m-subu "subtract unsigned" (USES-RS USES-RT NO-DIS)
+      "subu $rt,$rs,$mlo16"
+      (emit addiu rt rs mlo16)
+)
+
+(dnmi sb-base-0 "store byte - implied base 0" (USES-RT NO-DIS)
+      "sb $rt,$lo16"
+      (emit sb rt lo16 (base 0))
+)
+
+(dnmi sh-base-0 "store half - implied base 0" (USES-RT NO-DIS)
+      "sh $rt,$lo16"
+      (emit sh rt lo16 (base 0))
+)
+
+(dnmi sw-base-0 "store word - implied base 0" (USES-RT NO-DIS)
+      "sw $rt,$lo16"
+      (emit sw rt lo16 (base 0))
+)
+
+(dnmi m-xor "xor immediate" (USES-RS USES-RT NO-DIS)
+      "xor $rt,$rs,$lo16"
+      (emit xori rt rs lo16)
+)
+
+
+(if (keep-mach? (iq2000))
+(include "iq2000m.cpu"))
+
+(if (keep-mach? (iq10))
+(include "iq10.cpu"))
+
+
+
Index: iq2000.opc
===================================================================
RCS file: iq2000.opc
diff -N iq2000.opc
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ iq2000.opc	3 Jun 2003 18:39:08 -0000
@@ -0,0 +1,324 @@
+/* IQ2000 opcode support.  -*- C -*-
+
+   Copyright 2000, 2001, 2002 Free Software Foundation, Inc.
+
+   Contributed by Red Hat Inc; developed under contract from Fujitsu.
+
+   This file is part of the GNU Binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+/* This file is an addendum to iq2000.cpu.  Heavy use of C code isn't
+   appropriate in .cpu files, so it resides here.  This especially applies
+   to assembly/disassembly where parsing/printing can be quite involved.
+   Such things aren't really part of the specification of the cpu, per se,
+   so .cpu files provide the general framework and .opc files handle the
+   nitty-gritty details as necessary.
+
+   Each section is delimited with start and end markers.
+
+   <arch>-opc.h additions use: "-- opc.h"
+   <arch>-opc.c additions use: "-- opc.c"
+   <arch>-asm.c additions use: "-- asm.c"
+   <arch>-dis.c additions use: "-- dis.c"
+   <arch>-ibd.h additions use: "-- ibd.h"
+*/
+
+/* -- opc.h */
+
+/* Allows reason codes to be output when assembler errors occur.  */
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+/* Override disassembly hashing - there are variable bits in the top
+   byte of these instructions.  */
+#define CGEN_DIS_HASH_SIZE 8
+#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE)
+
+/* following activates check beyond hashing since some iq2000 and iq10
+   instructions have same mnemonics but different functionality. */
+#define CGEN_VALIDATE_INSN_SUPPORTED
+
+extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, CGEN_INSN *insn);
+
+/* -- asm.c */
+static const char * parse_mimm PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
+static const char * parse_imm  PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
+static const char * parse_lo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
+
+/* Special check to ensure that instruction exists for given machine */
+int
+iq2000_cgen_insn_supported (cd, insn)
+     CGEN_CPU_DESC cd;
+     CGEN_INSN *insn;
+{
+  int machs = cd->machs;
+
+  return ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0);
+}
+
+static int iq2000_cgen_isa_register (strp)
+     const char **strp;
+{
+  int len;
+  int ch1, ch2;
+  if (**strp == 'r' || **strp == 'R') 
+    {
+      len = strlen (*strp);
+      if (len == 2) 
+        {
+          ch1 = (*strp)[1];
+          if ('0' <= ch1 && ch1 <= '9')
+            return 1;
+        } 
+      else if (len == 3) 
+        {
+	  ch1 = (*strp)[1];
+          ch2 = (*strp)[2];
+          if (('1' <= ch1 && ch1 <= '2') && ('0' <= ch2 && ch2 <= '9'))
+            return 1;
+          if ('3' == ch1 && (ch2 == '0' || ch2 == '1'))
+            return 1;
+        }
+    }
+  if (**strp == '%' && tolower((*strp)[1]) != 'l' && tolower((*strp)[1]) != 'h')
+    return 1;
+  return 0;
+}
+
+/* Handle negated literal.  */
+
+static const char *
+parse_mimm (cd, strp, opindex, valuep)
+     CGEN_CPU_DESC cd;
+     const char **strp;
+     int opindex;
+     long *valuep;
+{
+  const char *errmsg;
+  long value;
+
+  /* Verify this isn't a register */
+  if (iq2000_cgen_isa_register (strp))
+    errmsg = _("immediate value cannot be register");
+  else
+    {
+      long value;
+      
+      errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+      if (errmsg == NULL)
+	{
+	  long x = (-value) & 0xFFFF0000;
+	  if (x != 0 && x != 0xFFFF0000)
+	    errmsg = _("immediate value out of range");
+	  else
+	    *valuep = (-value & 0xFFFF);
+	}
+    }
+  return errmsg;
+}
+
+/* Handle signed/unsigned literal.  */
+
+static const char *
+parse_imm (cd, strp, opindex, valuep)
+     CGEN_CPU_DESC cd;
+     const char **strp;
+     int opindex;
+     unsigned long *valuep;
+{
+  const char *errmsg;
+  long value;
+
+  if (iq2000_cgen_isa_register (strp))
+    errmsg = _("immediate value cannot be register");
+  else
+    {
+      long value;
+
+      errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
+      if (errmsg == NULL)
+	{
+	  long x = value & 0xFFFF0000;
+	  if (x != 0 && x != 0xFFFF0000)
+	    errmsg = _("immediate value out of range");
+	  else
+	    *valuep = (value & 0xFFFF);
+	}
+    }
+  return errmsg;
+}
+
+/* Handle iq10 21-bit jmp offset.  */
+
+static const char *
+parse_jtargq10 (cd, strp, opindex, reloc, type_addr, valuep)
+     CGEN_CPU_DESC cd;
+     const char **strp;
+     int opindex;
+     int reloc;
+     enum cgen_parse_operand_result *type_addr;
+     unsigned long *valuep;
+{
+  const char *errmsg;
+  bfd_vma value;
+  enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER;
+
+  errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_OFFSET_21,
+			       &result_type, &value);
+  if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+    {
+      /* check value is within 23-bits (remembering that 2-bit shift right will occur) */
+      if (value > 0x7fffff)
+        return _("21-bit offset out of range");
+    }
+  *valuep = (value & 0x7FFFFF);
+  return errmsg;
+}
+
+/* Handle high().  */
+
+static const char *
+parse_hi16 (cd, strp, opindex, valuep)
+     CGEN_CPU_DESC cd;
+     const char **strp;
+     int opindex;
+     unsigned long *valuep;
+{
+  if (strncasecmp (*strp, "%hi(", 4) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 4;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
+				   &result_type, &value);
+      if (**strp != ')')
+	return _("missing `)'");
+
+      ++*strp;
+      if (errmsg == NULL
+  	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	{
+	  /* if value has top-bit of %lo on, then it will
+	     sign-propagate and so we compensate by adding
+	     1 to the resultant %hi value */
+	  if (value & 0x8000)
+	    value += 0x10000;
+	  value >>= 16;
+	}
+      *valuep = value;
+
+      return errmsg;
+    }
+
+  /* we add %uhi in case a user just wants the high 16-bits or is using
+     an insn like ori for %lo which does not sign-propagate */
+  if (strncasecmp (*strp, "%uhi(", 5) == 0)
+    {
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+      const char *errmsg;
+
+      *strp += 5;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_UHI16,
+				   &result_type, &value);
+      if (**strp != ')')
+	return _("missing `)'");
+
+      ++*strp;
+      if (errmsg == NULL
+  	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	{
+	  value >>= 16;
+	}
+      *valuep = value;
+
+      return errmsg;
+    }
+
+  return parse_imm (cd, strp, opindex, valuep);
+}
+
+/* Handle %lo in a signed context.
+   The signedness of the value doesn't matter to %lo(), but this also
+   handles the case where %lo() isn't present.  */
+
+static const char *
+parse_lo16 (cd, strp, opindex, valuep)
+     CGEN_CPU_DESC cd;
+     const char **strp;
+     int opindex;
+     long *valuep;
+{
+  if (strncasecmp (*strp, "%lo(", 4) == 0)
+    {
+      const char *errmsg;
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+
+      *strp += 4;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
+				   &result_type, &value);
+      if (**strp != ')')
+	return _("missing `)'");
+      ++*strp;
+      if (errmsg == NULL
+	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	value &= 0xffff;
+      *valuep = value;
+      return errmsg;
+    }
+
+  return parse_imm (cd, strp, opindex, valuep);
+}
+
+/* Handle %lo in a negated signed context.
+   The signedness of the value doesn't matter to %lo(), but this also
+   handles the case where %lo() isn't present.  */
+
+static const char *
+parse_mlo16 (cd, strp, opindex, valuep)
+     CGEN_CPU_DESC cd;
+     const char **strp;
+     int opindex;
+     long *valuep;
+{
+  if (strncasecmp (*strp, "%lo(", 4) == 0)
+    {
+      const char *errmsg;
+      enum cgen_parse_operand_result result_type;
+      bfd_vma value;
+
+      *strp += 4;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
+				   &result_type, &value);
+      if (**strp != ')')
+	return _("missing `)'");
+      ++*strp;
+      if (errmsg == NULL
+	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	value = (-value) & 0xffff;
+      *valuep = value;
+      return errmsg;
+    }
+
+  return parse_mimm (cd, strp, opindex, valuep);
+}
+
+/* -- */
Index: iq2000m.cpu
===================================================================
RCS file: iq2000m.cpu
diff -N iq2000m.cpu
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ iq2000m.cpu	3 Jun 2003 18:39:09 -0000
@@ -0,0 +1,630 @@
+; IQ2000-only CPU description. -*- Scheme -*-
+;
+; Copyright 2000, 2001, 2002 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc; developed under contract from Vitesse.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 2 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+(dni andoui "and upper ones immediate" (MACH2000 USES-RS USES-RT)
+     "andoui $rt,$rs,$hi16"
+     (+ OP_ANDOUI rs rt hi16)
+     (set rt (and rs (or (sll hi16 16) #xFFFF)))
+     ())
+
+(dni andoui2 "and upper ones immediate" (ALIAS NO-DIS MACH2000 USES-RS USES-RT)
+     "andoui ${rt-rs},$hi16"
+     (+ OP_ANDOUI rt-rs hi16)
+     (set rt-rs (and rt-rs (or (sll hi16 16) #xFFFF)))
+     ())
+
+(dni orui2 "or upper immediate" (ALIAS NO-DIS MACH2000 USES-RS USES-RT)
+     "orui ${rt-rs},$hi16"
+     (+ OP_ORUI rt-rs hi16)
+     (set rt-rs (or rt-rs (sll hi16 16)))
+     ())
+
+(dni orui "or upper immediate" (MACH2000 USES-RS USES-RT)
+     "orui $rt,$rs,$hi16"
+     (+ OP_ORUI rs rt hi16)
+     (set rt (or rs (sll hi16 16)))
+     ())
+
+(dni bgtz "branch if greater than zero" (MACH2000 USES-RS)
+     "bgtz $rs,$offset"
+     (+ OP_BGTZ rs (f-rt 0) offset)
+     (if (gt rs 0)
+	 (delay 1 (set pc offset)))
+     ())
+
+
+(dni bgtzl "branch if greater than zero likely" (MACH2000 USES-RS)
+     "bgtzl $rs,$offset"
+     (+ OP_BGTZL rs (f-rt 0) offset)
+     (if (gt rs 0)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+(dni blez "branch if less than or equal to zero" (MACH2000 USES-RS)
+     "blez $rs,$offset"
+     (+ OP_BLEZ rs (f-rt 0) offset)
+     (if (le rs 0)
+	 (delay 1 (set pc offset)))
+     ())
+
+(dni blezl "branch if less than or equal to zero likely" (MACH2000 USES-RS)
+     "blezl $rs,$offset"
+     (+ OP_BLEZL rs (f-rt 0) offset)
+     (if (le rs 0)
+	 (delay 1 (set pc offset))
+	 (skip 1))
+     ())
+
+
+(dni mrgb "merge bytes" (MACH2000 USES-RD USES-RS USES-RT)
+     "mrgb $rd,$rs,$rt,$mask"
+     (+ OP_SPECIAL rs rt rd (f-10 0) mask FUNC_MRGB)
+     (sequence ((SI temp))
+	       (if (bitclear? mask 0)
+		   (set temp (and rs #xFF))
+		   (set temp (and rt #xFF)))
+	       (if (bitclear? mask 1)
+		   (set temp (or temp (and rs #xFF00)))
+		   (set temp (or temp (and rt #xFF00))))
+	       (if (bitclear? mask 2)
+		   (set temp (or temp (and rs #xFF0000)))
+		   (set temp (or temp (and rt #xFF0000))))
+	       (if (bitclear? mask 3)
+		   (set temp (or temp (and rs #xFF000000)))
+		   (set temp (or temp (and rt #xFF000000))))
+	       (set rd temp))
+     ())
+
+(dni mrgb2 "merge bytes" (ALIAS NO-DIS MACH2000 USES-RD USES-RS USES-RT)
+     "mrgb ${rd-rs},$rt,$mask"
+     (+ OP_SPECIAL rt rd-rs (f-10 0) mask FUNC_MRGB)
+     (sequence ((SI temp))
+	       (if (bitclear? mask 0)
+		   (set temp (and rd-rs #xFF))
+		   (set temp (and rt #xFF)))
+	       (if (bitclear? mask 1)
+		   (set temp (or temp (and rd-rs #xFF00)))
+		   (set temp (or temp (and rt #xFF00))))
+	       (if (bitclear? mask 2)
+		   (set temp (or temp (and rd-rs #xFF0000)))
+		   (set temp (or temp (and rt #xFF0000))))
+	       (if (bitclear? mask 3)
+		   (set temp (or temp (and rd-rs #xFF000000)))
+		   (set temp (or temp (and rt #xFF000000))))
+	       (set rd-rs temp))
+     ())
+
+; NOTE: None of these instructions' semantics are specified, so they
+; will not work in a simulator.
+;
+; Architectural and coprocessor instructions.
+; BREAK and SYSCALL are implemented with escape hatches to the C
+; code.  These are used by the test suite to indicate pass/failures.
+
+(dni bctxt "branch and switch context" (MACH2000 DELAY-SLOT COND-CTI USES-RS)
+     "bctxt $rs,$offset"
+     (+ OP_REGIMM rs (f-rt 6) offset)
+     (unimp bctxt)
+     ())
+
+(dni bc0f "branch if copro 0 condition false" (MACH2000 DELAY-SLOT COND-CTI)
+     "bc0f $offset"
+     (+ OP_COP0 (f-rs 8) (f-rt 0) offset)
+     (unimp bc0f)
+     ())
+
+(dni bc0fl "branch if copro 0 condition false likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
+     "bc0fl $offset"
+     (+ OP_COP0 (f-rs 8) (f-rt 2) offset)
+     (unimp bc0fl)
+     ())
+
+(dni bc3f "branch if copro 3 condition false" (MACH2000 DELAY-SLOT COND-CTI)
+     "bc3f $offset"
+     (+ OP_COP3 (f-rs 8) (f-rt 0) offset)
+     (unimp bc3f)
+     ())
+
+(dni bc3fl "branch if copro 3 condition false likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
+     "bc3fl $offset"
+     (+ OP_COP3 (f-rs 8) (f-rt 2) offset)
+     (unimp bc3fl)
+     ())
+
+(dni bc0t "branch if copro 0 condition true" (MACH2000 DELAY-SLOT COND-CTI)
+     "bc0t $offset"
+     (+ OP_COP0 (f-rs 8) (f-rt 1) offset)
+     (unimp bc0t)
+     ())
+
+(dni bc0tl "branch if copro 0 condition true likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
+     "bc0tl $offset"
+     (+ OP_COP0 (f-rs 8) (f-rt 3) offset)
+     (unimp bc0tl)
+     ())
+
+(dni bc3t "branch if copro 3 condition true" (MACH2000 DELAY-SLOT COND-CTI)
+     "bc3t $offset"
+     (+ OP_COP3 (f-rs 8) (f-rt 1) offset)
+     (unimp bc3t)
+     ())
+
+(dni bc3tl "branch if copro 3 condition true likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
+     "bc3tl $offset"
+     (+ OP_COP3 (f-rs 8) (f-rt 3) offset)
+     (unimp bc3tl)
+     ())
+
+; Note that we don't set the USES-RD or USES-RT attributes for many of the following 
+; instructions, as it's the COP register that's being specified.
+
+(dni cfc0 "control from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT)
+     "cfc0 $rt,$rd"
+     (+ OP_COP0 (f-rs 2) rt rd (f-10-11 0))
+     (unimp cfc0)
+     ())
+
+(dni cfc1 "control from coprocessor 1" (MACH2000 LOAD-DELAY USES-RT)
+     "cfc1 $rt,$rd"
+     (+ OP_COP1 (f-rs 2) rt rd (f-10-11 0))
+     (unimp cfc1)
+     ())
+
+(dni cfc2 "control from coprocessor 2" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
+     "cfc2 $rt,$rd"
+     (+ OP_COP2 (f-rs 2) rt rd (f-10-11 0))
+     (unimp cfc2)
+     ())
+
+(dni cfc3 "control from coprocessor 3" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
+     "cfc3 $rt,$rd"
+     (+ OP_COP3 (f-rs 2) rt rd (f-10-11 0))
+     (unimp cfc3)
+     ())
+
+; COPz instructions are an instruction form, not real instructions
+; with associated assembly mnemonics.  Therefore, they are omitted
+; from the ISA description.
+
+(dni chkhdr "check header" (MACH2000 LOAD-DELAY USES-RD YIELD-INSN)
+     "chkhdr $rd,$rt"
+     (+ OP_COP3 (f-rs 9) rt rd (f-shamt 0) (f-func 0))
+     (unimp chkhdr)
+     ())
+
+(dni ctc0 "control to coprocessor 0" (MACH2000 USES-RT)
+     "ctc0 $rt,$rd"
+     (+ OP_COP0 (f-rs 6) rt rd (f-10-11 0))
+     (unimp ctc0)
+     ())
+
+(dni ctc1 "control to coprocessor 1" (MACH2000 USES-RT)
+     "ctc1 $rt,$rd"
+     (+ OP_COP1 (f-rs 6) rt rd (f-10-11 0))
+     (unimp ctc1)
+     ())
+
+(dni ctc2 "control to coprocessor 2" (MACH2000 USES-RT)
+     "ctc2 $rt,$rd"
+     (+ OP_COP2 (f-rs 6) rt rd (f-10-11 0))
+     (unimp ctc2)
+     ())
+
+(dni ctc3 "control to coprocessor 3" (MACH2000 USES-RT)
+     "ctc3 $rt,$rd"
+     (+ OP_COP3 (f-rs 6) rt rd (f-10-11 0))
+     (unimp ctc3)
+     ())
+
+(dni jcr "jump context register" (MACH2000 DELAY-SLOT UNCOND-CTI USES-RS)
+     "jcr $rs"
+     (+ OP_SPECIAL rs (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_JCR)
+     (unimp jcr)
+     ())
+
+(dni luc32 "lookup chain 32 bits" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "luc32 $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 3))
+     (unimp luc32)
+     ())
+
+(dni luc32l "lookup chain 32 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "luc32l $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 7))
+     (unimp luc32l)
+     ())
+
+(dni luc64 "lookup chain 64 bits" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "luc64 $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 11))
+     (unimp luc64)
+     ())
+
+(dni luc64l "lookup chain 64 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "luc64l $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 15))
+     (unimp luc64l)
+     ())
+
+(dni luk "lookup key" (MACH2000 USES-RD USES-RT)
+     "luk $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 8))
+     (unimp luk)
+     ())
+
+(dni lulck "lookup lock" (MACH2000 USES-RT YIELD-INSN)
+     "lulck $rt"
+     (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 4))
+     (unimp lulck)
+     ())
+
+(dni lum32 "lookup match 32 bits" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "lum32 $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 2))
+     (unimp lum32)
+     ())
+
+(dni lum32l "lookup match 32 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "lum32l $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 6))
+     (unimp lum32l)
+     ())
+
+(dni lum64 "lookup match 64 bits" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "lum64 $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 10))
+     (unimp lum64)
+     ())
+
+(dni lum64l "lookup match 64 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "lum64l $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 14))
+     (unimp lum64l)
+     ())
+
+(dni lur "lookup read" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "lur $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 1))
+     (unimp lur)
+     ())
+
+(dni lurl "lookup read and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "lurl $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 5))
+     (unimp lurl)
+     ())
+
+(dni luulck "lookup unlock" (MACH2000 USES-RT YIELD-INSN)
+     "luulck $rt"
+     (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 0))
+     (unimp luulck)
+     ())
+
+(dni mfc0 "move from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT)
+     "mfc0 $rt,$rd"
+     (+ OP_COP0 (f-rs 0) rt rd (f-10-11 0))
+     (unimp mfc0)
+     ())
+
+(dni mfc1 "move from coprocessor 1" (MACH2000 LOAD-DELAY USES-RT)
+     "mfc1 $rt,$rd"
+     (+ OP_COP1 (f-rs 0) rt rd (f-10-11 0))
+     (unimp mfc1)
+     ())
+
+(dni mfc2 "move from coprocessor 2" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
+     "mfc2 $rt,$rd"
+     (+ OP_COP2 (f-rs 0) rt rd (f-10-11 0))
+     (unimp mfc2)
+     ())
+
+(dni mfc3 "move from coprocessor 3" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
+     "mfc3 $rt,$rd"
+     (+ OP_COP3 (f-rs 0) rt rd (f-10-11 0))
+     (unimp mfc3)
+     ())
+
+(dni mtc0 "move to coprocessor 0" (MACH2000 USES-RT)
+     "mtc0 $rt,$rd"
+     (+ OP_COP0 (f-rs 4) rt rd (f-10-11 0))
+     (unimp mtc0)
+     ())
+
+(dni mtc1 "move to coprocessor 1" (MACH2000 USES-RT)
+     "mtc1 $rt,$rd"
+     (+ OP_COP1 (f-rs 4) rt rd (f-10-11 0))
+     (unimp mtc1)
+     ())
+
+(dni mtc2 "move to coprocessor 2" (MACH2000 USES-RT)
+     "mtc2 $rt,$rd"
+     (+ OP_COP2 (f-rs 4) rt rd (f-10-11 0))
+     (unimp mtc2)
+     ())
+
+(dni mtc3 "move to coprocessor 3" (MACH2000 USES-RT)
+     "mtc3 $rt,$rd"
+     (+ OP_COP3 (f-rs 4) rt rd (f-10-11 0))
+     (unimp mtc3)
+     ())
+
+(dni pkrl "pkrl" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "pkrl $rd,$rt"
+     (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 7))
+     (unimp pkrl)
+     ())
+
+(dni pkrlr1 "pkrlr1" (MACH2000 USES-RT YIELD-INSN)
+     "pkrlr1 $rt,$count"
+     (+ OP_COP3 (f-rs 29) rt count)
+     (unimp pkrlr1)
+     ())
+
+(dni pkrlr30 "pkrlr30" (MACH2000 USES-RT YIELD-INSN)
+     "pkrlr30 $rt,$count"
+     (+ OP_COP3 (f-rs 31) rt count)
+     (unimp pkrlr30)
+     ())
+
+(dni rb "dma read bytes" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "rb $rd,$rt"
+     (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 4))
+     (unimp rb)
+     ())
+
+(dni rbr1 "dma read bytes using r1" (MACH2000 USES-RT YIELD-INSN)
+     "rbr1 $rt,$count"
+     (+ OP_COP3 (f-rs 24) rt count)
+     (unimp rbr1)
+     ())
+
+(dni rbr30 "dma read bytes using r30" (MACH2000 USES-RT YIELD-INSN)
+     "rbr30 $rt,$count"
+     (+ OP_COP3 (f-rs 26) rt count)
+     (unimp rbr30)
+     ())
+
+(dni rfe "restore from exception" (MACH2000)
+     "rfe"
+     (+ OP_COP0 (f-25 1) (f-24-19 0) (f-func 16))
+     (unimp rfe)
+     ())
+
+(dni rx "dma read word64s" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "rx $rd,$rt"
+     (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 6))
+     (unimp rx)
+     ())
+
+(dni rxr1 "dma read word64s using r1" (MACH2000 USES-RT YIELD-INSN)
+     "rxr1 $rt,$count"
+     (+ OP_COP3 (f-rs 28) rt count)
+     (unimp rxr1)
+     ())
+
+(dni rxr30 "dma read word 64s using r30" (MACH2000 USES-RT YIELD-INSN)
+     "rxr30 $rt,$count"
+     (+ OP_COP3 (f-rs 30) rt count)
+     (unimp rxr30)
+     ())
+
+(dni sleep "sleep" (MACH2000 YIELD-INSN)
+     "sleep"
+     (+ OP_SPECIAL execode FUNC_SLEEP)
+     (unimp sleep)
+     ())
+
+(dni srrd "sram read" (MACH2000 USES-RT YIELD-INSN)
+     "srrd $rt"
+     (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 16))
+     (unimp srrd)
+     ())
+
+(dni srrdl "sram read and lock" (MACH2000 USES-RT YIELD-INSN)
+     "srrdl $rt"
+     (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 20))
+     (unimp srrdl)
+     ())
+
+(dni srulck "sram unlock" (MACH2000 USES-RT YIELD-INSN)
+     "srulck $rt"
+     (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 22))
+     (unimp srulck)
+     ())
+
+(dni srwr "sram write" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "srwr $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 17))
+     (unimp srwr)
+     ())
+
+(dni srwru "sram write and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "srwru $rt,$rd"
+     (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 21))
+     (unimp srwru)
+     ())
+
+(dni trapqfl "yield if dma queue full" (MACH2000 YIELD-INSN)
+     "trapqfl"
+     (+ OP_COP3 (f-rs 1) (f-rt 0) (f-rd 0) (f-shamt 0) (f-func 8))
+     (unimp trapqfl)
+     ())
+
+(dni trapqne "yield if dma queue not empty" (MACH2000 YIELD-INSN)
+     "trapqne"
+     (+ OP_COP3 (f-rs 1) (f-rt 0) (f-rd 0) (f-shamt 0) (f-func 9))
+     (unimp trapqne)
+     ())
+
+(dni traprel "traprel" (MACH2000 USES-RT YIELD-INSN)
+     "traprel $rt"
+     (+ OP_COP3 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 10))
+     (unimp traprel)
+     ())
+
+(dni wb "dma write bytes" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "wb $rd,$rt"
+     (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 0))
+     (unimp wb)
+     ())
+
+(dni wbu "dma write bytes and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "wbu $rd,$rt"
+     (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 1))
+     (unimp wbu)
+     ())
+
+(dni wbr1 "dma write bytes using r1" (MACH2000 USES-RT YIELD-INSN)
+     "wbr1 $rt,$count"
+     (+ OP_COP3 (f-rs 16) rt count)
+     (unimp wbr1)
+     ())
+
+(dni wbr1u "dma write bytes using r1 and unlock" (MACH2000 USES-RT YIELD-INSN)
+     "wbr1u $rt,$count"
+     (+ OP_COP3 (f-rs 17) rt count)
+     (unimp wbr1u)
+     ())
+
+(dni wbr30 "dma write bytes using r30" (MACH2000 USES-RT YIELD-INSN)
+     "wbr30 $rt,$count"
+     (+ OP_COP3 (f-rs 18) rt count)
+     (unimp wbr30)
+     ())
+
+(dni wbr30u "dma write bytes using r30 and unlock" (MACH2000 USES-RT YIELD-INSN)
+     "wbr30u $rt,$count"
+     (+ OP_COP3 (f-rs 19) rt count)
+     (unimp wbr30u)
+     ())
+
+(dni wx "dma write word64s" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "wx $rd,$rt"
+     (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 2))
+     (unimp wx)
+     ())
+
+(dni wxu "dma write word64s and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN)
+     "wxu $rd,$rt"
+     (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 3))
+     (unimp wxu)
+     ())
+
+(dni wxr1 "dma write word64s using r1" (MACH2000 USES-RT YIELD-INSN)
+     "wxr1 $rt,$count"
+     (+ OP_COP3 (f-rs 20) rt count)
+     (unimp wxr1)
+     ())
+
+(dni wxr1u "dma write word64s using r1 and unlock" (MACH2000 USES-RT YIELD-INSN)
+     "wxr1u $rt,$count"
+     (+ OP_COP3 (f-rs 21) rt count)
+     (unimp wxr1u)
+     ())
+
+(dni wxr30 "dma write word64s using r30" (MACH2000 USES-RT YIELD-INSN)
+     "wxr30 $rt,$count"
+     (+ OP_COP3 (f-rs 22) rt count)
+     (unimp wxr30)
+     ())
+
+(dni wxr30u "dma write word64s using r30 and unlock" (MACH2000 USES-RT YIELD-INSN)
+     "wxr30u $rt,$count"
+     (+ OP_COP3 (f-rs 23) rt count)
+     (unimp wxr30u)
+     ())
+
+
+; Load/Store instructions.
+
+(dni ldw "load double word" (MACH2000 EVEN-REG-NUM LOAD-DELAY USES-RT)
+     "ldw $rt,$lo16($base)"
+     (+ OP_LDW base rt lo16)
+     (sequence ((SI addr))
+	       (set addr (and (add base lo16) (inv 3)))
+	       (set (reg h-gr (add (ifield f-rt) 1)) (mem SI addr))
+	       (set rt (mem SI (add addr 4))))
+     ())
+
+(dni sdw "store double word" (MACH2000 EVEN-REG-NUM USES-RT)
+     "sdw $rt,$lo16($base)"
+     (+ OP_SDW base rt lo16)
+     (sequence ((SI addr))
+	       (set addr (and (add base lo16) (inv 3)))
+	       (set (mem SI (add addr 4)) rt)
+	       (set (mem SI addr) (reg h-gr (add (ifield f-rt) 1))))
+     ())
+
+
+; Jump instructions
+
+(dni j "jump" (MACH2000)
+     "j $jmptarg"
+     (+ OP_J (f-rsrvd 0) jmptarg)
+     (delay 1 (set pc jmptarg))
+     ())
+
+(dni jal "jump and link" (MACH2000 USES-R31)
+     "jal $jmptarg"
+     (+ OP_JAL (f-rsrvd 0) jmptarg)
+     (delay 1
+	    (sequence ()
+		      (set (reg h-gr 31) (add pc 8))
+		      (set pc jmptarg)))
+     ())
+
+(dni bmb "branch if matching byte-lane" (MACH2000 USES-RS USES-RT)
+     "bmb $rs,$rt,$offset"
+     (+ OP_BMB rs rt offset)
+     (sequence ((BI branch?))
+	       (set branch? 0)
+	       (if (eq (and rs #xFF) (and rt #xFF))
+		   (set branch? 1))
+	       (if (eq (and rs #xFF00) (and rt #xFF00))
+		   (set branch? 1))
+	       (if (eq (and rs #xFF0000) (and rt #xFF0000))
+		   (set branch? 1))
+	       (if (eq (and rs #xFF000000) (and rt #xFF000000))
+		   (set branch? 1))
+	       (if branch?
+		   (delay 1 (set pc offset))))
+     ())
+
+
+; Macros
+
+(dnmi ldw-base-0 "load double word - implied base 0" (MACH2000 EVEN-REG-NUM LOAD-DELAY USES-RT USES-RS NO-DIS)
+      "ldw $rt,$lo16"
+      (emit ldw rt lo16 (base 0))
+)
+
+(dnmi sdw-base-0 "store double word - implied base 0" (MACH2000 EVEN-REG-NUM USES-RT NO-DIS)
+      "sdw $rt,$lo16"
+      (emit sdw rt lo16 (base 0))
+)
+
+
+
+
+
+

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