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[Patch] i860 pseudo-insn defect (committed)
- From: Jason Eckhardt <jle at owlnet dot rice dot edu>
- To: <binutils at sources dot redhat dot com>
- Date: Sun, 17 Aug 2003 13:35:23 -0500 (CDT)
- Subject: [Patch] i860 pseudo-insn defect (committed)
We were using the wrong opcodes for the [p]fmov.{ds,sd}
pseudo-instructions, resulting in difficult-to-isolate
runtime errors in some floating-point codes. The fix and
a new testcase for it have been applied.
include/opcode/ChangeLog:
2003-08-16 Jason Eckhardt <jle@rice.edu>
* i860.h (fmov.ds): Expand as famov.ds.
(fmov.sd): Expand as famov.sd.
(pfmov.ds): Expand as pfamov.ds.
gas/testsuite/ChangeLog:
2003-08-16 Jason Eckhardt <jle@rice.edu>
* gas/i860/pseudo-ops01.{s,d}: New files.
* gas/i860/i860.exp: Execute the new test above.
* gas/i860/README.i860: Mention that pseudo-ops need more testing
and remove the align fill defect from the list.
Index: gas/testsuite/gas/i860/README.i860
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/i860/README.i860,v
retrieving revision 1.4
diff -c -3 -p -r1.4 README.i860
*** gas/testsuite/gas/i860/README.i860 6 Aug 2003 19:53:19 -0000 1.4
--- gas/testsuite/gas/i860/README.i860 17 Aug 2003 03:07:03 -0000
*************** way GAS/i860 is tested against a known g
*** 19,33 ****
TODO:
- Relocation testing is basically non-existent.
- pst.d (pixel store) is the only instruction with no testcase.
- More tests for dual instruction mode: check that dual mode has a
proper pair (FLOP/core) of instructions, and other error conditions.
- Most current testcases use the default AT&T/SVR4 syntax; a few simple
tests of the Intel syntax should be added to prevent bitrot (including
relocatable expression syntax, etc). Test file dual03.s uses Intel
syntax lightly (i.e., register names without '%' prefix).
- - Currently, .align in a .text section fills with 0x00000000. This is
- a defect and it needs to fill with nop (0xa0000000). Write a testcase
- for it.
Contact me (Jason Eckhardt, jle@rice.edu) if you'd like to help.
--- 19,31 ----
TODO:
- Relocation testing is basically non-existent.
- pst.d (pixel store) is the only instruction with no testcase.
+ - Some pseudo instructions need testcases (mov, all pfmov, etc.).
- More tests for dual instruction mode: check that dual mode has a
proper pair (FLOP/core) of instructions, and other error conditions.
- Most current testcases use the default AT&T/SVR4 syntax; a few simple
tests of the Intel syntax should be added to prevent bitrot (including
relocatable expression syntax, etc). Test file dual03.s uses Intel
syntax lightly (i.e., register names without '%' prefix).
Contact me (Jason Eckhardt, jle@rice.edu) if you'd like to help.
Index: gas/testsuite/gas/i860/i860.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/i860/i860.exp,v
retrieving revision 1.5
diff -c -3 -p -r1.5 i860.exp
*** gas/testsuite/gas/i860/i860.exp 6 Aug 2003 23:59:36 -0000 1.5
--- gas/testsuite/gas/i860/i860.exp 17 Aug 2003 03:07:04 -0000
*************** if [istarget i860-*-*] {
*** 48,53 ****
--- 48,54 ----
run_dump_test "pfmam"
run_dump_test "pfmsm"
run_dump_test "pfsm"
+ run_dump_test "pseudo-ops01"
run_dump_test "regress01"
run_dump_test "shift"
run_dump_test "simd"
Index: gas/testsuite/gas/i860/pseudo-ops01.d
===================================================================
RCS file: gas/testsuite/gas/i860/pseudo-ops01.d
diff -N gas/testsuite/gas/i860/pseudo-ops01.d
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/i860/pseudo-ops01.d 17 Aug 2003 03:07:04 -0000
***************
*** 0 ****
--- 1,14 ----
+ #as:
+ #objdump: -d
+ #name: i860 pseudo-ops01
+
+ .*: +file format .*
+
+ Disassembly of section \.text:
+
+ 00000000 <\.text>:
+ 0: 49 28 06 48 fiadd\.ss %f5,%f0,%f6
+ 4: c9 41 0a 48 fiadd\.dd %f8,%f0,%f10
+ 8: b3 18 14 48 famov\.sd %f3,%f20
+ c: 33 c1 09 48 famov\.ds %f24,%f9
+ 10: 33 e5 03 48 pfamov\.ds %f28,%f3
Index: gas/testsuite/gas/i860/pseudo-ops01.s
===================================================================
RCS file: gas/testsuite/gas/i860/pseudo-ops01.s
diff -N gas/testsuite/gas/i860/pseudo-ops01.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/i860/pseudo-ops01.s 17 Aug 2003 03:07:04 -0000
***************
*** 0 ****
--- 1,10 ----
+ # Test some assembler pseudo-operations:
+ # Floating point moves.
+
+ .text
+ fmov.ss %f5,%f6
+ fmov.dd %f8,%f10
+ fmov.sd %f3,%f20
+ fmov.ds %f24,%f9
+ pfmov.ds %f28,%f3
+
Index: include/opcode/i860.h
===================================================================
RCS file: /cvs/src/src/include/opcode/i860.h,v
retrieving revision 1.9
diff -c -3 -p -r1.9 i860.h
*** include/opcode/i860.h 24 May 2003 04:22:23 -0000 1.9
--- include/opcode/i860.h 17 Aug 2003 03:07:18 -0000
*************** static const struct i860_opcode i860_opc
*** 494,502 ****
/* Floating point pseudo-instructions. */
{ "fmov.ss", 0x48000049, 0xb7e005b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */
{ "fmov.dd", 0x480001c9, 0xb7e00436, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */
! { "fmov.sd", 0x480000b0, 0xb7e0054f, "e,g", 0 }, /* fadd.sd fsrc1,f0,fdest */
! { "fmov.ds", 0x48000130, 0xb7e004cf, "e,g", 0 }, /* fadd.ds fsrc1,f0,fdest */
! { "pfmov.ds", 0x48000530, 0xb73000cf, "e,g", 0 }, /* pfadd.ds fsrc1,f0,fdest */
{ "pfmov.dd", 0x480005c9, 0xb7e00036, "e,g", 0 }, /* pfiadd.dd fsrc1,f0,fdest */
{ 0, 0, 0, 0, 0 },
--- 494,502 ----
/* Floating point pseudo-instructions. */
{ "fmov.ss", 0x48000049, 0xb7e005b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */
{ "fmov.dd", 0x480001c9, 0xb7e00436, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */
! { "fmov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.sd fsrc1,fdest */
! { "fmov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.ds fsrc1,fdest */
! { "pfmov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.ds fsrc1,fdest */
{ "pfmov.dd", 0x480005c9, 0xb7e00036, "e,g", 0 }, /* pfiadd.dd fsrc1,f0,fdest */
{ 0, 0, 0, 0, 0 },