Re: how to calculate opcode mask

[Shinpei Kato <shinny at j02 dot itscom dot net>]

>The mask follows from the definition of the instruction.  Any
>instruction has some fixed bits which define the instruction.  Most
>but not all instructions have some variable bits which are register
>numbers, immediate values, etc.  The mask is simply the fixed bits
>which define the instruction.
>
>I can translate d,v,t into a mask by looking at the definitions in
>include/opcode/mips.h, and doing
>    ~ ((OP_MASK_RD << OP_SH_RD)
>       | (OP_MASK_RS << OP_SH_RS)
>       | (OP_MASK_RT << OP_SH_RT))
>As I said, though, that approach doesn't always work for all
>instructions.

I've just got it how to use OP_MASK_XX and OP_SH_XX :-)
However, now things got clearer than before for me.
I'm trying.

>> And could I ask one more question?
>> There are several shift counters for registers such as OP_SH_FT,
>> OP_SH_FS, etc. Maybe these are used to set up a next register number, I
>> suppose. 
>
>Those are shift counts for fields within an instruction.

I see. It means I seldom have to change those values.

>Hmmm.  To change the number of registers you need to define new fields
>within the instruction, and you need to write new code to set those
>fields.  Note that you are asking about MIPS, and the MIPS chip
>already has 32 floating point registers.

Yes, you're right. Simply speaking, the CPU arch is not MIPS but very 
similar to MIPS. One of differences is the number of floating point
registers. 
And I've been taking one mistake. GAS doesn't allocate the register
number but GCC does. It's to be expected... I was confusing, sorry.
Now I modified GCC to allocate the only 8 floating-point registers.
I guess(wish) it's working as I expect.

Thanks,
Shinpei Kato.