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Re: [arm] Fix maverick load/store offsets
- From: Richard Earnshaw <Richard dot Earnshaw at arm dot com>
- To: Paul Brook <paul at codesourcery dot com>
- Cc: binutils at sources dot redhat dot com
- Date: Wed, 21 Apr 2004 11:05:25 +0100
- Subject: Re: [arm] Fix maverick load/store offsets
- References: <200404202031.32474.paul@codesourcery.com>
On Tue, 2004-04-20 at 20:31, Paul Brook wrote:
> Arm coprocessor load/store insns (including maverick crunch) use an 8-bit word
> offset. This allows -1020 <= offset <= 1020 where offset % 4 == 0.
>
> We were limiting offsets to +-255, and silently corrupting non-multiple of 4
> offsets.
>
> The patch below fixes this, and updates the testsuite accordingly. The current
> version of maverick.c in the testsuite seems to generate a broken tests for
> other insns, so I fixed that too.
>
> Tested with cross to arm-none-elf.
> Ok?
>
> Paul
>
> 2004-04-20 Paul Brook <paul@codesourcery.com>
>
> * config/tc-arm.c (mav_parse_offset): Value must be multiple of 4.
> testsuite
> * maverick.c (off8s): Test full shifted operand range.
> (MCC2): Define.
> (MVDSPACC, MVACCDSP): Use it.
> * maverick.d, maverick.s: Regenerate.
OK.
R.