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Re: [PATCH] Handle mtsprg and mfsprg properly for BookE
- From: Jeff Baker <jbaker at qnx dot com>
- To: Alan Modra <amodra at bigpond dot net dot au>
- Cc: binutils at sourceware dot org
- Date: Wed, 09 Mar 2005 11:41:01 -0500
- Subject: Re: [PATCH] Handle mtsprg and mfsprg properly for BookE
- Organization: QNX Software Systems Ltd.
- References: <20050309021118.GJ15642@bubble.modra.org>
- Reply-to: jbaker at qnx dot com
Here is the patch as you suggested. Let me know if you consider the
testsuite additions insufficient.
2005-03-09 Jeff Baker <jbaker@qnx.com>
* ppc-opc.c (SPRG_MASK): Allow 3 bits for register.
(powerpc_operands): Likewise.
(insert_sprg): New Function.
Index: ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.78
diff -w -u -p -r1.78 ppc-opc.c
--- ppc-opc.c 20 Jan 2005 06:54:48 -0000 1.78
+++ ppc-opc.c 9 Mar 2005 16:23:09 -0000
@@ -84,6 +84,7 @@ static unsigned long insert_sh6 (unsigne
static long extract_sh6 (unsigned long, int, int *);
static unsigned long insert_spr (unsigned long, long, int, const char **);
static long extract_spr (unsigned long, int, int *);
+static unsigned long insert_sprg (unsigned long, long, int, const char **);
static unsigned long insert_tbr (unsigned long, long, int, const char **);
static long extract_tbr (unsigned long, int, int *);
static unsigned long insert_ev2 (unsigned long, long, int, const char **);
@@ -465,8 +466,8 @@ const struct powerpc_operand powerpc_ope
/* The SPRG register number in an XFX form m[ft]sprg instruction. */
#define SPRG SPRBAT + 1
-#define SPRG_MASK (0x3 << 16)
- { 2, 16, NULL, NULL, 0 },
+#define SPRG_MASK (0x7 << 16)
+ { 3, 16, insert_sprg, NULL, 0 },
/* The SR field in an X form instruction. */
#define SR SPRG + 1
@@ -1397,6 +1398,30 @@ extract_spr (unsigned long insn,
return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
}
+/* Some dialects have 8 SPRG registers instead of the standard 4.*/
+
+static unsigned long
+insert_sprg (unsigned long insn,
+ long value,
+ int dialect,
+ const char **errmsg)
+{
+ /* This check uses PPC_OPCODE_403 because PPC405 is later defined
+ as a synonym. If ever a 405 specific dialect is added this
+ check should use that instead. */
+ if (value > 7
+ || (value > 3
+ && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
+ *errmsg = _("invalid sprg number");
+
+ insn |= (value & 7) << 16;
+ /* Clear the sprn5 bit if the sprgN in question should be read in
+ user mode. */
+ if (value > 3)
+ insn &= (insn >> 8) & 1 ? ~0 : ~( 1 << 20 );
+ return insn;
+}
+
/* The TBR field in an XFX instruction. This is just like SPR, but it
is optional. When TBR is omitted, it must be inserted as 268 (the
magic number of the TB register). These functions treat 0
2005-03-09 Jeff Baker <jbaker@qnx.com>
* gas/ppc/booke.s: Add new m[t,f]sprg testcases.
* gas/ppc/booke.d: Likewise.
Index: gas/ppc/booke.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/booke.d,v
retrieving revision 1.9
diff -w -u -p -r1.9 booke.d
--- gas/ppc/booke.d 2 Mar 2005 13:25:01 -0000 1.9
+++ gas/ppc/booke.d 9 Mar 2005 16:24:05 -0000
@@ -142,3 +142,11 @@ Disassembly of section \.text:
1c0: 7c 00 06 ac mbar
1c4: 7c 00 06 ac mbar
1c8: 7c 20 06 ac mbar 1
+ 1cc: 7c 12 42 a6 mfsprg r0,2
+ 1d0: 7c 12 42 a6 mfsprg r0,2
+ 1d4: 7c 12 43 a6 mtsprg 2,r0
+ 1d8: 7c 12 43 a6 mtsprg 2,r0
+ 1dc: 7c 07 42 a6 mfsprg7 r0
+ 1e0: 7c 07 42 a6 mfsprg7 r0
+ 1e4: 7c 17 43 a6 mtsprg 7,r0
+ 1e8: 7c 17 43 a6 mtsprg 7,r0
Index: gas/ppc/booke.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/booke.s,v
retrieving revision 1.3
diff -w -u -p -r1.3 booke.s
--- gas/ppc/booke.s 10 Dec 2003 22:12:50 -0000 1.3
+++ gas/ppc/booke.s 9 Mar 2005 16:24:05 -0000
@@ -1,5 +1,5 @@
# Motorola PowerPC BookE tests
-#as: -mbooke32
+#as: -mbooke64
.section ".text"
start:
bce 1, 5, branch_target_1
@@ -134,3 +134,12 @@ branch_target_8:
mbar
mbar 0
mbar 1
+
+ mfsprg 0, 2
+ mfsprg2 0
+ mtsprg 2, 0
+ mtsprg2 0
+ mfsprg 0, 7
+ mfsprg7 0
+ mtsprg 7, 0
+ mtsprg7 0
Alan Modra wrote:
On Tue, Mar 08, 2005 at 08:20:21PM -0500, Jeff Baker wrote:
Would it be correct to change the generic PPC_OPCODE_BOOKE case to
always use user mode sprg2+ and then override it to be sprg3+ for
PPC_OPCODE_403 and PPC_OPCODE_440? Should there be a version of
mtsprg3
for e500 and MPC8560 that encodes 259 instead of 275?
That's what _you_ need to research. If you can decide on the correct
mapping of sprg number to spr number for a given processor, and defend
your mapping against potential criticism, I'm more than happy to help
correct an implementation.
Hmm, looking over your patch again, I suppose you could simply say that
your mapping of sprg number to spr number matches the existing gas
opcodes. ie. "mfsprg 0,4" generates the same as "mfsprg4 0" and so on.
Enumerate all the possibilities in an addition to the testsuite, and
you've made that obvious. If you fix the formatting, correct the error
messages, and extend the testsuite this way I'll accept the patch. I'll
also still be worried that gas isn't generating the right opcodes, but
I suppose that's another issue..