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Thumb32 assembler (67/69)
- From: Zack Weinberg <zack at codesourcery dot com>
- To: binutils <binutils at sourceware dot org>
- Date: Tue, 26 Apr 2005 02:43:47 -0700
- Subject: Thumb32 assembler (67/69)
Here's something I should have done a long, long time ago in this
series: convert all the "gas_test" tests in testsuite/gas/arm to
"run_dump_test" tests, so that we are actually verifying that GAS
produces the correct machine language for these instructions. As you
can see, this change flushed out a fair number of bugs.
gas:
* config/tc-arm.c (arm_reg_parse): Accept MMXWCG registers
wherever MMXWC registers are accepted.
(parse_operands): Likewise.
(do_fpa_ldmstm): Correct bit-bashing.
(do_iwmmxt_wldst): Rename do_iwmmxt_wldstbh. Scale offset by 4.
(do_iwmmxt_wldstd): New function.
(insns): Correct opcode for Thumb cmp. Correct operand order for
tbcstb, tbcsth, tbcstw, textrmub, textrmuh, textrmuw, textrmsb,
textrmuh, textrmuw. Use do_iwmmxt_wldstbh for wldrb, wldrh,
wstrb, wstrh; do_iwmmxt_wldstd for wldrd, wstrd.
gas/testsuite:
* gas/arm/arm.exp: Replace all "gas_test" tests with
"run_dump_test" tests. Run iwmmxt and iwmmxt-bad on all
subarchitectures.
* gas/arm/arch4t.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/offset.d, gas/arm/thumb.d: New files.
* gas/arm/arch4t.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/offset.s: Make safe for dump test.
* gas/arm/iwmmxt.s: Make safe for a.out target.
* gas/arm/iwmmxt-bad.l, gas/arm/iwmmxt.d: Update patterns.
===================================================================
Index: gas/config/tc-arm.c
--- gas/config/tc-arm.c (revision 77)
+++ gas/config/tc-arm.c (revision 78)
@@ -855,6 +855,12 @@
if (*ccp != start && processor <= 15)
return processor;
}
+
+ case REG_TYPE_MMXWC:
+ /* WC includes WCG. ??? I'm not sure this is true for all
+ instructions that take WC registers. */
+ if (reg->type == REG_TYPE_MMXWCG)
+ return reg->number;
break;
default:
@@ -3698,7 +3704,9 @@
case OP_RIWR_RIWC:
{
struct reg_entry *rege = arm_reg_parse_multi (&str);
- if (rege->type != REG_TYPE_MMXWR && rege->type != REG_TYPE_MMXWC)
+ if (rege->type != REG_TYPE_MMXWR
+ && rege->type != REG_TYPE_MMXWC
+ && rege->type != REG_TYPE_MMXWCG)
{
inst.error = _("iWMMXt data or control register expected");
goto failure;
@@ -5186,20 +5194,21 @@
constraint (inst.reloc.exp.X_op != O_constant
|| inst.reloc.exp.X_add_number != 0,
_("this instruction does not support indexing"));
- if (inst.operands[2].writeback)
- inst.instruction |= WRITE_BACK;
- if (inst.instruction & (PRE_INDEX | WRITE_BACK))
+
+ if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
- else
- inst.instruction |= PRE_INDEX; /* prevent use of unindexed mode */
-
+
if (!(inst.instruction & INDEX_UP))
inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
- inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
+ if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
+ {
+ inst.operands[2].preind = 0;
+ inst.operands[2].postind = 1;
+ }
}
- else
- encode_arm_cp_address (2, TRUE, TRUE, 0);
+
+ encode_arm_cp_address (2, TRUE, TRUE, 0);
}
/* iWMMXt instructions: strictly in alphabetical order. */
@@ -5260,9 +5269,10 @@
}
static void
-do_iwmmxt_wldst (void)
+do_iwmmxt_wldstbh (void)
{
inst.instruction |= inst.operands[0].reg << 12;
+ inst.reloc.exp.X_add_number *= 4;
encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_CP_OFF_IMM_S2);
}
@@ -5281,6 +5291,13 @@
}
static void
+do_iwmmxt_wldstd (void)
+{
+ inst.instruction |= inst.operands[0].reg << 12;
+ encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_CP_OFF_IMM_S2);
+}
+
+static void
do_iwmmxt_wshufh (void)
{
inst.instruction |= inst.operands[0].reg << 12;
@@ -6450,7 +6467,7 @@
CE(teq, 1300000, 2, (RR, SH), cmp),
CM(teq,s, 1300000, 2, (RR, SH), cmp),
CM(teq,p, 130f000, 2, (RR, SH), cmp),
- TCE(cmp, 1500000, 4280, 2, (RR, SH), cmp, t_mov_cmp),
+ TCE(cmp, 1500000, 4500, 2, (RR, SH), cmp, t_mov_cmp),
CM(cmp,s, 1500000, 2, (RR, SH), cmp),
CM(cmp,p, 150f000, 2, (RR, SH), cmp),
TCE(cmn, 1700000, 42c0, 2, (RR, SH), cmp, t_arit),
@@ -7373,18 +7390,18 @@
CE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
CE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
CE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
- CE(tbcstb, e400010, 2, (RR, RIWR), rd_rn),
- CE(tbcsth, e400050, 2, (RR, RIWR), rd_rn),
- CE(tbcstw, e400090, 2, (RR, RIWR), rd_rn),
+ CE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
+ CE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
+ CE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
CE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
CE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
CE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
- CE(textrmub, e100070, 3, (RIWR, RR, I7), iwmmxt_textrm),
- CE(textrmuh, e500070, 3, (RIWR, RR, I7), iwmmxt_textrm),
- CE(textrmuw, e900070, 3, (RIWR, RR, I7), iwmmxt_textrm),
- CE(textrmsb, e100078, 3, (RIWR, RR, I7), iwmmxt_textrm),
- CE(textrmsh, e500078, 3, (RIWR, RR, I7), iwmmxt_textrm),
- CE(textrmsw, e900078, 3, (RIWR, RR, I7), iwmmxt_textrm),
+ CE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
+ CE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
+ CE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
+ CE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
+ CE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
+ CE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
CE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
CE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
CE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
@@ -7436,10 +7453,10 @@
CE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
CE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
CE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldst),
- CE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldst),
+ CE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
+ CE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
CE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
- CE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldst),
+ CE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
CE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
CE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
CE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
@@ -7499,10 +7516,10 @@
CE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
CE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
CE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
- CE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldst),
- CE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldst),
+ CE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
+ CE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
CE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
- CE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldst),
+ CE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
CE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
CE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
CE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
===================================================================
Index: gas/testsuite/gas/arm/arm3.d
--- gas/testsuite/gas/arm/arm3.d (revision 0)
+++ gas/testsuite/gas/arm/arm3.d (revision 78)
@@ -0,0 +1,11 @@
+# name: ARM 3 instructions
+# as: -mcpu=arm3
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+0 <[^>]*> e1080091 ? swp r0, r1, \[r8\]
+0+4 <[^>]*> e1432093 ? swpb r2, r3, \[r3\]
+0+8 <[^>]*> a1444091 ? swpgeb r4, r1, \[r4\]
+0+c <[^>]*> e1a00000 ? nop \(mov r0,r0\)
===================================================================
Index: gas/testsuite/gas/arm/bignum1.d
--- gas/testsuite/gas/arm/bignum1.d (revision 0)
+++ gas/testsuite/gas/arm/bignum1.d (revision 78)
@@ -0,0 +1,8 @@
+# name: bignums
+# as:
+# objdump: --full-contents
+
+.*: +file format .*arm.*
+
+Contents of section .data:
+ 0000 [08]0000000 000000[08]0 11111111 11111111 \.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.
===================================================================
Index: gas/testsuite/gas/arm/iwmmxt-bad.l
--- gas/testsuite/gas/arm/iwmmxt-bad.l (revision 77)
+++ gas/testsuite/gas/arm/iwmmxt-bad.l (revision 78)
@@ -1,9 +1,9 @@
[^:]*: Assembler messages:
-[^:]*:1: Error: conditional execution not supported with control register
-[^:]*:2: Error: non-word size not supported with control register
-[^:]*:3: Error: non-word size not supported with control register
-[^:]*:4: Error: non-word size not supported with control register
-[^:]*:5: Error: conditional execution not supported with control register
-[^:]*:6: Error: non-word size not supported with control register
-[^:]*:7: Error: non-word size not supported with control register
-[^:]*:8: Error: non-word size not supported with control register
+[^:]*:1: Error: instruction cannot be conditional -- `wldrwgt wcgr0,\[r1\]'
+[^:]*:2: Error: iWMMXt data register expected -- `wldrb wcgr0,\[r1\]'
+[^:]*:3: Error: iWMMXt data register expected -- `wldrh wcgr0,\[r1\]'
+[^:]*:4: Error: iWMMXt data register expected -- `wldrd wcgr0,\[r1\]'
+[^:]*:5: Error: instruction cannot be conditional -- `wstrwgt wcgr0,\[r1\]'
+[^:]*:6: Error: iWMMXt data register expected -- `wstrb wcgr0,\[r1\]'
+[^:]*:7: Error: iWMMXt data register expected -- `wstrh wcgr0,\[r1\]'
+[^:]*:8: Error: iWMMXt data register expected -- `wstrd wcgr0,\[r1\]'
===================================================================
Index: gas/testsuite/gas/arm/arm3.s
--- gas/testsuite/gas/arm/arm3.s (revision 77)
+++ gas/testsuite/gas/arm/arm3.s (revision 78)
@@ -1,6 +1,7 @@
-.text
-.align 0
+ .text
+ .align 0
+l:
swp r0, r1, [r8]
swpb r2, r3, [r3]
swpgeb r4, r1, [r4]
-
+ nop
===================================================================
Index: gas/testsuite/gas/arm/bignum1.s
--- gas/testsuite/gas/arm/bignum1.s (revision 77)
+++ gas/testsuite/gas/arm/bignum1.s (revision 78)
@@ -1 +1,3 @@
+ .data
.8byte -9223372036854775808
+ .8byte 1229782938247303441
===================================================================
Index: gas/testsuite/gas/arm/offset.d
--- gas/testsuite/gas/arm/offset.d (revision 0)
+++ gas/testsuite/gas/arm/offset.d (revision 78)
@@ -0,0 +1,11 @@
+# name: OFFSET_IMM regression
+# as:
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+0 <[^>]+> e51f0004 ? ldr r0, \[pc, #-4\] ; 0+4 <[^>]+>
+0+4 <[^>]+> e1a00000 ? nop \(mov r0,r0\)
+0+8 <[^>]+> e1a00000 ? nop \(mov r0,r0\)
+0+c <[^>]+> e1a00000 ? nop \(mov r0,r0\)
===================================================================
Index: gas/testsuite/gas/arm/immed.d
--- gas/testsuite/gas/arm/immed.d (revision 0)
+++ gas/testsuite/gas/arm/immed.d (revision 78)
@@ -0,0 +1,16 @@
+# name: immediate expressions
+# as:
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+0000 <[^>]+> e3a00000 ? mov r0, #0 ; 0x0
+0+0004 <[^>]+> e3e00003 ? mvn r0, #3 ; 0x3
+0+0008 <[^>]+> e51f0010 ? ldr r0, \[pc, #-16\] ; 0+0 <[^>]+>
+0+000c <[^>]+> e51f0014 ? ldr r0, \[pc, #-20\] ; 0+0 <[^>]+>
+ \.\.\.
+0+1010 <[^>]+> e3a00008 ? mov r0, #8 ; 0x8
+0+1014 <[^>]+> e59f00e4 ? ldr r0, \[pc, #228\] ; 0+1100 <[^>]+>
+0+1018 <[^>]+> e1a00000 ? nop \(mov r0,r0\)
+0+101c <[^>]+> e1a00000 ? nop \(mov r0,r0\)
===================================================================
Index: gas/testsuite/gas/arm/offset.s
--- gas/testsuite/gas/arm/offset.s (revision 77)
+++ gas/testsuite/gas/arm/offset.s (revision 78)
@@ -1,5 +1,14 @@
-@ test for OFFSET_IMM reloc against global symbols
+ @ test that an OFFSET_IMM reloc against a global symbol is
+ @ still resolved by the assembler, as long as the symbol is in
+ @ the same section as the reference
+ .text
+ .globl l
+ .globl foo
+l:
+ ldr r0, foo
+foo:
+ nop
-.globl foo
-foo: .word 0
-ldr r0, foo
+ @ pad section for a.out's benefit
+ nop
+ nop
===================================================================
Index: gas/testsuite/gas/arm/immed.s
--- gas/testsuite/gas/arm/immed.s (revision 77)
+++ gas/testsuite/gas/arm/immed.s (revision 78)
@@ -9,3 +9,7 @@
.space 4096
mov r0, #(. - bar - 8) & 0xff
ldr r0, [pc, # (bar - . -8) & 0xff]
+
+ @ section padding for a.out's benefit
+ nop
+ nop
===================================================================
Index: gas/testsuite/gas/arm/iwmmxt.d
--- gas/testsuite/gas/arm/iwmmxt.d (revision 77)
+++ gas/testsuite/gas/arm/iwmmxt.d (revision 78)
@@ -166,3 +166,6 @@
0+278 <[^>]*> 0e9540ea[ ]+wunpckilweq[ ]+wr4, wr5, wr10
0+27c <[^>]*> 1e143005[ ]+wxorne[ ]+wr3, wr4, wr5
0+280 <[^>]*> ae377007[ ]+wandnge[ ]+wr7, wr7, wr7
+0+284 <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\)
+0+288 <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\)
+0+28c <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\)
===================================================================
Index: gas/testsuite/gas/arm/arm.exp
--- gas/testsuite/gas/arm/arm.exp (revision 77)
+++ gas/testsuite/gas/arm/arm.exp (revision 78)
@@ -28,14 +28,13 @@
run_dump_test "copro"
}
- gas_test "arm3.s" "-mcpu=arm3" $stdoptlist "Arm 3 instructions"
- gas_test "arm6.s" "-mcpu=arm6" $stdoptlist "Arm 6 instructions"
- gas_test "arm7dm.s" "-mcpu=arm7dm" $stdoptlist "Arm 7DM instructions"
- gas_test "arch4t.s" "-march=armv4t" $stdoptlist "Arm architecture 4t instructions"
- gas_test "immed.s" "" $stdoptlist "immediate expressions"
- gas_test "float.s" "-mcpu=arm7tdmi -mfpu=fpa" $stdoptlist "Core floating point instructions"
- gas_test "offset.s" "" $stdoptlist "OFFSET_IMM regression"
-
+ run_dump_test "arm3"
+ run_dump_test "arm6"
+ run_dump_test "arm7dm"
+ run_dump_test "arch4t"
+ run_dump_test "immed"
+ run_dump_test "float"
+ run_dump_test "offset"
run_dump_test "armv1"
run_dump_test "arch5tej"
run_dump_test "fpa-monadic"
@@ -54,6 +53,7 @@
run_dump_test "thumbv6k"
run_dump_test "arch6zk"
run_dump_test "tcompat"
+ run_dump_test "iwmmxt"
run_errors_test "vfp-bad" "-mfpu=vfp" "VFP errors"
run_errors_test "req" "-mcpu=arm7m" ".req errors"
@@ -61,6 +61,7 @@
run_errors_test "r15-bad" "" "Invalid use of r15 errors"
run_errors_test "archv6t2-bad" "-march=armv6t2" "Invalid V6T2 instructions"
run_errors_test "t16-bad" "-march=armv6k" "Valid ARM, invalid Thumb"
+ run_errors_test "iwmmxt-bad" "-mcpu=iwmmxt" "iWMMXt errors"
if {[istarget *-*-*coff] || [istarget *-*-pe] || [istarget *-*-wince] ||
[istarget *-*-*aout*] || [istarget *-*-netbsd] || [istarget *-*-riscix*]} then {
@@ -72,29 +73,19 @@
run_dump_test "pic"
run_dump_test "mapping"
- gas_test "bignum1.s" "" $stdoptlist "bignums"
+ run_dump_test "bignum1"
run_dump_test "unwind"
-
run_dump_test "tls"
}
+ # The arm-aout port does not support Thumb branch relocations.
if {! [istarget arm*-*-aout] && ![istarget arm-*-pe]} then {
- # The arm-aout port does not support Thumb mode.
- gas_test "thumb.s" "-mcpu=arm7t" $stdoptlist "Thumb instructions"
+ run_dump_test "thumb"
}
-}
-# Not all arm targets are bi-endian, so only run this test on ones
-# we know that are. FIXME: We should probably also key off armeb/armel.
-
-if [istarget arm-*-pe] {
- run_dump_test "le-fpconst"
-
- # Since big-endian numbers have the normal format, this doesn't exist.
- #run_dump_test "be-fpconst"
+ # Not all arm targets are bi-endian, so only run this test on ones
+ # we know that are. FIXME: We should probably also key off armeb/armel.
+ if [istarget *-*-pe] {
+ run_dump_test "le-fpconst"
+ }
}
-
-if [istarget xscale-*] {
- run_dump_test "iwmmxt"
- run_errors_test "iwmmxt-bad" "-mcpu=iwmmxt" "iWMMXt errors"
-}
===================================================================
Index: gas/testsuite/gas/arm/iwmmxt.s
--- gas/testsuite/gas/arm/iwmmxt.s (revision 77)
+++ gas/testsuite/gas/arm/iwmmxt.s (revision 78)
@@ -202,3 +202,8 @@
wxorne wr3, wr4, wr5
wzeroge wr7
+
+ @ a.out-required section size padding
+ nop
+ nop
+ nop
===================================================================
Index: gas/testsuite/gas/arm/float.d
--- gas/testsuite/gas/arm/float.d (revision 0)
+++ gas/testsuite/gas/arm/float.d (revision 78)
@@ -0,0 +1,131 @@
+# name: Core floating point instructions
+# as: -mcpu=arm7tdmi -mfpu=fpa
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]+> ee088101 ? mvfe f0, f1
+0+004 <[^>]+> 0e08b105 ? mvfeqe f3, f5
+0+008 <[^>]+> 0e00c189 ? mvfeqd f4, #1\.0
+0+00c <[^>]+> ee00c107 ? mvfs f4, f7
+0+010 <[^>]+> ee008121 ? mvfsp f0, f1
+0+014 <[^>]+> ee00b1c4 ? mvfdm f3, f4
+0+018 <[^>]+> ee08f167 ? mvfez f7, f7
+0+01c <[^>]+> ee09010a ? adfe f0, f1, #2\.0
+0+020 <[^>]+> 0e0a110e ? adfeqe f1, f2, #0\.5
+0+024 <[^>]+> ee043145 ? adfsm f3, f4, f5
+0+028 <[^>]+> ee20018a ? sufd f0, f0, #2\.0
+0+02c <[^>]+> ee22110f ? sufs f1, f2, #10\.0
+0+030 <[^>]+> 1e2c3165 ? sufneez f3, f4, f5
+0+034 <[^>]+> ee311108 ? rsfs f1, f1, #0\.0
+0+038 <[^>]+> ee3031ad ? rsfdp f3, f0, #5\.0
+0+03c <[^>]+> de367180 ? rsfled f7, f6, f0
+0+040 <[^>]+> ee100180 ? mufd f0, f0, f0
+0+044 <[^>]+> ee1a116b ? mufez f1, f2, #3\.0
+0+048 <[^>]+> ee10010c ? mufs f0, f0, #4\.0
+0+04c <[^>]+> ee400189 ? dvfd f0, f0, #1\.0
+0+050 <[^>]+> ee49016f ? dvfez f0, f1, #10\.0
+0+054 <[^>]+> 4e443145 ? dvfmism f3, f4, f5
+0+058 <[^>]+> ee59010f ? rdfe f0, f1, #10\.0
+0+05c <[^>]+> ee573109 ? rdfs f3, f7, #1\.0
+0+060 <[^>]+> 3e5441a3 ? rdfccdp f4, f4, f3
+0+064 <[^>]+> ee620183 ? powd f0, f2, f3
+0+068 <[^>]+> ee63110f ? pows f1, f3, #10\.0
+0+06c <[^>]+> 2e6f4169 ? powcsez f4, f7, #1\.0
+0+070 <[^>]+> ee767107 ? rpws f7, f6, f7
+0+074 <[^>]+> 0e710182 ? rpweqd f0, f1, f2
+0+078 <[^>]+> ee7a2143 ? rpwem f2, f2, f3
+0+07c <[^>]+> ee82118b ? rmfd f1, f2, #3\.0
+0+080 <[^>]+> 6e843104 ? rmfvss f3, f4, f4
+0+084 <[^>]+> ee8f4120 ? rmfep f4, f7, f0
+0+088 <[^>]+> ee910102 ? fmls f0, f1, f2
+0+08c <[^>]+> 0e931105 ? fmleqs f1, f3, f5
+0+090 <[^>]+> 5e964160 ? fmlplsz f4, f6, f0
+0+094 <[^>]+> eea3110f ? fdvs f1, f3, #10\.0
+0+098 <[^>]+> eea10122 ? fdvsp f0, f1, f2
+0+09c <[^>]+> 2ea44144 ? fdvcssm f4, f4, f4
+0+0a0 <[^>]+> eeb11109 ? frds f1, f1, #1\.0
+0+0a4 <[^>]+> ceb12100 ? frdgts f2, f1, f0
+0+0a8 <[^>]+> ceb44165 ? frdgtsz f4, f4, f5
+0+0ac <[^>]+> eec10182 ? pold f0, f1, f2
+0+0b0 <[^>]+> eec6416b ? polsz f4, f6, #3\.0
+0+0b4 <[^>]+> 0ece5107 ? poleqe f5, f6, f7
+0+0b8 <[^>]+> ee108101 ? mnfs f0, f1
+0+0bc <[^>]+> ee10818b ? mnfd f0, #3\.0
+0+0c0 <[^>]+> ee18816c ? mnfez f0, #4\.0
+0+0c4 <[^>]+> 0e188165 ? mnfeqez f0, f5
+0+0c8 <[^>]+> ee108124 ? mnfsp f0, f4
+0+0cc <[^>]+> ee1091c7 ? mnfdm f1, f7
+0+0d0 <[^>]+> ee208181 ? absd f0, f1
+0+0d4 <[^>]+> ee20912b ? abssp f1, #3\.0
+0+0d8 <[^>]+> 0e28c105 ? abseqe f4, f5
+0+0dc <[^>]+> ee309102 ? rnds f1, f2
+0+0e0 <[^>]+> ee30b184 ? rndd f3, f4
+0+0e4 <[^>]+> 0e38e16c ? rndeqez f6, #4\.0
+0+0e8 <[^>]+> ee40d105 ? sqts f5, f5
+0+0ec <[^>]+> ee40e1a6 ? sqtdp f6, f6
+0+0f0 <[^>]+> 5e48f166 ? sqtplez f7, f6
+0+0f4 <[^>]+> ee50810f ? logs f0, #10\.0
+0+0f8 <[^>]+> ee58810f ? loge f0, #10\.0
+0+0fc <[^>]+> 1e5081e1 ? lognedz f0, f1
+0+100 <[^>]+> ee689102 ? lgne f1, f2
+0+104 <[^>]+> ee6091e3 ? lgndz f1, f3
+0+108 <[^>]+> 7e60b104 ? lgnvcs f3, f4
+0+10c <[^>]+> ee709103 ? exps f1, f3
+0+110 <[^>]+> ee78b14f ? expem f3, #10\.0
+0+114 <[^>]+> 5e70e187 ? exppld f6, f7
+0+118 <[^>]+> ee808181 ? sind f0, f1
+0+11c <[^>]+> ee809142 ? sinsm f1, f2
+0+120 <[^>]+> ce88c10d ? singte f4, #5\.0
+0+124 <[^>]+> ee909183 ? cosd f1, f3
+0+128 <[^>]+> ee98c145 ? cosem f4, f5
+0+12c <[^>]+> 1e90e1a1 ? cosnedp f6, f1
+0+130 <[^>]+> eea89105 ? tane f1, f5
+0+134 <[^>]+> eea0c167 ? tansz f4, f7
+0+138 <[^>]+> aea091ec ? tangedz f1, #4\.0
+0+13c <[^>]+> eeb8c105 ? asne f4, f5
+0+140 <[^>]+> eeb0e12e ? asnsp f6, #0\.5
+0+144 <[^>]+> 4eb0d1e5 ? asnmidz f5, f5
+0+148 <[^>]+> eec0d106 ? acss f5, f6
+0+14c <[^>]+> eec0e180 ? acsd f6, f0
+0+150 <[^>]+> 2ec8914e ? acscsem f1, #0\.5
+0+154 <[^>]+> eed88105 ? atne f0, f5
+0+158 <[^>]+> eed0916d ? atnsz f1, #5\.0
+0+15c <[^>]+> bed0b182 ? atnltd f3, f2
+0+160 <[^>]+> eee8d104 ? urde f5, f4
+0+164 <[^>]+> eef8e105 ? nrme f6, f5
+0+168 <[^>]+> 5ef0f1e5 ? nrmpldz f7, f5
+0+16c <[^>]+> ee008130 ? fltsp f0, r8
+0+170 <[^>]+> ee090110 ? flte f1, r0
+0+174 <[^>]+> 0e0571f0 ? flteqdz f5, r7
+0+178 <[^>]+> ee100111 ? fix r0, f1
+0+17c <[^>]+> ee101177 ? fixz r1, f7
+0+180 <[^>]+> 2e105155 ? fixcsm r5, f5
+0+184 <[^>]+> ee400110 ? wfc r0
+0+188 <[^>]+> ee201110 ? wfs r1
+0+18c <[^>]+> 0e302110 ? rfseq r2
+0+190 <[^>]+> ee504110 ? rfc r4
+0+194 <[^>]+> ee90f119 ? cmf f0, #1\.0
+0+198 <[^>]+> ee91f112 ? cmf f1, f2
+0+19c <[^>]+> 0e90f111 ? cmfeq f0, f1
+0+1a0 <[^>]+> eeb0f11b ? cnf f0, #3\.0
+0+1a4 <[^>]+> eeb1f11e ? cnf f1, #0\.5
+0+1a8 <[^>]+> 6eb3f114 ? cnfvs f3, f4
+0+1ac <[^>]+> eed0f111 ? cmfe f0, f1
+0+1b0 <[^>]+> 0ed1f112 ? cmfeeq f1, f2
+0+1b4 <[^>]+> 0ed3f11d ? cmfeeq f3, #5\.0
+0+1b8 <[^>]+> eef1f113 ? cnfe f1, f3
+0+1bc <[^>]+> 0ef3f114 ? cnfeeq f3, f4
+0+1c0 <[^>]+> 0ef4f117 ? cnfeeq f4, f7
+0+1c4 <[^>]+> eef4f11d ? cnfe f4, #5\.0
+0+1c8 <[^>]+> ed900200 ? lfm f0, 4, \[r0\]
+0+1cc <[^>]+> ed900200 ? lfm f0, 4, \[r0\]
+0+1d0 <[^>]+> ed911210 ? lfm f1, 4, \[r1, #64\]
+0+1d4 <[^>]+> edae22ff ? sfm f2, 4, \[lr, #1020\]!
+0+1d8 <[^>]+> 0c68f2ff ? sfmeq f7, 3, \[r8\], #-1020
+0+1dc <[^>]+> eddf6200 ? lfm f6, 2, \[pc\]
+0+1e0 <[^>]+> eca8f203 ? sfm f7, 1, \[r8\], #12
+0+1e4 <[^>]+> 0d16520c ? lfmeq f5, 4, \[r6, #-48\]
+0+1e8 <[^>]+> 1d42c209 ? sfmne f4, 3, \[r2, #-36\]
+0+1ec <[^>]+> 1d62c209 ? sfmne f4, 3, \[r2, #-36\]!
===================================================================
Index: gas/testsuite/gas/arm/arm6.d
--- gas/testsuite/gas/arm/arm6.d (revision 0)
+++ gas/testsuite/gas/arm/arm6.d (revision 78)
@@ -0,0 +1,19 @@
+# name: ARM 6 instructions
+# as: -mcpu=arm6
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+00 <[^>]+> e10f8000 ? mrs r8, CPSR
+0+04 <[^>]+> e14f2000 ? mrs r2, SPSR
+0+08 <[^>]+> e129f001 ? msr CPSR_fc, r1
+0+0c <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 ; 0xf0000000
+0+10 <[^>]+> e168f008 ? msr SPSR_f, r8
+0+14 <[^>]+> e169f009 ? msr SPSR_fc, r9
+0+18 <[^>]+> e10f8000 ? mrs r8, CPSR
+0+1c <[^>]+> e14f2000 ? mrs r2, SPSR
+0+20 <[^>]+> e129f001 ? msr CPSR_fc, r1
+0+24 <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 ; 0xf0000000
+0+28 <[^>]+> e168f008 ? msr SPSR_f, r8
+0+2c <[^>]+> e169f009 ? msr SPSR_fc, r9
===================================================================
Index: gas/testsuite/gas/arm/thumb.d
--- gas/testsuite/gas/arm/thumb.d (revision 0)
+++ gas/testsuite/gas/arm/thumb.d (revision 78)
@@ -0,0 +1,183 @@
+# name: Thumb instructions
+# as: -mcpu=arm7t
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section \.text:
+0+000 <[^>]+> 00ca lsls r2, r1, #3
+0+002 <[^>]+> 0fe3 lsrs r3, r4, #31
+0+004 <[^>]+> 1147 asrs r7, r0, #5
+0+006 <[^>]+> 0011 lsls r1, r2, #0
+0+008 <[^>]+> 0023 lsls r3, r4, #0
+0+00a <[^>]+> 002c lsls r4, r5, #0
+0+00c <[^>]+> 083e lsrs r6, r7, #32
+0+00e <[^>]+> 1008 asrs r0, r1, #32
+0+010 <[^>]+> 18d1 adds r1, r2, r3
+0+012 <[^>]+> 1ca2 adds r2, r4, #2
+0+014 <[^>]+> 1beb sub r3, r5, r7
+0+016 <[^>]+> 1fe2 sub r2, r4, #7
+0+018 <[^>]+> 24ff movs r4, #255
+0+01a <[^>]+> 2bfa cmp r3, #250
+0+01c <[^>]+> 367b adds r6, #123
+0+01e <[^>]+> 3d80 subs r5, #128
+0+020 <[^>]+> 402b ands r3, r5
+0+022 <[^>]+> 4074 eors r4, r6
+0+024 <[^>]+> 4081 lsls r1, r0
+0+026 <[^>]+> 40da lsrs r2, r3
+0+028 <[^>]+> 4134 asrs r4, r6
+0+02a <[^>]+> 417d adcs r5, r7
+0+02c <[^>]+> 41a0 sbcs r0, r4
+0+02e <[^>]+> 41e1 rors r1, r4
+0+030 <[^>]+> 422a tst r2, r5
+0+032 <[^>]+> 4249 rsbs r1, r1, #0
+0+034 <[^>]+> 429a cmp r2, r3
+0+036 <[^>]+> 42e1 cmn r1, r4
+0+038 <[^>]+> 4318 orrs r0, r3
+0+03a <[^>]+> 436c muls r4, r5
+0+03c <[^>]+> 43bd bics r5, r7
+0+03e <[^>]+> 43ed mvns r5, r5
+0+040 <[^>]+> 4469 add r1, sp
+0+042 <[^>]+> 4494 add ip, r2
+0+044 <[^>]+> 44c9 add r9, r9
+0+046 <[^>]+> 4571 cmp r1, lr
+0+048 <[^>]+> 4580 cmp r8, r0
+0+04a <[^>]+> 45f4 cmp ip, lr
+0+04c <[^>]+> 4648 mov r0, r9
+0+04e <[^>]+> 46a1 mov r9, r4
+0+050 <[^>]+> 46c0 nop \(mov r8, r8\)
+0+052 <[^>]+> 4738 bx r7
+0+054 <[^>]+> 4740 bx r8
+0+056 <[^>]+> 0000 lsls r0, r0, #0
+0+058 <[^>]+> 4778 bx pc
+0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] \(0+0dc <[^>]+>\)
+0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] \(0+068 <[^>]+>\)
+0+05e <[^>]+> 5088 str r0, \[r1, r2\]
+0+060 <[^>]+> 5511 strb r1, \[r2, r4\]
+0+062 <[^>]+> 59f5 ldr r5, \[r6, r7\]
+0+064 <[^>]+> 5d62 ldrb r2, \[r4, r5\]
+ \.\.\.
+0+068 <[^>]+> 52d1 strh r1, \[r2, r3\]
+0+06a <[^>]+> 5a23 ldrh r3, \[r4, r0\]
+0+06c <[^>]+> 57f1 ldrsb r1, \[r6, r7\]
+0+06e <[^>]+> 5f42 ldrsh r2, \[r0, r5\]
+0+070 <[^>]+> 67db str r3, \[r3, #124\]
+0+072 <[^>]+> 6fe1 ldr r1, \[r4, #124\]
+0+074 <[^>]+> 682d ldr r5, \[r5, #0\]
+0+076 <[^>]+> 77e9 strb r1, \[r5, #31\]
+0+078 <[^>]+> 7161 strb r1, \[r4, #5\]
+0+07a <[^>]+> 7032 strb r2, \[r6, #0\]
+0+07c <[^>]+> 87ec strh r4, \[r5, #62\]
+0+07e <[^>]+> 8885 ldrh r5, \[r0, #4\]
+0+080 <[^>]+> 8813 ldrh r3, \[r2, #0\]
+0+082 <[^>]+> 93ff str r3, \[sp, #1020\]
+0+084 <[^>]+> 990b ldr r1, \[sp, #44\]
+0+086 <[^>]+> 9a00 ldr r2, \[sp, #0\]
+0+088 <[^>]+> a7ff add r7, pc, #1020 \(adr r7,0+488 <[^>]+>\)
+0+08a <[^>]+> ac80 add r4, sp, #512
+0+08c <[^>]+> b043 add sp, #268
+0+08e <[^>]+> b09a sub sp, #104
+0+090 <[^>]+> b0c3 sub sp, #268
+0+092 <[^>]+> b01b add sp, #108
+0+094 <[^>]+> b417 push {r0, r1, r2, r4}
+0+096 <[^>]+> b5f9 push {r0, r3, r4, r5, r6, r7, lr}
+0+098 <[^>]+> bc98 pop {r3, r4, r7}
+0+09a <[^>]+> bdff pop {r0, r1, r2, r3, r4, r5, r6, r7, pc}
+0+09c <[^>]+> c3f3 stmia r3!,{r0, r1, r4, r5, r6, r7}
+0+09e <[^>]+> c8fe ldmia r0!,{r1, r2, r3, r4, r5, r6, r7}
+0+0a0 <[^>]+> d0e2 beq.n 0+068 <[^>]+>
+0+0a2 <[^>]+> d1e1 bne.n 0+068 <[^>]+>
+0+0a4 <[^>]+> d2e0 bcs.n 0+068 <[^>]+>
+0+0a6 <[^>]+> d3df bcc.n 0+068 <[^>]+>
+0+0a8 <[^>]+> d4de bmi.n 0+068 <[^>]+>
+0+0aa <[^>]+> d5dd bpl.n 0+068 <[^>]+>
+0+0ac <[^>]+> d6dc bvs.n 0+068 <[^>]+>
+0+0ae <[^>]+> d7db bvc.n 0+068 <[^>]+>
+0+0b0 <[^>]+> d8da bhi.n 0+068 <[^>]+>
+0+0b2 <[^>]+> d9d9 bls.n 0+068 <[^>]+>
+0+0b4 <[^>]+> dad8 bge.n 0+068 <[^>]+>
+0+0b6 <[^>]+> dcd7 bgt.n 0+068 <[^>]+>
+0+0b8 <[^>]+> dbd6 blt.n 0+068 <[^>]+>
+0+0ba <[^>]+> dcd5 bgt.n 0+068 <[^>]+>
+0+0bc <[^>]+> ddd4 ble.n 0+068 <[^>]+>
+0+0be <[^>]+> d8d3 bhi.n 0+068 <[^>]+>
+0+0c0 <[^>]+> d3d2 bcc.n 0+068 <[^>]+>
+0+0c2 <[^>]+> d3d1 bcc.n 0+068 <[^>]+>
+0+0c4 <[^>]+> ded0 bal.n 0+068 <[^>]+>
+0+0c6 <[^>]+> 00ac lsls r4, r5, #2
+0+0c8 <[^>]+> 1c9a adds r2, r3, #2
+0+0ca <[^>]+> b07f add sp, #508
+0+0cc <[^>]+> b0ff sub sp, #508
+0+0ce <[^>]+> a8ff add r0, sp, #1020
+0+0d0 <[^>]+> a0ff add r0, pc, #1020 \(adr r0,0+4d0 <[^>]+>\)
+0+0d2 <[^>]+> b01a add sp, #104
+0+0d4 <[^>]+> b09a sub sp, #104
+0+0d6 <[^>]+> a81a add r0, sp, #104
+0+0d8 <[^>]+> a01a add r0, pc, #104 \(adr r0,0+144 <[^>]+>\)
+0+0da <[^>]+> 3168 adds r1, #104
+0+0dc <[^>]+> 2668 movs r6, #104
+0+0de <[^>]+> 2f68 cmp r7, #104
+0+0e0 <[^>]+> 46c0 nop \(mov r8, r8\)
+0+0e2 <[^>]+> 46c0 nop \(mov r8, r8\)
+0+0e4 <[^>]+> ea000037 b 0+0e4 <[^>]+>
+ e4: R_ARM_PC24 \.text
+0+0e8 <[^>]+> eafffffe b 0+000 <[^>]+>
+ e8: R_ARM_PC24 \.wombat
+0+0ec <[^>]+> eb000037 bl 0+0e4 <[^>]+>
+ ec: R_ARM_PC24 \.text
+0+0f0 <[^>]+> ebfffffe bl 0+000 <[^>]+>
+ f0: R_ARM_PC24 \.wombat
+0+0f4 <[^>]+> e12fff10 bx r0
+0+0f8 <[^>]+> ef123456 swi 0x00123456
+0+0fc <[^>]+> a004 add r0, pc, #16 \(adr r0,0+110 <[^>]+>\)
+0+0fe <[^>]+> e77f b.n 0+000 <[^>]+>
+0+100 <[^>]+> e7fe b.n 0+000 <[^>]+>
+ 100: R_ARM_THM_JUMP11 \.wombat
+0+102 <[^>]+> f7ff fffe bl 0+000 <[^>]+>
+ 102: R_ARM_THM_CALL \.text
+0+106 <[^>]+> f7ff fffe bl 0+000 <[^>]+>
+ 106: R_ARM_THM_CALL \.wombat
+0+10a <[^>]+> 4700 bx r0
+0+10c <[^>]+> dfff swi 255
+ \.\.\.
+0+110 <[^>]+> d0fe beq.n 0+000 <[^>]+>
+ 110: R_ARM_THM_JUMP8 \.wombat
+0+112 <[^>]+> d1fe bne.n 0+000 <[^>]+>
+ 112: R_ARM_THM_JUMP8 \.wombat
+0+114 <[^>]+> d2fe bcs.n 0+000 <[^>]+>
+ 114: R_ARM_THM_JUMP8 \.wombat
+0+116 <[^>]+> d3fe bcc.n 0+000 <[^>]+>
+ 116: R_ARM_THM_JUMP8 \.wombat
+0+118 <[^>]+> d4fe bmi.n 0+000 <[^>]+>
+ 118: R_ARM_THM_JUMP8 \.wombat
+0+11a <[^>]+> d5fe bpl.n 0+000 <[^>]+>
+ 11a: R_ARM_THM_JUMP8 \.wombat
+0+11c <[^>]+> d6fe bvs.n 0+000 <[^>]+>
+ 11c: R_ARM_THM_JUMP8 \.wombat
+0+11e <[^>]+> d7fe bvc.n 0+000 <[^>]+>
+ 11e: R_ARM_THM_JUMP8 \.wombat
+0+120 <[^>]+> d8fe bhi.n 0+000 <[^>]+>
+ 120: R_ARM_THM_JUMP8 \.wombat
+0+122 <[^>]+> d9fe bls.n 0+000 <[^>]+>
+ 122: R_ARM_THM_JUMP8 \.wombat
+0+124 <[^>]+> dafe bge.n 0+000 <[^>]+>
+ 124: R_ARM_THM_JUMP8 \.wombat
+0+126 <[^>]+> dcfe bgt.n 0+000 <[^>]+>
+ 126: R_ARM_THM_JUMP8 \.wombat
+0+128 <[^>]+> dbfe blt.n 0+000 <[^>]+>
+ 128: R_ARM_THM_JUMP8 \.wombat
+0+12a <[^>]+> dcfe bgt.n 0+000 <[^>]+>
+ 12a: R_ARM_THM_JUMP8 \.wombat
+0+12c <[^>]+> ddfe ble.n 0+000 <[^>]+>
+ 12c: R_ARM_THM_JUMP8 \.wombat
+0+12e <[^>]+> d8fe bhi.n 0+000 <[^>]+>
+ 12e: R_ARM_THM_JUMP8 \.wombat
+0+130 <[^>]+> d3fe bcc.n 0+000 <[^>]+>
+ 130: R_ARM_THM_JUMP8 \.wombat
+0+132 <[^>]+> d3fe bcc.n 0+000 <[^>]+>
+ 132: R_ARM_THM_JUMP8 \.wombat
+0+134 <[^>]+> f000 fc9a bl 0+938 <[^>]+>
+ 134: R_ARM_THM_CALL \.text
+ \.\.\.
+0+938 <[^>]+> f000 f898 bl 0+134 <[^>]+>
+ 938: R_ARM_THM_CALL \.text
===================================================================
Index: gas/testsuite/gas/arm/float.s
--- gas/testsuite/gas/arm/float.s (revision 77)
+++ gas/testsuite/gas/arm/float.s (revision 78)
@@ -1,5 +1,6 @@
-.text
-.align 0
+ .text
+ .align 0
+l:
mvfe f0, f1
mvfeqe f3, f5
mvfeqd f4, #1.0
===================================================================
Index: gas/testsuite/gas/arm/arm6.s
--- gas/testsuite/gas/arm/arm6.s (revision 77)
+++ gas/testsuite/gas/arm/arm6.s (revision 78)
@@ -1,6 +1,6 @@
-.text
-.align 0
-
+ .text
+ .align 0
+l:
mrs r8, cpsr
mrs r2, spsr
@@ -16,4 +16,3 @@
msrne CPSR_flg, #0xf0000000
msr SPSR_flg, r8
msr SPSR_all, r9
-
===================================================================
Index: gas/testsuite/gas/arm/arch4t.d
--- gas/testsuite/gas/arm/arch4t.d (revision 0)
+++ gas/testsuite/gas/arm/arch4t.d (revision 78)
@@ -0,0 +1,36 @@
+# name: ARM architecture 4t instructions
+# as: -march=armv4t
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+00 <[^>]+> e12fff10 ? bx r0
+0+04 <[^>]+> 012fff11 ? bxeq r1
+0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] ; 0+08 <[^>]+>
+0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5\]
+0+10 <[^>]+> e19140d3 ? ldrsb r4, \[r1, r3\]
+0+14 <[^>]+> e1b410f4 ? ldrsh r1, \[r4, r4\]!
+0+18 <[^>]+> 011510d3 ? ldreqsb r1, \[r5, -r3\]
+0+1c <[^>]+> 109620b7 ? ldrneh r2, \[r6\], r7
+0+20 <[^>]+> 309720f8 ? ldrccsh r2, \[r7\], r8
+0+24 <[^>]+> e1d32fdf ? ldrsb r2, \[r3, #255\]
+0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\]
+0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\]
+0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+>
+0+34 <[^>]+> 11c330b0 ? strneh r3, \[r3\]
+0+38 <[^>]+> e328f002 ? msr CPSR_f, #2 ; 0x2
+0+3c <[^>]+> e121f003 ? msr CPSR_c, r3
+0+40 <[^>]+> e122f004 ? msr CPSR_x, r4
+0+44 <[^>]+> e124f005 ? msr CPSR_s, r5
+0+48 <[^>]+> e128f006 ? msr CPSR_f, r6
+0+4c <[^>]+> e129f007 ? msr CPSR_fc, r7
+0+50 <[^>]+> e368f004 ? msr SPSR_f, #4 ; 0x4
+0+54 <[^>]+> e161f008 ? msr SPSR_c, r8
+0+58 <[^>]+> e162f009 ? msr SPSR_x, r9
+0+5c <[^>]+> e164f00a ? msr SPSR_s, sl
+0+60 <[^>]+> e168f00b ? msr SPSR_f, fp
+0+64 <[^>]+> e169f00c ? msr SPSR_fc, ip
+0+68 <[^>]+> e1a00000 ? nop \(mov r0,r0\)
+0+6c <[^>]+> e1a00000 ? nop \(mov r0,r0\)
+
===================================================================
Index: gas/testsuite/gas/arm/arm7dm.d
--- gas/testsuite/gas/arm/arm7dm.d (revision 0)
+++ gas/testsuite/gas/arm/arm7dm.d (revision 78)
@@ -0,0 +1,19 @@
+# name: ARM 7DM instructions
+# as: -mcpu=arm7dm
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+00 <[^>]+> e0c10392 ? smull r0, r1, r2, r3
+0+04 <[^>]+> e0810392 ? umull r0, r1, r2, r3
+0+08 <[^>]+> e0e10392 ? smlal r0, r1, r2, r3
+0+0c <[^>]+> e0a10394 ? umlal r0, r1, r4, r3
+0+10 <[^>]+> 10c10493 ? smullne r0, r1, r3, r4
+0+14 <[^>]+> e0d01b99 ? smulls r1, r0, r9, fp
+0+18 <[^>]+> 00b92994 ? umlaleqs r2, r9, r4, r9
+0+1c <[^>]+> a0eaee98 ? smlalge lr, sl, r8, lr
+0+20 <[^>]+> e322f000 ? msr CPSR_x, #0 ; 0x0
+0+24 <[^>]+> e1a00000 ? nop \(mov r0,r0\)
+0+28 <[^>]+> e1a00000 ? nop \(mov r0,r0\)
+0+2c <[^>]+> e1a00000 ? nop \(mov r0,r0\)
===================================================================
Index: gas/testsuite/gas/arm/arch4t.s
--- gas/testsuite/gas/arm/arch4t.s (revision 77)
+++ gas/testsuite/gas/arm/arch4t.s (revision 78)
@@ -1,6 +1,6 @@
-.text
-.align 0
-
+ .text
+ .align 0
+l:
bx r0
bxeq r1
@@ -33,3 +33,6 @@
msr SPSR_f, r11
msr SPSR_all, r12
bar:
+ @ section padding for a.out's benefit
+ nop
+ nop
===================================================================
Index: gas/testsuite/gas/arm/arm7dm.s
--- gas/testsuite/gas/arm/arm7dm.s (revision 77)
+++ gas/testsuite/gas/arm/arm7dm.s (revision 78)
@@ -1,6 +1,6 @@
-.text
-.align 0
-
+ .text
+ .align 0
+l:
smull r0, r1, r2, r3
umull r0, r1, r2, r3
smlal r0, r1, r2, r3
@@ -11,4 +11,10 @@
umlaleqs r2, r9, r4, r9
smlalge r14, r10, r8, r14
- msr CPSR_x, #0 @ This used to be illegal, but rev 2 of the ARM ARM allows it.
+ @ This used to be illegal, but rev 2 of the ARM ARM allows it.
+ msr CPSR_x, #0
+
+ @ padding for a.out's sake
+ nop
+ nop
+ nop