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[Patch gas] MIPS: mips16e options for gas
- From: David Ung <davidu at mips dot com>
- To: binutils at sources dot redhat dot com
- Date: Wed, 08 Jun 2005 16:37:32 +0100
- Subject: [Patch gas] MIPS: mips16e options for gas
The following patch adds the command line options -mips16e and
-no-mips16e (also .set mips16e and .set nomips16e) to gas. The
no-mips16e is really optional and its there mainly for completeness.
There's also some discussion of it on the gcc-patch list.
David.
2005-06-08 David Ung <davidu@mips.com>
* config/tc-mips.c (struct mips_set_options): Add option
mips16e. Changed by the ".set" directive or by command line
options.
(mips_opts): Initialize mips16e to -1.
(ISA_SUPPORT_MIPS16E): True if ISA is one of
mips32/mip32r2/mips64/mips64r2.
(OPTION_MIPS16E, OPTION_NO_MIPS16E): New options.
(OPTION_MIPS3D, OPTION_NO_MIPS3D, OPTION_MDMX, OPTION_NO_MDMX)
(OPTION_COMPAT_ARCH_BASE): Change offsets.
(md_parse_option): Parse mips16e options.
(mips_after_parse_args): Enable mips16 if mips16e is
enabled. Enable mips16e if mips16 and ISA_SUPPORT_MIPS16E.
(s_mipsset): Similarly.
(md_show_usage): Add -mips16e and -no-mips16e.
* doc/as.texinfo: Update and add -mips16e, -no-mips16e options.
* doc/c-mips.texi: Similarly.
Index: src/gas/config/tc-mips.c
===================================================================
RCS file: /cvsroot/gcc/src-cvs/src/gas/config/tc-mips.c,v
retrieving revision 1.315
diff -c -p -b -r1.315 tc-mips.c
*** src/gas/config/tc-mips.c 7 Jun 2005 17:54:17 -0000 1.315
--- src/gas/config/tc-mips.c 8 Jun 2005 15:35:04 -0000
*************** struct mips_set_options
*** 198,203 ****
--- 198,208 ----
Changed by `.set mips16' and `.set nomips16', and the -mips16 and
-nomips16 command line options, and the default CPU. */
int mips16;
+ /* Whether we are assembling with mips16e extension. 0 if we are
+ not, 1 if we are, and -1 if the value has not been initialized.
+ Changed by `.set mips16e' and `.set nomips16e', and the -mips16e and
+ -nomips16e command line options, and the default CPU. */
+ int mips16e;
/* Non-zero if we should not reorder instructions. Changed by `.set
reorder' and `.set noreorder'. */
int noreorder;
*************** static int file_mips_fp32 = -1;
*** 243,249 ****
static struct mips_set_options mips_opts =
{
! ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
};
/* These variables are filled in with the masks of registers used.
--- 248,254 ----
static struct mips_set_options mips_opts =
{
! ISA_UNKNOWN, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
};
/* These variables are filled in with the masks of registers used.
*************** static int file_mips_isa = ISA_UNKNOWN;
*** 259,264 ****
--- 264,274 ----
command line (e.g., by -march). */
static int file_ase_mips16;
+ #define ISA_SUPPORT_MIPS16E (mips_opts.isa == ISA_MIPS32 \
+ || mips_opts.isa == ISA_MIPS32R2 \
+ || mips_opts.isa == ISA_MIPS64 \
+ || mips_opts.isa == ISA_MIPS64R2)
+
/* True if -mips3d was passed or implied by arguments passed on the
command line (e.g., by -march). */
static int file_ase_mips3d;
*************** struct option md_longopts[] =
*** 10019,10035 ****
{"mips16", no_argument, NULL, OPTION_MIPS16},
#define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
{"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
! #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
{"mips3d", no_argument, NULL, OPTION_MIPS3D},
! #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
{"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
! #define OPTION_MDMX (OPTION_ASE_BASE + 4)
{"mdmx", no_argument, NULL, OPTION_MDMX},
! #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
{"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
/* Old-style architecture options. Don't add more of these. */
! #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
{"m4650", no_argument, NULL, OPTION_M4650},
#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
--- 10029,10049 ----
{"mips16", no_argument, NULL, OPTION_MIPS16},
#define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
{"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
! #define OPTION_MIPS16E (OPTION_ASE_BASE + 2)
! {"mips16e", no_argument, NULL, OPTION_MIPS16E},
! #define OPTION_NO_MIPS16E (OPTION_ASE_BASE + 3)
! {"no-mips16e", no_argument, NULL, OPTION_NO_MIPS16E},
! #define OPTION_MIPS3D (OPTION_ASE_BASE + 4)
{"mips3d", no_argument, NULL, OPTION_MIPS3D},
! #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 5)
{"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
! #define OPTION_MDMX (OPTION_ASE_BASE + 6)
{"mdmx", no_argument, NULL, OPTION_MDMX},
! #define OPTION_NO_MDMX (OPTION_ASE_BASE + 7)
{"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
/* Old-style architecture options. Don't add more of these. */
! #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 8)
#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
{"m4650", no_argument, NULL, OPTION_M4650},
#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
*************** md_parse_option (int c, char *arg)
*** 10291,10296 ****
--- 10305,10320 ----
mips_no_prev_insn ();
break;
+ case OPTION_MIPS16E:
+ mips_opts.mips16e = 1;
+ mips_no_prev_insn ();
+ break;
+
+ case OPTION_NO_MIPS16E:
+ mips_opts.mips16e = 0;
+ mips_no_prev_insn ();
+ break;
+
case OPTION_MIPS3D:
mips_opts.ase_mips3d = 1;
break;
*************** mips_after_parse_args (void)
*** 10631,10636 ****
--- 10655,10665 ----
generation of code for them. */
if (mips_opts.mips16 == -1)
mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
+ if (mips_opts.mips16e == 1)
+ /* Automatically set mips16 if mips16e is set */
+ mips_opts.mips16 = 1;
+ else if (mips_opts.mips16 == 1 && ISA_SUPPORT_MIPS16E)
+ mips_opts.mips16e = 1
if (mips_opts.ase_mips3d == -1)
mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
if (mips_opts.ase_mdmx == -1)
*************** s_mipsset (int x ATTRIBUTE_UNUSED)
*** 11550,11559 ****
--- 11579,11606 ----
}
else if (strcmp (name, "mips16") == 0
|| strcmp (name, "MIPS-16") == 0)
+ {
mips_opts.mips16 = 1;
+ if (ISA_SUPPORT_MIPS16E)
+ mips_opts.mips16e = 1;
+ }
else if (strcmp (name, "nomips16") == 0
|| strcmp (name, "noMIPS-16") == 0)
+ {
+ mips_opts.mips16 = 0;
+ mips_opts.mips16e = 0;
+ }
+ else if (strcmp (name, "mips16e") == 0)
+ {
+ mips_opts.mips16e = 1;
+ mips_opts.mips16 = 1;
+ }
+ else if (strcmp (name, "nomips16e") == 0
+ || strcmp (name, "noMIPS-16e") == 0)
+ {
mips_opts.mips16 = 0;
+ mips_opts.mips16e = 0;
+ }
else if (strcmp (name, "mips3d") == 0)
mips_opts.ase_mips3d = 1;
else if (strcmp (name, "nomips3d") == 0)
*************** MIPS options:\n\
*** 13997,14003 ****
fprintf (stream, _("\
-mips16 generate mips16 instructions\n\
! -no-mips16 do not generate mips16 instructions\n"));
fprintf (stream, _("\
-mfix-vr4120 work around certain VR4120 errata\n\
-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
--- 14044,14052 ----
fprintf (stream, _("\
-mips16 generate mips16 instructions\n\
! -no-mips16 do not generate mips16 instructions\n\
! -mips16e generate mips16e instructions\n\
! -no-mips16e do not generate mips16e instructions\n"));
fprintf (stream, _("\
-mfix-vr4120 work around certain VR4120 errata\n\
-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
Index: src/gas/doc/as.texinfo
===================================================================
RCS file: /cvsroot/gcc/src-cvs/src/gas/doc/as.texinfo,v
retrieving revision 1.122
diff -c -p -b -r1.122 as.texinfo
*** src/gas/doc/as.texinfo 6 May 2005 06:50:29 -0000 1.122
--- src/gas/doc/as.texinfo 8 Jun 2005 15:35:35 -0000
*************** gcc(1), ld(1), and the Info entries for
*** 367,372 ****
--- 367,373 ----
[@b{-trap}] [@b{-no-break}] [@b{-break}] [@b{-no-trap}]
[@b{-mfix7000}] [@b{-mno-fix7000}]
[@b{-mips16}] [@b{-no-mips16}]
+ [@b{-mips16e}] [@b{-no-mips16e}]
[@b{-mips3d}] [@b{-no-mips3d}]
[@b{-mdmx}] [@b{-no-mdmx}]
[@b{-mdebug}] [@b{-no-mdebug}]
*************** and @samp{-mfp32} controls the size of f
*** 970,978 ****
@item -mips16
@itemx -no-mips16
! Generate code for the MIPS 16 processor. This is equivalent to putting
@code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
! turns off this option.
@item -mips3d
@itemx -no-mips3d
--- 971,987 ----
@item -mips16
@itemx -no-mips16
! Generate code for the MIPS16 ASE. This is equivalent to putting
@code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
! turns off this option. Note that the following ISAs will automatically
! enable MIPS16e; MIPS32, MIPS32R2, MIPS64 and MIPS64R2.
!
! @item -mips16e
! @itemx -no-mips16e
! Generate code for the MIPS16e ASE. This is equivalent to putting
! @code{.set mips16e} at the start of the assembly file. MIPS16e include
! all MIPS16 instructions. @samp{-no-mips16e} turns off this option,
! same as @samp{-no-mips16}.
@item -mips3d
@itemx -no-mips3d
Index: src/gas/doc/c-mips.texi
===================================================================
RCS file: /cvsroot/gcc/src-cvs/src/gas/doc/c-mips.texi,v
retrieving revision 1.34
diff -c -p -b -r1.34 c-mips.texi
*** src/gas/doc/c-mips.texi 9 Mar 2005 09:53:49 -0000 1.34
--- src/gas/doc/c-mips.texi 8 Jun 2005 15:35:46 -0000
*************** provided in the interests of symmetry wi
*** 102,110 ****
@item -mips16
@itemx -no-mips16
! Generate code for the MIPS 16 processor. This is equivalent to putting
! @samp{.set mips16} at the start of the assembly file. @samp{-no-mips16}
! turns off this option.
@item -mips3d
@itemx -no-mips3d
--- 102,118 ----
@item -mips16
@itemx -no-mips16
! Generate code for the MIPS16 ASE. This is equivalent to putting
! @code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
! turns off this option. Note that the following ISAs will automatically
! enable MIPS16e; MIPS32, MIPS32R2, MIPS64 and MIPS64R2.
!
! @item -mips16e
! @itemx -no-mips16e
! Generate code for the MIPS16e ASE. This is equivalent to putting
! @code{.set mips16e} at the start of the assembly file. MIPS16e include
! all MIPS16 instructions. @samp{-no-mips16e} turns off this option,
! same as @samp{-no-mips16}.
@item -mips3d
@itemx -no-mips3d
*************** care!
*** 386,391 ****
--- 394,402 ----
The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
in which it will assemble instructions for the MIPS 16 processor. Use
@samp{.set nomips16} to return to normal 32 bit mode.
+ The directive @samp{.set mips16e} is similar, but enables the extended
+ MIPS16e instruction set. Use @samp{.set nomips16e} or
+ @samp{.set nomips16} to return to normal 32 bit mode.
Traditional @sc{mips} assemblers do not support this directive.