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Blackfin patch: Don't generate unnecessary relocation stacks in gas
- From: Bernd Schmidt <bernds_cb1 at t-online dot de>
- To: binutils at sources dot redhat dot com
- Date: Mon, 24 Oct 2005 20:43:04 +0200
- Subject: Blackfin patch: Don't generate unnecessary relocation stacks in gas
This is a followup to (and reason for) my earlier linker patch. It
prevents the generation of relocation stacks for (symbol + constant)
relocations, which means we shouldn't be generating them at all.
Instead, we just put the constant into the relocation's offset field.
This was necessary because the module loader in our kernel doesn't
handle the relocation stacks.
Committed.
Bernd
gas:
* config/tc-bfin.c (Expr_Node_Gen_Reloc): If have symbol + constant,
make a single reloc with an offset rather than a stack.
* config/tc-bfin.h (MD_APPLY_SYM_VALUE): Define to 0.
testsuite:
* gas/bfin/flow2.d: Match changed assembler behaviour.
* gas/bfin/reloc.d: Likewise.
Index: config/tc-bfin.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-bfin.c,v
retrieving revision 1.3
diff -c -p -r1.3 tc-bfin.c
*** config/tc-bfin.c 24 Oct 2005 16:31:22 -0000 1.3
--- config/tc-bfin.c 24 Oct 2005 18:28:59 -0000
*************** Expr_Node_Gen_Reloc (Expr_Node * head, i
*** 1003,1008 ****
--- 1003,1023 ----
if (note1 != NULL_CODE)
note = conscode (note1, note);
}
+ else if (head->type == Expr_Node_Binop
+ && (head->value.op_value == Expr_Op_Type_Add
+ || head->value.op_value == Expr_Op_Type_Sub)
+ && head->Left_Child->type == Expr_Node_Reloc
+ && head->Right_Child->type == Expr_Node_Constant)
+ {
+ int val = head->Right_Child->value.i_value;
+ if (head->value.op_value == Expr_Op_Type_Sub)
+ val = -val;
+ note = conscode (note_reloc2 (gencode (0), head->Left_Child->value.s_value,
+ parent_reloc, val, 0),
+ NULL_CODE);
+ if (note1 != NULL_CODE)
+ note = conscode (note1, note);
+ }
else
{
/* Call the recursive function. */
Index: config/tc-bfin.h
===================================================================
RCS file: /cvs/src/src/gas/config/tc-bfin.h,v
retrieving revision 1.1
diff -c -p -r1.1 tc-bfin.h
*** config/tc-bfin.h 30 Sep 2005 15:05:06 -0000 1.1
--- config/tc-bfin.h 24 Oct 2005 18:28:59 -0000
*************** extern int bfin_force_relocation PARAMS
*** 72,75 ****
--- 72,84 ----
#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
+ /* Values passed to md_apply_fix3 don't include symbol values. */
+ #define MD_APPLY_SYM_VALUE(FIX) 0
+
/* end of tc-bfin.h */
Index: testsuite/gas/bfin/reloc.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/bfin/reloc.d,v
retrieving revision 1.1
diff -c -p -r1.1 reloc.d
*** testsuite/gas/bfin/reloc.d 30 Sep 2005 15:10:16 -0000 1.1
--- testsuite/gas/bfin/reloc.d 24 Oct 2005 18:29:00 -0000
*************** RELOCATION RECORDS FOR \[\.text\]:
*** 6,19 ****
OFFSET TYPE VALUE
0*0004 R_pcrel24 _call_data1
0*0008 R_rimm16 .data
! 0*000a R_expst_push .text\+0x0000001c
! 0*000a R_expst_const .__constant\+0x00000004
! 0*000a R_expst_sub .__operator
! 0*000a R_pcrel12_jump_s .__operator
! 0*000c R_expst_push call_data1
! 0*000c R_expst_const .__constant\+0x00000008
! 0*000c R_expst_add .__operator
! 0*000e R_pcrel24 .__operator
0*0012 R_huimm16 .data\+0x00000002
0*0016 R_luimm16 .data\+0x00000004
0*001a R_huimm16 load_extern1
--- 6,13 ----
OFFSET TYPE VALUE
0*0004 R_pcrel24 _call_data1
0*0008 R_rimm16 .data
! 0*000a R_pcrel12_jump_s .text\+0x00000018
! 0*000e R_pcrel24 call_data1\+0x00000008
0*0012 R_huimm16 .data\+0x00000002
0*0016 R_luimm16 .data\+0x00000004
0*001a R_huimm16 load_extern1
Index: testsuite/gas/bfin/flow2.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/bfin/flow2.d,v
retrieving revision 1.1
diff -c -p -r1.1 flow2.d
*** testsuite/gas/bfin/flow2.d 30 Sep 2005 15:10:16 -0000 1.1
--- testsuite/gas/bfin/flow2.d 24 Oct 2005 18:29:00 -0000
*************** Disassembly of section .text:
*** 41,49 ****
48: 00 e2 01 00 JUMP.L 4a <MY_LABEL1\+0x20>;
4c: ff e2 ff ff JUMP.L 4a <MY_LABEL1\+0x20>;
50: ed 2f JUMP.S 2a <MY_LABEL1>;
! 52: d7 2f JUMP.S 0 <MY_LABEL1-0x2a>;
! 54: ea 2f JUMP.S 28 <MY_LABEL1-0x2>;
! 56: d4 2f JUMP.S fffffffe.*
58: 04 1b IF CC JUMP fffffe60.*
5a: 5a 18 IF CC JUMP 10e.*
5c: 00 18 IF CC JUMP 5c <MY_LABEL1\+0x32>;
--- 41,49 ----
48: 00 e2 01 00 JUMP.L 4a <MY_LABEL1\+0x20>;
4c: ff e2 ff ff JUMP.L 4a <MY_LABEL1\+0x20>;
50: ed 2f JUMP.S 2a <MY_LABEL1>;
! 52: d7 2f JUMP.S 0 .*
! 54: d6 2f JUMP.S 0 .*
! 56: d5 2f JUMP.S 0 .*
58: 04 1b IF CC JUMP fffffe60.*
5a: 5a 18 IF CC JUMP 10e.*
5c: 00 18 IF CC JUMP 5c <MY_LABEL1\+0x32>;