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Blackfin disassembler fixes
- From: Bernd Schmidt <bernds_cb1 at t-online dot de>
- To: binutils at sources dot redhat dot com
- Date: Thu, 16 Mar 2006 20:10:17 +0100
- Subject: Blackfin disassembler fixes
This patch fixes a few bugs in the Blackfin disassembler; halfword
shifts weren't being handled correctly in all cases. Assembler
testcases are updated and a few new ones added.
Committed.
Bernd
Index: gas/testsuite/ChangeLog.bfin
2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
* gas/bfin/shift2.s: Add new tests.
* gas/bfin/shift.d: Match changed disassembler behaviour.
* gas/bfin/parallel2.d: Likewise.
* gas/bfin/shift2.d: Likewise; also match new tests.
Index: opcodes/ChangeLog.bfin
2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
* bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
logic to identify halfword shifts.
Index: gas/testsuite/gas/bfin/parallel2.d
===================================================================
RCS file: /cvsroot/gcc3/binutils/binutils-2.15/gas/testsuite/gas/bfin/parallel2.d,v
retrieving revision 1.4
diff -c -p -r1.4 parallel2.d
*** gas/testsuite/gas/bfin/parallel2.d 23 May 2005 06:43:52 -0000 1.4
--- gas/testsuite/gas/bfin/parallel2.d 16 Mar 2006 19:03:12 -0000
*************** Disassembly of section .text:
*** 71,79 ****
fc: c0 b9 00 00
100: 82 ce 52 07 R3=R2>>>0x16 \|\| R0=\[FP-12\] \|\| NOP;
104: d0 b9 00 00
! 108: 80 ce 7a 52 R1.L=R2.H<<0xf\(S\) \|\| R0=\[FP-8\] \|\| NOP;
10c: e0 b9 00 00
! 110: 80 ce f2 2b R5.H=R2.L>>>0x2 \|\| R0=\[FP-4\] \|\| NOP;
114: f0 b9 00 00
118: 00 ce 14 16 R3.L= ASHIFT R4.H BY R2.L \|\| R0=\[FP-100\] \|\| NOP;
11c: 70 b8 00 00
--- 71,79 ----
fc: c0 b9 00 00
100: 82 ce 52 07 R3=R2>>>0x16 \|\| R0=\[FP-12\] \|\| NOP;
104: d0 b9 00 00
! 108: 80 ce 7a 52 R1.L = R2.H << 0xf \(S\) \|\| R0=\[FP-8\] \|\| NOP;
10c: e0 b9 00 00
! 110: 80 ce f2 2b R5.H = R2.L >>> 0x2 \|\| R0=\[FP-4\] \|\| NOP;
114: f0 b9 00 00
118: 00 ce 14 16 R3.L= ASHIFT R4.H BY R2.L \|\| R0=\[FP-100\] \|\| NOP;
11c: 70 b8 00 00
*************** Disassembly of section .text:
*** 91,99 ****
14c: 10 b8 00 00
150: 03 ce 00 10 A1= ASHIFT A1 BY R0.L \|\| R0=\[FP-128\] \|\| NOP;
154: 00 b8 00 00
! 158: 80 ce 8a a3 R1.H=R2.L>>0xf \|\| R5=W\[P1--\] \(Z\) \|\| NOP;
15c: 8d 94 00 00
! 160: 80 ce 00 8e R7.L=R0.L<<0x0 \|\| R5=W\[P2\] \(Z\) \|\| NOP;
164: 15 95 00 00
168: 82 ce 0d 8b R5=R5>>0x1f \|\| R7=W\[P2\+\+\] \(Z\) \|\| NOP;
16c: 17 94 00 00
--- 91,99 ----
14c: 10 b8 00 00
150: 03 ce 00 10 A1= ASHIFT A1 BY R0.L \|\| R0=\[FP-128\] \|\| NOP;
154: 00 b8 00 00
! 158: 80 ce 8a a3 R1.H = R2.L >> 0xf \|\| R5=W\[P1--\] \(Z\) \|\| NOP;
15c: 8d 94 00 00
! 160: 80 ce 00 8e R7.L = R0.L << 0x0 \|\| R5=W\[P2\] \(Z\) \|\| NOP;
164: 15 95 00 00
168: 82 ce 0d 8b R5=R5>>0x1f \|\| R7=W\[P2\+\+\] \(Z\) \|\| NOP;
16c: 17 94 00 00
Index: gas/testsuite/gas/bfin/shift.d
===================================================================
RCS file: /cvsroot/gcc3/binutils/binutils-2.15/gas/testsuite/gas/bfin/shift.d,v
retrieving revision 1.6
diff -c -p -r1.6 shift.d
*** gas/testsuite/gas/bfin/shift.d 23 May 2005 06:43:52 -0000 1.6
--- gas/testsuite/gas/bfin/shift.d 16 Mar 2006 19:03:12 -0000
*************** Disassembly of section .text:
*** 21,28 ****
18: 83 c6 00 10 A1=A1<<0x0;
1c: 82 c6 fd 4e R7=R5<<0x1f\(S\);
20: 82 c6 52 07 R3=R2>>>0x16;
! 24: 80 c6 7a 52 R1.L=R2.H<<0xf\(S\);
! 28: 80 c6 f2 2b R5.H=R2.L>>>0x2;
2c: 00 4f R0<<=0x0;
2e: f9 4d R1>>>=0x1f;
30: 08 40 R0>>>=R1;
--- 21,28 ----
18: 83 c6 00 10 A1=A1<<0x0;
1c: 82 c6 fd 4e R7=R5<<0x1f\(S\);
20: 82 c6 52 07 R3=R2>>>0x16;
! 24: 80 c6 7a 52 R1.L = R2.H << 0xf \(S\);
! 28: 80 c6 f2 2b R5.H = R2.L >>> 0x2;
2c: 00 4f R0<<=0x0;
2e: f9 4d R1>>>=0x1f;
30: 08 40 R0>>>=R1;
*************** Disassembly of section .text:
*** 43,50 ****
5a: 6c 44 P4=P5<<2;
5c: f8 4e R0>>=0x1f;
5e: ff 4f R7<<=0x1f;
! 60: 80 c6 8a a3 R1.H=R2.L>>0xf;
! 64: 80 c6 00 8e R7.L=R0.L<<0x0;
68: 82 c6 0d 8b R5=R5>>0x1f;
6c: 82 c6 60 80 R0=R0<<0xc;
70: 83 c6 f8 41 A0=A0>>0x1;
--- 43,50 ----
5a: 6c 44 P4=P5<<2;
5c: f8 4e R0>>=0x1f;
5e: ff 4f R7<<=0x1f;
! 60: 80 c6 8a a3 R1.H = R2.L >> 0xf;
! 64: 80 c6 00 8e R7.L = R0.L << 0x0;
68: 82 c6 0d 8b R5=R5>>0x1f;
6c: 82 c6 60 80 R0=R0<<0xc;
70: 83 c6 f8 41 A0=A0>>0x1;
Index: gas/testsuite/gas/bfin/shift2.d
===================================================================
RCS file: /cvsroot/gcc3/binutils/binutils-2.15/gas/testsuite/gas/bfin/shift2.d,v
retrieving revision 1.4
diff -c -p -r1.4 shift2.d
*** gas/testsuite/gas/bfin/shift2.d 23 May 2005 06:43:52 -0000 1.4
--- gas/testsuite/gas/bfin/shift2.d 16 Mar 2006 19:03:12 -0000
*************** Disassembly of section .text:
*** 53,106 ****
5a: 05 4f R5<<=0x0;
5c: fd 4f R5<<=0x1f;
5e: 2d 4f R5<<=0x5;
! 60: 80 c6 00 00 R0.L=R0.L>>>0x0;
! 64: 80 c6 88 01 R0.L=R0.L>>>0xf;
! 68: 80 c6 00 10 R0.L=R0.H>>>0x0;
! 6c: 80 c6 88 11 R0.L=R0.H>>>0xf;
! 70: 80 c6 00 20 R0.H=R0.L>>>0x0;
! 74: 80 c6 88 21 R0.H=R0.L>>>0xf;
! 78: 80 c6 00 30 R0.H=R0.H>>>0x0;
! 7c: 80 c6 88 31 R0.H=R0.H>>>0xf;
! 80: 80 c6 01 00 R0.L=R1.L>>>0x0;
! 84: 80 c6 89 01 R0.L=R1.L>>>0xf;
! 88: 80 c6 01 10 R0.L=R1.H>>>0x0;
! 8c: 80 c6 89 11 R0.L=R1.H>>>0xf;
! 90: 80 c6 01 20 R0.H=R1.L>>>0x0;
! 94: 80 c6 89 21 R0.H=R1.L>>>0xf;
! 98: 80 c6 01 30 R0.H=R1.H>>>0x0;
! 9c: 80 c6 89 31 R0.H=R1.H>>>0xf;
! a0: 80 c6 07 00 R0.L=R7.L>>>0x0;
! a4: 80 c6 8e 03 R1.L=R6.L>>>0xf;
! a8: 80 c6 05 14 R2.L=R5.H>>>0x0;
! ac: 80 c6 8c 17 R3.L=R4.H>>>0xf;
! b0: 80 c6 03 28 R4.H=R3.L>>>0x0;
! b4: 80 c6 8a 2b R5.H=R2.L>>>0xf;
! b8: 80 c6 01 3c R6.H=R1.H>>>0x0;
! bc: 80 c6 88 3f R7.H=R0.H>>>0xf;
! c0: 80 c6 00 40 R0.L=R0.L<<0x0\(S\);
! c4: 80 c6 78 40 R0.L=R0.L<<0xf\(S\);
! c8: 80 c6 00 50 R0.L=R0.H<<0x0\(S\);
! cc: 80 c6 78 50 R0.L=R0.H<<0xf\(S\);
! d0: 80 c6 00 60 R0.H=R0.L<<0x0\(S\);
! d4: 80 c6 78 60 R0.H=R0.L<<0xf\(S\);
! d8: 80 c6 00 70 R0.H=R0.H<<0x0\(S\);
! dc: 80 c6 78 70 R0.H=R0.H<<0xf\(S\);
! e0: 80 c6 01 40 R0.L=R1.L<<0x0\(S\);
! e4: 80 c6 79 40 R0.L=R1.L<<0xf\(S\);
! e8: 80 c6 01 50 R0.L=R1.H<<0x0\(S\);
! ec: 80 c6 79 50 R0.L=R1.H<<0xf\(S\);
! f0: 80 c6 01 60 R0.H=R1.L<<0x0\(S\);
! f4: 80 c6 79 60 R0.H=R1.L<<0xf\(S\);
! f8: 80 c6 01 70 R0.H=R1.H<<0x0\(S\);
! fc: 80 c6 79 70 R0.H=R1.H<<0xf\(S\);
! 100: 80 c6 07 40 R0.L=R7.L<<0x0\(S\);
! 104: 80 c6 7e 42 R1.L=R6.L<<0xf\(S\);
! 108: 80 c6 05 54 R2.L=R5.H<<0x0\(S\);
! 10c: 80 c6 7c 56 R3.L=R4.H<<0xf\(S\);
! 110: 80 c6 03 68 R4.H=R3.L<<0x0\(S\);
! 114: 80 c6 7a 6a R5.H=R2.L<<0xf\(S\);
! 118: 80 c6 01 7c R6.H=R1.H<<0x0\(S\);
! 11c: 80 c6 78 7e R7.H=R0.H<<0xf\(S\);
120: 82 c6 00 00 R0=R0>>>0x0;
124: 82 c6 08 01 R0=R0>>>0x1f;
128: 82 c6 01 00 R0=R1>>>0x0;
--- 53,106 ----
5a: 05 4f R5<<=0x0;
5c: fd 4f R5<<=0x1f;
5e: 2d 4f R5<<=0x5;
! 60: 80 c6 00 00 R0.L = R0.L >>> 0x0;
! 64: 80 c6 88 01 R0.L = R0.L >>> 0xf;
! 68: 80 c6 00 10 R0.L = R0.H >>> 0x0;
! 6c: 80 c6 88 11 R0.L = R0.H >>> 0xf;
! 70: 80 c6 00 20 R0.H = R0.L >>> 0x0;
! 74: 80 c6 88 21 R0.H = R0.L >>> 0xf;
! 78: 80 c6 00 30 R0.H = R0.H >>> 0x0;
! 7c: 80 c6 88 31 R0.H = R0.H >>> 0xf;
! 80: 80 c6 01 00 R0.L = R1.L >>> 0x0;
! 84: 80 c6 89 01 R0.L = R1.L >>> 0xf;
! 88: 80 c6 01 10 R0.L = R1.H >>> 0x0;
! 8c: 80 c6 89 11 R0.L = R1.H >>> 0xf;
! 90: 80 c6 01 20 R0.H = R1.L >>> 0x0;
! 94: 80 c6 89 21 R0.H = R1.L >>> 0xf;
! 98: 80 c6 01 30 R0.H = R1.H >>> 0x0;
! 9c: 80 c6 89 31 R0.H = R1.H >>> 0xf;
! a0: 80 c6 07 00 R0.L = R7.L >>> 0x0;
! a4: 80 c6 8e 03 R1.L = R6.L >>> 0xf;
! a8: 80 c6 05 14 R2.L = R5.H >>> 0x0;
! ac: 80 c6 8c 17 R3.L = R4.H >>> 0xf;
! b0: 80 c6 03 28 R4.H = R3.L >>> 0x0;
! b4: 80 c6 8a 2b R5.H = R2.L >>> 0xf;
! b8: 80 c6 01 3c R6.H = R1.H >>> 0x0;
! bc: 80 c6 88 3f R7.H = R0.H >>> 0xf;
! c0: 80 c6 00 40 R0.L = R0.L << 0x0 \(S\);
! c4: 80 c6 78 40 R0.L = R0.L << 0xf \(S\);
! c8: 80 c6 00 50 R0.L = R0.H << 0x0 \(S\);
! cc: 80 c6 78 50 R0.L = R0.H << 0xf \(S\);
! d0: 80 c6 00 60 R0.H = R0.L << 0x0 \(S\);
! d4: 80 c6 78 60 R0.H = R0.L << 0xf \(S\);
! d8: 80 c6 00 70 R0.H = R0.H << 0x0 \(S\);
! dc: 80 c6 78 70 R0.H = R0.H << 0xf \(S\);
! e0: 80 c6 01 40 R0.L = R1.L << 0x0 \(S\);
! e4: 80 c6 79 40 R0.L = R1.L << 0xf \(S\);
! e8: 80 c6 01 50 R0.L = R1.H << 0x0 \(S\);
! ec: 80 c6 79 50 R0.L = R1.H << 0xf \(S\);
! f0: 80 c6 01 60 R0.H = R1.L << 0x0 \(S\);
! f4: 80 c6 79 60 R0.H = R1.L << 0xf \(S\);
! f8: 80 c6 01 70 R0.H = R1.H << 0x0 \(S\);
! fc: 80 c6 79 70 R0.H = R1.H << 0xf \(S\);
! 100: 80 c6 07 40 R0.L = R7.L << 0x0 \(S\);
! 104: 80 c6 7e 42 R1.L = R6.L << 0xf \(S\);
! 108: 80 c6 05 54 R2.L = R5.H << 0x0 \(S\);
! 10c: 80 c6 7c 56 R3.L = R4.H << 0xf \(S\);
! 110: 80 c6 03 68 R4.H = R3.L << 0x0 \(S\);
! 114: 80 c6 7a 6a R5.H = R2.L << 0xf \(S\);
! 118: 80 c6 01 7c R6.H = R1.H << 0x0 \(S\);
! 11c: 80 c6 78 7e R7.H = R0.H << 0xf \(S\);
120: 82 c6 00 00 R0=R0>>>0x0;
124: 82 c6 08 01 R0=R0>>>0x1f;
128: 82 c6 01 00 R0=R1>>>0x0;
*************** Disassembly of section .text:
*** 163,172 ****
1f6: 48 44 P0=P1<<2;
1f8: 8b 4e R3>>=0x11;
1fa: 8b 4f R3<<=0x11;
! 1fc: 80 c6 e0 87 R3.L=R0.L>>0x4;
! 200: 80 c6 e0 97 R3.L=R0.H>>0x4;
! 204: 80 c6 60 a6 R3.H=R0.L<<0xc;
! 208: 80 c6 70 b6 R3.H=R0.H<<0xe;
20c: 82 c6 e6 87 R3=R6>>0x4;
210: 82 c6 26 86 R3=R6<<0x4;
214: 83 c6 c8 41 A0=A0>>0x7;
--- 163,172 ----
1f6: 48 44 P0=P1<<2;
1f8: 8b 4e R3>>=0x11;
1fa: 8b 4f R3<<=0x11;
! 1fc: 80 c6 e0 87 R3.L = R0.L >> 0x4;
! 200: 80 c6 e0 97 R3.L = R0.H >> 0x4;
! 204: 80 c6 60 a6 R3.H = R0.L << 0xc;
! 208: 80 c6 70 b6 R3.H = R0.H << 0xe;
20c: 82 c6 e6 87 R3=R6>>0x4;
210: 82 c6 26 86 R3=R6<<0x4;
214: 83 c6 c8 41 A0=A0>>0x7;
*************** Disassembly of section .text:
*** 191,193 ****
--- 191,222 ----
25c: 02 c6 11 c8 R4= ROT R1 BY R2.L;
260: 03 c6 18 80 A0= ROT A0 BY R3.L;
264: 03 c6 38 90 A1= ROT A1 BY R7.L;
+ 268: 80 c6 01 80 R0.L = R1.L << 0x0;
+ 26c: 80 c6 09 80 R0.L = R1.L << 0x1;
+ 270: 80 c6 11 80 R0.L = R1.L << 0x2;
+ 274: 80 c6 21 80 R0.L = R1.L << 0x4;
+ 278: 80 c6 01 80 R0.L = R1.L << 0x0;
+ 27c: 80 c6 f9 81 R0.L = R1.L >> 0x1;
+ 280: 80 c6 f1 81 R0.L = R1.L >> 0x2;
+ 284: 80 c6 e1 81 R0.L = R1.L >> 0x4;
+ 288: 80 c6 f9 01 R0.L = R1.L >>> 0x1;
+ 28c: 80 c6 f1 01 R0.L = R1.L >>> 0x2;
+ 290: 80 c6 e1 01 R0.L = R1.L >>> 0x4;
+ 294: 80 c6 01 90 R0.L = R1.H << 0x0;
+ 298: 80 c6 09 90 R0.L = R1.H << 0x1;
+ 29c: 80 c6 11 90 R0.L = R1.H << 0x2;
+ 2a0: 80 c6 21 90 R0.L = R1.H << 0x4;
+ 2a4: 80 c6 01 90 R0.L = R1.H << 0x0;
+ 2a8: 80 c6 f9 91 R0.L = R1.H >> 0x1;
+ 2ac: 80 c6 f1 91 R0.L = R1.H >> 0x2;
+ 2b0: 80 c6 e1 91 R0.L = R1.H >> 0x4;
+ 2b4: 80 c6 f9 11 R0.L = R1.H >>> 0x1;
+ 2b8: 80 c6 f1 11 R0.L = R1.H >>> 0x2;
+ 2bc: 80 c6 e1 11 R0.L = R1.H >>> 0x4;
+ 2c0: 80 c6 01 50 R0.L = R1.H << 0x0 \(S\);
+ 2c4: 80 c6 09 50 R0.L = R1.H << 0x1 \(S\);
+ 2c8: 80 c6 11 50 R0.L = R1.H << 0x2 \(S\);
+ 2cc: 80 c6 21 50 R0.L = R1.H << 0x4 \(S\);
+ 2d0: 80 c6 f9 51 R0.L = R1.H >>> 0x1 \(S\);
+ 2d4: 80 c6 f1 51 R0.L = R1.H >>> 0x2 \(S\);
+ 2d8: 80 c6 e1 51 R0.L = R1.H >>> 0x4 \(S\);
Index: gas/testsuite/gas/bfin/shift2.s
===================================================================
RCS file: /cvsroot/gcc3/binutils/binutils-2.15/gas/testsuite/gas/bfin/shift2.s,v
retrieving revision 1.1
diff -c -p -r1.1 shift2.s
*** gas/testsuite/gas/bfin/shift2.s 15 Dec 2004 21:20:06 -0000 1.1
--- gas/testsuite/gas/bfin/shift2.s 16 Mar 2006 19:03:13 -0000
*************** r4 = rot r1 by r2.l ;
*** 256,258 ****
--- 256,290 ----
a0 = rot a0 by r3.l ;
a1 = rot a1 by r7.l ;
+ r0.l = r1.l << 0;
+ r0.l = r1.l << 1;
+ r0.l = r1.l << 2;
+ r0.l = r1.l << 4;
+ r0.l = r1.l >> 0;
+ r0.l = r1.l >> 1;
+ r0.l = r1.l >> 2;
+ r0.l = r1.l >> 4;
+ r0.l = r1.l >>> 1;
+ r0.l = r1.l >>> 2;
+ r0.l = r1.l >>> 4;
+
+ r0.l = r1.h << 0;
+ r0.l = r1.h << 1;
+ r0.l = r1.h << 2;
+ r0.l = r1.h << 4;
+ r0.l = r1.h >> 0;
+ r0.l = r1.h >> 1;
+ r0.l = r1.h >> 2;
+ r0.l = r1.h >> 4;
+ r0.l = r1.h >>> 1;
+ r0.l = r1.h >>> 2;
+ r0.l = r1.h >>> 4;
+
+ r0.l = r1.h << 0 (S);
+ r0.l = r1.h << 1 (S);
+ r0.l = r1.h << 2 (S);
+ r0.l = r1.h << 4 (S);
+ r0.l = r1.h >>> 1 (S);
+ r0.l = r1.h >>> 2 (S);
+ r0.l = r1.h >>> 4 (S);
+
Index: opcodes/bfin-dis.c
===================================================================
RCS file: /cvsroot/gcc3/binutils/binutils-2.15/opcodes/bfin-dis.c,v
retrieving revision 1.29
diff -c -p -r1.29 bfin-dis.c
*** opcodes/bfin-dis.c 24 Oct 2005 03:58:30 -0000 1.29
--- opcodes/bfin-dis.c 16 Mar 2006 19:03:14 -0000
*************** decode_dsp32shiftimm_0 (TIword iw0, TIwo
*** 4034,4163 ****
int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
! if (HLs == 0 && sop == 0 && sopcde == 0)
{
! OUTS (outf, dregs_lo (dst0));
! OUTS (outf, "=");
! OUTS (outf, dregs_lo (src1));
! OUTS (outf, ">>>");
! OUTS (outf, uimm4 (newimmag));
! }
! else if (HLs == 1 && sop == 0 && sopcde == 0)
! {
! OUTS (outf, dregs_lo (dst0));
! OUTS (outf, "=");
! OUTS (outf, dregs_hi (src1));
! OUTS (outf, ">>>");
! OUTS (outf, uimm4 (newimmag));
! }
! else if (HLs == 2 && sop == 0 && sopcde == 0)
! {
! OUTS (outf, dregs_hi (dst0));
! OUTS (outf, "=");
! OUTS (outf, dregs_lo (src1));
! OUTS (outf, ">>>");
! OUTS (outf, uimm4 (newimmag));
! }
! else if (HLs == 3 && sop == 0 && sopcde == 0)
! {
! OUTS (outf, dregs_hi (dst0));
! OUTS (outf, "=");
! OUTS (outf, dregs_hi (src1));
! OUTS (outf, ">>>");
OUTS (outf, uimm4 (newimmag));
}
! else if (HLs == 0 && sop == 1 && sopcde == 0)
{
! OUTS (outf, dregs_lo (dst0));
! OUTS (outf, "=");
! OUTS (outf, dregs_lo (src1));
! OUTS (outf, "<<");
! OUTS (outf, uimm4 (immag));
! OUTS (outf, "(S)");
! }
! else if (HLs == 1 && sop == 1 && sopcde == 0)
! {
! OUTS (outf, dregs_lo (dst0));
! OUTS (outf, "=");
! OUTS (outf, dregs_hi (src1));
! OUTS (outf, "<<");
OUTS (outf, uimm4 (immag));
! OUTS (outf, "(S)");
! }
! else if (HLs == 2 && sop == 1 && sopcde == 0)
! {
! OUTS (outf, dregs_hi (dst0));
! OUTS (outf, "=");
! OUTS (outf, dregs_lo (src1));
! OUTS (outf, "<<");
! OUTS (outf, uimm4 (immag));
! OUTS (outf, "(S)");
}
! else if (HLs == 3 && sop == 1 && sopcde == 0)
{
! OUTS (outf, dregs_hi (dst0));
! OUTS (outf, "=");
! OUTS (outf, dregs_hi (src1));
! OUTS (outf, "<<");
! OUTS (outf, uimm4 (immag));
! OUTS (outf, "(S)");
! }
! else if (HLs == 0 && sop == 2 && sopcde == 0 && bit8 == 0)
! {
! OUTS (outf, dregs_lo (dst0));
! OUTS (outf, "=");
! OUTS (outf, dregs_lo (src1));
! OUTS (outf, "<<");
! OUTS (outf, uimm4 (immag));
! }
! else if (HLs == 0 && sop == 2 && sopcde == 0 && bit8 == 1)
! {
! OUTS (outf, dregs_lo (dst0));
! OUTS (outf, "=");
! OUTS (outf, dregs_lo (src1));
! OUTS (outf, ">>");
! OUTS (outf, uimm4 (newimmag));
! }
! else if (HLs == 1 && sop == 2 && sopcde == 0)
! {
! OUTS (outf, dregs_lo (dst0));
! OUTS (outf, "=");
! OUTS (outf, dregs_hi (src1));
! OUTS (outf, ">>");
! OUTS (outf, uimm4 (newimmag));
! }
! else if (HLs == 2 && sop == 2 && sopcde == 0 && bit8 == 1)
! {
! OUTS (outf, dregs_hi (dst0));
! OUTS (outf, "=");
! OUTS (outf, dregs_lo (src1));
! OUTS (outf, ">>");
OUTS (outf, uimm4 (newimmag));
}
! else if (HLs == 2 && sop == 2 && sopcde == 0 && bit8 == 0)
{
! OUTS (outf, dregs_hi (dst0));
! OUTS (outf, "=");
! OUTS (outf, dregs_lo (src1));
! OUTS (outf, "<<");
OUTS (outf, uimm4 (immag));
}
! else if (HLs == 3 && sop == 2 && sopcde == 0 && bit8 == 1)
{
! OUTS (outf, dregs_hi (dst0));
! OUTS (outf, "=");
! OUTS (outf, dregs_hi (src1));
! OUTS (outf, ">>");
OUTS (outf, uimm4 (newimmag));
}
- else if (HLs == 3 && sop == 2 && sopcde == 0 && bit8 == 0)
- {
- OUTS (outf, dregs_hi (dst0));
- OUTS (outf, "=");
- OUTS (outf, dregs_hi (src1));
- OUTS (outf, "<<");
- OUTS (outf, uimm4 (immag));
- }
else if (sop == 2 && sopcde == 3 && HLs == 1)
{
OUTS (outf, "A1= ROT A1 BY ");
--- 4034,4081 ----
int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
! if (sop == 0 && sopcde == 0)
{
! OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
! OUTS (outf, " = ");
! OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
! OUTS (outf, " >>> ");
OUTS (outf, uimm4 (newimmag));
}
! else if (sop == 1 && sopcde == 0 && bit8 == 0)
{
! OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
! OUTS (outf, " = ");
! OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
! OUTS (outf, " << ");
OUTS (outf, uimm4 (immag));
! OUTS (outf, " (S)");
}
! else if (sop == 1 && sopcde == 0 && bit8 == 1)
{
! OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
! OUTS (outf, " = ");
! OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
! OUTS (outf, " >>> ");
OUTS (outf, uimm4 (newimmag));
+ OUTS (outf, " (S)");
}
! else if (sop == 2 && sopcde == 0 && bit8 == 0)
{
! OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
! OUTS (outf, " = ");
! OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
! OUTS (outf, " << ");
OUTS (outf, uimm4 (immag));
}
! else if (sop == 2 && sopcde == 0 && bit8 == 1)
{
! OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
! OUTS (outf, " = ");
! OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
! OUTS (outf, " >> ");
OUTS (outf, uimm4 (newimmag));
}
else if (sop == 2 && sopcde == 3 && HLs == 1)
{
OUTS (outf, "A1= ROT A1 BY ");