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[PATCH, ARM] Allow Neon syntax for overlapping VFP instructions


Hi,

This patch allows the Neon syntax to be used in vanilla VFP mode for the several VFP instructions which overlap new Neon instructions, and which now disassemble in the latter form. Failure to allow the same syntax for assembly and disassembly will probably cause undue confusion. Eventually, the Neon-style syntax will be implemented for all VFP instructions, so this is a (small) step in that direction.

The fldmx/fstmx instructions can't be represented in the Neon syntax, so I've made them use the old VFP syntax instead. Those variants are deprecated in armv6, but I think disassembling them differently is still a sensible thing to do, in the interest of fully supporting the older architectures. (The previous Neon patches made fldmd/fldmx/fstmd/fstmx disassemble as vldm/vldm/vstm/vstm respectively).

Tested with "make check" with cross to arm-none-eabi, with a new test case added. OK to apply on the CSL branch? Mainline?

Cheers,

Julian

ChangeLog (gas):

    * config/tc-arm.c (parse_vfp_reg_list): Improve register bounds
    checking.
    (do_neon_mov): Enable several VMOV variants for VFP. Add suitable
    architecture version checks.
    (insns): Allow overlapping instructions to be used in VFP mode.

ChangeLog (gas/testsuite):

    * gas/arm/vfp-neon-overlap.s: New test. Overlapping VFP/Neon
    instructions.
    * gas/arm/vfp-neon-overlap.d: Expected output of above.
    * gas/arm/vfp1xD.d: Test for fldmx/fstmx.
    * gas/arm/vfp1xD_t2.d: Likewise.
    * gas/arm/vfpv3-32drs.d: Likewise.

ChangeLog (opcodes):

    * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
    vldm/vstm.
diff -Nurp ../../binutils-csl-fpconst/src/gas/config/tc-arm.c ./gas/config/tc-arm.c
--- ../../binutils-csl-fpconst/src/gas/config/tc-arm.c	2006-04-24 22:51:00.000000000 +0100
+++ ./gas/config/tc-arm.c	2006-04-26 00:58:31.000000000 +0100
@@ -1553,6 +1553,15 @@ parse_vfp_reg_list (char **str, unsigned
     
     case REGLIST_VFP_D:
       regtype = REG_TYPE_VFD;
+      break;
+    
+    case REGLIST_NEON_D:
+      regtype = REG_TYPE_NDQ;
+      break;
+    }
+
+  if (etype != REGLIST_VFP_S)
+    {
       /* VFPv3 allows 32 D registers.  */
       if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
         {
@@ -1566,12 +1575,6 @@ parse_vfp_reg_list (char **str, unsigned
         }
       else
         max_regs = 16;
-      break;
-    
-    case REGLIST_NEON_D:
-      regtype = REG_TYPE_NDQ;
-      max_regs = 32;
-      break;
     }
 
   base_reg = max_regs;
@@ -1588,6 +1591,12 @@ parse_vfp_reg_list (char **str, unsigned
 	  return FAIL;
 	}
  
+      if (new_base >= max_regs)
+        {
+          first_error (_("register out of range in list"));
+          return FAIL;
+        }
+ 
       /* Note: a value of 2 * n is returned for the register Q<n>.  */
       if (regtype == REG_TYPE_NQ)
         {
@@ -1626,6 +1635,12 @@ parse_vfp_reg_list (char **str, unsigned
 	      return FAIL;
 	    }
 
+          if (high_range >= max_regs)
+            {
+              first_error (_("register out of range in list"));
+              return FAIL;
+            }
+
           if (regtype == REG_TYPE_NQ)
             high_range = high_range + 1;
 
@@ -11304,6 +11319,9 @@ do_neon_dup (void)
    
    All the encoded bits are hardcoded by this function.
    
+   Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
+   Cases 5, 7 may be used with VFPv2 and above.
+   
    FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
    can specify a type where it doesn't make sense to, and is ignored).
 */
@@ -11314,6 +11332,7 @@ do_neon_mov (void)
   int nargs = inst.operands[0].present + inst.operands[1].present
               + inst.operands[2].present;
   unsigned save_cond = thumb_mode ? 0xe0000000 : inst.instruction & 0xf0000000;
+  const char *vfp_vers = "selected FPU does not support instruction";
 
   switch (nargs)
     {
@@ -11329,6 +11348,10 @@ do_neon_mov (void)
           unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
           unsigned abcdebits = 0;
 
+          constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
+                      _(vfp_vers));
+          constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
+                      && et.size != 32, _(vfp_vers));
           constraint (et.type == NT_invtype, _("bad type for scalar"));
           constraint (x >= 64 / et.size, _("scalar index out of range"));
 
@@ -11362,6 +11385,10 @@ do_neon_mov (void)
               unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
               unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
 
+              constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
+                          _(vfp_vers));
+              constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
+                          && et.size != 32, _(vfp_vers));
               constraint (et.type == NT_invtype, _("bad type for scalar"));
               constraint (x >= 64 / et.size, _("scalar index out of range"));
 
@@ -11412,6 +11439,9 @@ do_neon_mov (void)
     
     case 3:
       /* Cases 5, 7.  */
+      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
+                  _(vfp_vers));
+
       if (inst.operands[0].regisimm)
         {
           /* Case 5.  */
@@ -14138,7 +14168,16 @@ static const struct asm_opcode insns[] =
  nUF(vcvtq,     vcvt,    3, (RNQ,  RNQ,  oI32b), neon_cvt),
 
   /* One register and an immediate value. All encoding special-cased!  */
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &fpu_vfp_ext_v1
+#undef ARM_VARIANT
+#define ARM_VARIANT &fpu_vfp_ext_v1
  NCE(vmov,      0,       1, (VMOV),             neon_mov),
+
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &fpu_neon_ext_v1
+#undef ARM_VARIANT
+#define ARM_VARIANT &fpu_neon_ext_v1
  NCE(vmovq,     0,       1, (VMOV),             neon_mov),
  nUF(vmvn,      vmvn,    2, (RNDQ, RNDQ_IMVNb), neon_mvn),
  nUF(vmvnq,     vmvn,    2, (RNQ,  RNDQ_IMVNb), neon_mvn),
@@ -14233,9 +14272,9 @@ static const struct asm_opcode insns[] =
  NUF(vtbx,      1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
 
 #undef THUMB_VARIANT
-#define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
+#define THUMB_VARIANT &fpu_vfp_ext_v1xd
 #undef ARM_VARIANT
-#define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
+#define ARM_VARIANT &fpu_vfp_ext_v1xd
 
   /* Load/store instructions. Available in Neon or VFPv3.  */
  NCE(vldm,      c900b00, 2, (RRw, NRDLST),    neon_ldm_stm),
@@ -14247,6 +14286,11 @@ static const struct asm_opcode insns[] =
  NCE(vldr,      d100b00, 2, (RND, ADDR),      neon_ldr_str),
  NCE(vstr,      d000b00, 2, (RND, ADDR),      neon_ldr_str),
 
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
+#undef ARM_VARIANT
+#define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
+
   /* Neon element/structure load/store.  */
  nUF(vld1,      vld1,    2, (NSTRLST, ADDR),  neon_ldx_stx),
  nUF(vst1,      vst1,    2, (NSTRLST, ADDR),  neon_ldx_stx),
Binary files ../../binutils-csl-fpconst/src/gas/testsuite/gas/arm/neon-ldst-rm.o and ./gas/testsuite/gas/arm/neon-ldst-rm.o differ
diff -Nurp ../../binutils-csl-fpconst/src/gas/testsuite/gas/arm/vfp-neon-overlap.d ./gas/testsuite/gas/arm/vfp-neon-overlap.d
--- ../../binutils-csl-fpconst/src/gas/testsuite/gas/arm/vfp-neon-overlap.d	1970-01-01 01:00:00.000000000 +0100
+++ ./gas/testsuite/gas/arm/vfp-neon-overlap.d	2006-04-25 23:05:23.000000000 +0100
@@ -0,0 +1,35 @@
+# name: VFP/Neon overlapping instructions
+# as: -mfpu=vfp
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> ec410b10 	vmov	d0, r0, r1
+0[0-9a-f]+ <[^>]+> ec410b10 	vmov	d0, r0, r1
+0[0-9a-f]+ <[^>]+> ec510b10 	vmov	r0, r1, d0
+0[0-9a-f]+ <[^>]+> ec510b10 	vmov	r0, r1, d0
+0[0-9a-f]+ <[^>]+> ec900b09 	fldmiax	r0, {d0-d3}
+0[0-9a-f]+ <[^>]+> ed300b09 	fldmdbx	r0!, {d0-d3}
+0[0-9a-f]+ <[^>]+> ec800b09 	fstmiax	r0, {d0-d3}
+0[0-9a-f]+ <[^>]+> ed200b09 	fstmdbx	r0!, {d0-d3}
+0[0-9a-f]+ <[^>]+> ed900b00 	vldr	d0, \[r0\]
+0[0-9a-f]+ <[^>]+> ed900b00 	vldr	d0, \[r0\]
+0[0-9a-f]+ <[^>]+> ed800b00 	vstr	d0, \[r0\]
+0[0-9a-f]+ <[^>]+> ed800b00 	vstr	d0, \[r0\]
+0[0-9a-f]+ <[^>]+> ec900b08 	vldmia	r0, {d0-d3}
+0[0-9a-f]+ <[^>]+> ec900b08 	vldmia	r0, {d0-d3}
+0[0-9a-f]+ <[^>]+> ed300b08 	vldmdb	r0!, {d0-d3}
+0[0-9a-f]+ <[^>]+> ed300b08 	vldmdb	r0!, {d0-d3}
+0[0-9a-f]+ <[^>]+> ec800b08 	vstmia	r0, {d0-d3}
+0[0-9a-f]+ <[^>]+> ec800b08 	vstmia	r0, {d0-d3}
+0[0-9a-f]+ <[^>]+> ed200b08 	vstmdb	r0!, {d0-d3}
+0[0-9a-f]+ <[^>]+> ed200b08 	vstmdb	r0!, {d0-d3}
+0[0-9a-f]+ <[^>]+> ee300b10 	vmov\.32	r0, d0\[1\]
+0[0-9a-f]+ <[^>]+> ee300b10 	vmov\.32	r0, d0\[1\]
+0[0-9a-f]+ <[^>]+> ee100b10 	vmov\.32	r0, d0\[0\]
+0[0-9a-f]+ <[^>]+> ee100b10 	vmov\.32	r0, d0\[0\]
+0[0-9a-f]+ <[^>]+> ee200b10 	vmov\.32	d0\[1\], r0
+0[0-9a-f]+ <[^>]+> ee200b10 	vmov\.32	d0\[1\], r0
+0[0-9a-f]+ <[^>]+> ee000b10 	vmov\.32	d0\[0\], r0
+0[0-9a-f]+ <[^>]+> ee000b10 	vmov\.32	d0\[0\], r0
Binary files ../../binutils-csl-fpconst/src/gas/testsuite/gas/arm/vfp-neon-overlap.o and ./gas/testsuite/gas/arm/vfp-neon-overlap.o differ
diff -Nurp ../../binutils-csl-fpconst/src/gas/testsuite/gas/arm/vfp-neon-overlap.s ./gas/testsuite/gas/arm/vfp-neon-overlap.s
--- ../../binutils-csl-fpconst/src/gas/testsuite/gas/arm/vfp-neon-overlap.s	1970-01-01 01:00:00.000000000 +0100
+++ ./gas/testsuite/gas/arm/vfp-neon-overlap.s	2006-04-25 22:48:59.000000000 +0100
@@ -0,0 +1,41 @@
+@ VFP/Neon overlapping instructions
+
+	.arm
+	.text
+	.syntax unified
+
+	fmdrr d0,r0,r1
+        vmov d0,r0,r1
+        fmrrd r0,r1,d0
+        vmov r0,r1,d0
+
+	@ the 'x' versions should disassemble as VFP instructions, because
+        @ they can't be represented in Neon syntax.
+
+	fldmiax r0,{d0-d3}
+        fldmdbx r0!,{d0-d3}
+        fstmiax r0,{d0-d3}
+        fstmdbx r0!,{d0-d3}
+
+	fldd d0,[r0]
+        vldr d0,[r0]
+        fstd d0,[r0]
+        vstr d0,[r0]
+
+	fldmiad r0,{d0-d3}
+        vldmia r0,{d0-d3}
+        fldmdbd r0!,{d0-d3}
+        vldmdb r0!,{d0-d3}
+        fstmiad r0,{d0-d3}
+        vstmia r0,{d0-d3}
+        fstmdbd r0!,{d0-d3}
+        vstmdb r0!,{d0-d3}
+
+	fmrdh r0,d0
+        vmov.32 r0,d0[1]
+        fmrdl r0,d0
+        vmov.32 r0,d0[0]
+	fmdhr d0,r0
+        vmov.32 d0[1],r0
+        fmdlr d0,r0
+        vmov.32 d0[0],r0
diff -Nurp ../../binutils-csl-fpconst/src/gas/testsuite/gas/arm/vfp1xD.d ./gas/testsuite/gas/arm/vfp1xD.d
--- ../../binutils-csl-fpconst/src/gas/testsuite/gas/arm/vfp1xD.d	2006-04-03 14:35:44.000000000 +0100
+++ ./gas/testsuite/gas/arm/vfp1xD.d	2006-04-26 00:06:23.000000000 +0100
@@ -33,24 +33,24 @@ Disassembly of section .text:
 0+05c <[^>]*> ecb00a01 	fldmias	r0!, {s0}
 0+060 <[^>]*> ed300a01 	fldmdbs	r0!, {s0}
 0+064 <[^>]*> ed300a01 	fldmdbs	r0!, {s0}
-0+068 <[^>]*> ec900b03 	vldmia	r0, {d0}
-0+06c <[^>]*> ec900b03 	vldmia	r0, {d0}
-0+070 <[^>]*> ecb00b03 	vldmia	r0!, {d0}
-0+074 <[^>]*> ecb00b03 	vldmia	r0!, {d0}
-0+078 <[^>]*> ed300b03 	vldmdb	r0!, {d0}
-0+07c <[^>]*> ed300b03 	vldmdb	r0!, {d0}
+0+068 <[^>]*> ec900b03 	fldmiax	r0, {d0}
+0+06c <[^>]*> ec900b03 	fldmiax	r0, {d0}
+0+070 <[^>]*> ecb00b03 	fldmiax	r0!, {d0}
+0+074 <[^>]*> ecb00b03 	fldmiax	r0!, {d0}
+0+078 <[^>]*> ed300b03 	fldmdbx	r0!, {d0}
+0+07c <[^>]*> ed300b03 	fldmdbx	r0!, {d0}
 0+080 <[^>]*> ec800a01 	fstmias	r0, {s0}
 0+084 <[^>]*> ec800a01 	fstmias	r0, {s0}
 0+088 <[^>]*> eca00a01 	fstmias	r0!, {s0}
 0+08c <[^>]*> eca00a01 	fstmias	r0!, {s0}
 0+090 <[^>]*> ed200a01 	fstmdbs	r0!, {s0}
 0+094 <[^>]*> ed200a01 	fstmdbs	r0!, {s0}
-0+098 <[^>]*> ec800b03 	vstmia	r0, {d0}
-0+09c <[^>]*> ec800b03 	vstmia	r0, {d0}
-0+0a0 <[^>]*> eca00b03 	vstmia	r0!, {d0}
-0+0a4 <[^>]*> eca00b03 	vstmia	r0!, {d0}
-0+0a8 <[^>]*> ed200b03 	vstmdb	r0!, {d0}
-0+0ac <[^>]*> ed200b03 	vstmdb	r0!, {d0}
+0+098 <[^>]*> ec800b03 	fstmiax	r0, {d0}
+0+09c <[^>]*> ec800b03 	fstmiax	r0, {d0}
+0+0a0 <[^>]*> eca00b03 	fstmiax	r0!, {d0}
+0+0a4 <[^>]*> eca00b03 	fstmiax	r0!, {d0}
+0+0a8 <[^>]*> ed200b03 	fstmdbx	r0!, {d0}
+0+0ac <[^>]*> ed200b03 	fstmdbx	r0!, {d0}
 0+0b0 <[^>]*> eeb80ac0 	fsitos	s0, s0
 0+0b4 <[^>]*> eeb80a40 	fuitos	s0, s0
 0+0b8 <[^>]*> eebd0a40 	ftosis	s0, s0
@@ -142,17 +142,17 @@ Disassembly of section .text:
 0+210 <[^>]*> ec90fa02 	fldmias	r0, {s30-s31}
 0+214 <[^>]*> ec910a01 	fldmias	r1, {s0}
 0+218 <[^>]*> ec9e0a01 	fldmias	lr, {s0}
-0+21c <[^>]*> ec801b03 	vstmia	r0, {d1}
-0+220 <[^>]*> ec802b03 	vstmia	r0, {d2}
-0+224 <[^>]*> ec80fb03 	vstmia	r0, {d15}
-0+228 <[^>]*> ec800b05 	vstmia	r0, {d0-d1}
-0+22c <[^>]*> ec800b07 	vstmia	r0, {d0-d2}
-0+230 <[^>]*> ec800b21 	vstmia	r0, {d0-d15}
-0+234 <[^>]*> ec801b1f 	vstmia	r0, {d1-d15}
-0+238 <[^>]*> ec802b1d 	vstmia	r0, {d2-d15}
-0+23c <[^>]*> ec80eb05 	vstmia	r0, {d14-d15}
-0+240 <[^>]*> ec810b03 	vstmia	r1, {d0}
-0+244 <[^>]*> ec8e0b03 	vstmia	lr, {d0}
+0+21c <[^>]*> ec801b03 	fstmiax	r0, {d1}
+0+220 <[^>]*> ec802b03 	fstmiax	r0, {d2}
+0+224 <[^>]*> ec80fb03 	fstmiax	r0, {d15}
+0+228 <[^>]*> ec800b05 	fstmiax	r0, {d0-d1}
+0+22c <[^>]*> ec800b07 	fstmiax	r0, {d0-d2}
+0+230 <[^>]*> ec800b21 	fstmiax	r0, {d0-d15}
+0+234 <[^>]*> ec801b1f 	fstmiax	r0, {d1-d15}
+0+238 <[^>]*> ec802b1d 	fstmiax	r0, {d2-d15}
+0+23c <[^>]*> ec80eb05 	fstmiax	r0, {d14-d15}
+0+240 <[^>]*> ec810b03 	fstmiax	r1, {d0}
+0+244 <[^>]*> ec8e0b03 	fstmiax	lr, {d0}
 0+248 <[^>]*> eeb50a40 	fcmpzs	s0
 0+24c <[^>]*> eef50a40 	fcmpzs	s1
 0+250 <[^>]*> eeb51a40 	fcmpzs	s2
@@ -211,24 +211,24 @@ Disassembly of section .text:
 0+324 <[^>]*> 0cf42a01 	fldmiaseq	r4!, {s5}
 0+328 <[^>]*> 0d352a01 	fldmdbseq	r5!, {s4}
 0+32c <[^>]*> 0d761a01 	fldmdbseq	r6!, {s3}
-0+330 <[^>]*> 0c971b03 	vldmiaeq	r7, {d1}
-0+334 <[^>]*> 0c982b03 	vldmiaeq	r8, {d2}
-0+338 <[^>]*> 0cb93b03 	vldmiaeq	r9!, {d3}
-0+33c <[^>]*> 0cba4b03 	vldmiaeq	sl!, {d4}
-0+340 <[^>]*> 0d3b5b03 	vldmdbeq	fp!, {d5}
-0+344 <[^>]*> 0d3c6b03 	vldmdbeq	ip!, {d6}
+0+330 <[^>]*> 0c971b03 	fldmiaxeq	r7, {d1}
+0+334 <[^>]*> 0c982b03 	fldmiaxeq	r8, {d2}
+0+338 <[^>]*> 0cb93b03 	fldmiaxeq	r9!, {d3}
+0+33c <[^>]*> 0cba4b03 	fldmiaxeq	sl!, {d4}
+0+340 <[^>]*> 0d3b5b03 	fldmdbxeq	fp!, {d5}
+0+344 <[^>]*> 0d3c6b03 	fldmdbxeq	ip!, {d6}
 0+348 <[^>]*> 0c8d1a01 	fstmiaseq	sp, {s2}
 0+34c <[^>]*> 0cce0a01 	fstmiaseq	lr, {s1}
 0+350 <[^>]*> 0ce1fa01 	fstmiaseq	r1!, {s31}
 0+354 <[^>]*> 0ca2fa01 	fstmiaseq	r2!, {s30}
 0+358 <[^>]*> 0d63ea01 	fstmdbseq	r3!, {s29}
 0+35c <[^>]*> 0d24ea01 	fstmdbseq	r4!, {s28}
-0+360 <[^>]*> 0c857b03 	vstmiaeq	r5, {d7}
-0+364 <[^>]*> 0c868b03 	vstmiaeq	r6, {d8}
-0+368 <[^>]*> 0ca79b03 	vstmiaeq	r7!, {d9}
-0+36c <[^>]*> 0ca8ab03 	vstmiaeq	r8!, {d10}
-0+370 <[^>]*> 0d29bb03 	vstmdbeq	r9!, {d11}
-0+374 <[^>]*> 0d2acb03 	vstmdbeq	sl!, {d12}
+0+360 <[^>]*> 0c857b03 	fstmiaxeq	r5, {d7}
+0+364 <[^>]*> 0c868b03 	fstmiaxeq	r6, {d8}
+0+368 <[^>]*> 0ca79b03 	fstmiaxeq	r7!, {d9}
+0+36c <[^>]*> 0ca8ab03 	fstmiaxeq	r8!, {d10}
+0+370 <[^>]*> 0d29bb03 	fstmdbxeq	r9!, {d11}
+0+374 <[^>]*> 0d2acb03 	fstmdbxeq	sl!, {d12}
 0+378 <[^>]*> 0ef8dac3 	fsitoseq	s27, s6
 0+37c <[^>]*> 0efdca62 	ftosiseq	s25, s5
 0+380 <[^>]*> 0efdbac2 	ftosizseq	s23, s4
diff -Nurp ../../binutils-csl-fpconst/src/gas/testsuite/gas/arm/vfp1xD_t2.d ./gas/testsuite/gas/arm/vfp1xD_t2.d
--- ../../binutils-csl-fpconst/src/gas/testsuite/gas/arm/vfp1xD_t2.d	2006-04-03 14:35:44.000000000 +0100
+++ ./gas/testsuite/gas/arm/vfp1xD_t2.d	2006-04-26 00:10:23.000000000 +0100
@@ -33,24 +33,24 @@ Disassembly of section .text:
 0+05c <[^>]*> ecb0 0a01 	fldmias	r0!, {s0}
 0+060 <[^>]*> ed30 0a01 	fldmdbs	r0!, {s0}
 0+064 <[^>]*> ed30 0a01 	fldmdbs	r0!, {s0}
-0+068 <[^>]*> ec90 0b03 	vldmia	r0, {d0}
-0+06c <[^>]*> ec90 0b03 	vldmia	r0, {d0}
-0+070 <[^>]*> ecb0 0b03 	vldmia	r0!, {d0}
-0+074 <[^>]*> ecb0 0b03 	vldmia	r0!, {d0}
-0+078 <[^>]*> ed30 0b03 	vldmdb	r0!, {d0}
-0+07c <[^>]*> ed30 0b03 	vldmdb	r0!, {d0}
+0+068 <[^>]*> ec90 0b03 	fldmiax	r0, {d0}
+0+06c <[^>]*> ec90 0b03 	fldmiax	r0, {d0}
+0+070 <[^>]*> ecb0 0b03 	fldmiax	r0!, {d0}
+0+074 <[^>]*> ecb0 0b03 	fldmiax	r0!, {d0}
+0+078 <[^>]*> ed30 0b03 	fldmdbx	r0!, {d0}
+0+07c <[^>]*> ed30 0b03 	fldmdbx	r0!, {d0}
 0+080 <[^>]*> ec80 0a01 	fstmias	r0, {s0}
 0+084 <[^>]*> ec80 0a01 	fstmias	r0, {s0}
 0+088 <[^>]*> eca0 0a01 	fstmias	r0!, {s0}
 0+08c <[^>]*> eca0 0a01 	fstmias	r0!, {s0}
 0+090 <[^>]*> ed20 0a01 	fstmdbs	r0!, {s0}
 0+094 <[^>]*> ed20 0a01 	fstmdbs	r0!, {s0}
-0+098 <[^>]*> ec80 0b03 	vstmia	r0, {d0}
-0+09c <[^>]*> ec80 0b03 	vstmia	r0, {d0}
-0+0a0 <[^>]*> eca0 0b03 	vstmia	r0!, {d0}
-0+0a4 <[^>]*> eca0 0b03 	vstmia	r0!, {d0}
-0+0a8 <[^>]*> ed20 0b03 	vstmdb	r0!, {d0}
-0+0ac <[^>]*> ed20 0b03 	vstmdb	r0!, {d0}
+0+098 <[^>]*> ec80 0b03 	fstmiax	r0, {d0}
+0+09c <[^>]*> ec80 0b03 	fstmiax	r0, {d0}
+0+0a0 <[^>]*> eca0 0b03 	fstmiax	r0!, {d0}
+0+0a4 <[^>]*> eca0 0b03 	fstmiax	r0!, {d0}
+0+0a8 <[^>]*> ed20 0b03 	fstmdbx	r0!, {d0}
+0+0ac <[^>]*> ed20 0b03 	fstmdbx	r0!, {d0}
 0+0b0 <[^>]*> eeb8 0ac0 	fsitos	s0, s0
 0+0b4 <[^>]*> eeb8 0a40 	fuitos	s0, s0
 0+0b8 <[^>]*> eebd 0a40 	ftosis	s0, s0
@@ -142,17 +142,17 @@ Disassembly of section .text:
 0+210 <[^>]*> ec90 fa02 	fldmias	r0, {s30-s31}
 0+214 <[^>]*> ec91 0a01 	fldmias	r1, {s0}
 0+218 <[^>]*> ec9e 0a01 	fldmias	lr, {s0}
-0+21c <[^>]*> ec80 1b03 	vstmia	r0, {d1}
-0+220 <[^>]*> ec80 2b03 	vstmia	r0, {d2}
-0+224 <[^>]*> ec80 fb03 	vstmia	r0, {d15}
-0+228 <[^>]*> ec80 0b05 	vstmia	r0, {d0-d1}
-0+22c <[^>]*> ec80 0b07 	vstmia	r0, {d0-d2}
-0+230 <[^>]*> ec80 0b21 	vstmia	r0, {d0-d15}
-0+234 <[^>]*> ec80 1b1f 	vstmia	r0, {d1-d15}
-0+238 <[^>]*> ec80 2b1d 	vstmia	r0, {d2-d15}
-0+23c <[^>]*> ec80 eb05 	vstmia	r0, {d14-d15}
-0+240 <[^>]*> ec81 0b03 	vstmia	r1, {d0}
-0+244 <[^>]*> ec8e 0b03 	vstmia	lr, {d0}
+0+21c <[^>]*> ec80 1b03 	fstmiax	r0, {d1}
+0+220 <[^>]*> ec80 2b03 	fstmiax	r0, {d2}
+0+224 <[^>]*> ec80 fb03 	fstmiax	r0, {d15}
+0+228 <[^>]*> ec80 0b05 	fstmiax	r0, {d0-d1}
+0+22c <[^>]*> ec80 0b07 	fstmiax	r0, {d0-d2}
+0+230 <[^>]*> ec80 0b21 	fstmiax	r0, {d0-d15}
+0+234 <[^>]*> ec80 1b1f 	fstmiax	r0, {d1-d15}
+0+238 <[^>]*> ec80 2b1d 	fstmiax	r0, {d2-d15}
+0+23c <[^>]*> ec80 eb05 	fstmiax	r0, {d14-d15}
+0+240 <[^>]*> ec81 0b03 	fstmiax	r1, {d0}
+0+244 <[^>]*> ec8e 0b03 	fstmiax	lr, {d0}
 0+248 <[^>]*> eeb5 0a40 	fcmpzs	s0
 0+24c <[^>]*> eef5 0a40 	fcmpzs	s1
 0+250 <[^>]*> eeb5 1a40 	fcmpzs	s2
@@ -219,13 +219,13 @@ Disassembly of section .text:
 0+334 <[^>]*> bf01      	itttt	eq
 0+336 <[^>]*> ed35 2a01 	fldmdbs(eq|)	r5!, {s4}
 0+33a <[^>]*> ed76 1a01 	fldmdbs(eq|)	r6!, {s3}
-0+33e <[^>]*> ec97 1b03 	vldmia(eq|)	r7, {d1}
-0+342 <[^>]*> ec98 2b03 	vldmia(eq|)	r8, {d2}
+0+33e <[^>]*> ec97 1b03 	fldmiax(eq|)	r7, {d1}
+0+342 <[^>]*> ec98 2b03 	fldmiax(eq|)	r8, {d2}
 0+346 <[^>]*> bf01      	itttt	eq
-0+348 <[^>]*> ecb9 3b03 	vldmia(eq|)	r9!, {d3}
-0+34c <[^>]*> ecba 4b03 	vldmia(eq|)	sl!, {d4}
-0+350 <[^>]*> ed3b 5b03 	vldmdb(eq|)	fp!, {d5}
-0+354 <[^>]*> ed3c 6b03 	vldmdb(eq|)	ip!, {d6}
+0+348 <[^>]*> ecb9 3b03 	fldmiax(eq|)	r9!, {d3}
+0+34c <[^>]*> ecba 4b03 	fldmiax(eq|)	sl!, {d4}
+0+350 <[^>]*> ed3b 5b03 	fldmdbx(eq|)	fp!, {d5}
+0+354 <[^>]*> ed3c 6b03 	fldmdbx(eq|)	ip!, {d6}
 0+358 <[^>]*> bf01      	itttt	eq
 0+35a <[^>]*> ec8d 1a01 	fstmias(eq|)	sp, {s2}
 0+35e <[^>]*> ecce 0a01 	fstmias(eq|)	lr, {s1}
@@ -234,13 +234,13 @@ Disassembly of section .text:
 0+36a <[^>]*> bf01      	itttt	eq
 0+36c <[^>]*> ed63 ea01 	fstmdbs(eq|)	r3!, {s29}
 0+370 <[^>]*> ed24 ea01 	fstmdbs(eq|)	r4!, {s28}
-0+374 <[^>]*> ec85 7b03 	vstmia(eq|)	r5, {d7}
-0+378 <[^>]*> ec86 8b03 	vstmia(eq|)	r6, {d8}
+0+374 <[^>]*> ec85 7b03 	fstmiax(eq|)	r5, {d7}
+0+378 <[^>]*> ec86 8b03 	fstmiax(eq|)	r6, {d8}
 0+37c <[^>]*> bf01      	itttt	eq
-0+37e <[^>]*> eca7 9b03 	vstmia(eq|)	r7!, {d9}
-0+382 <[^>]*> eca8 ab03 	vstmia(eq|)	r8!, {d10}
-0+386 <[^>]*> ed29 bb03 	vstmdb(eq|)	r9!, {d11}
-0+38a <[^>]*> ed2a cb03 	vstmdb(eq|)	sl!, {d12}
+0+37e <[^>]*> eca7 9b03 	fstmiax(eq|)	r7!, {d9}
+0+382 <[^>]*> eca8 ab03 	fstmiax(eq|)	r8!, {d10}
+0+386 <[^>]*> ed29 bb03 	fstmdbx(eq|)	r9!, {d11}
+0+38a <[^>]*> ed2a cb03 	fstmdbx(eq|)	sl!, {d12}
 0+38e <[^>]*> bf01      	itttt	eq
 0+390 <[^>]*> eef8 dac3 	fsitos(eq|)	s27, s6
 0+394 <[^>]*> eefd ca62 	ftosis(eq|)	s25, s5
diff -Nurp ../../binutils-csl-fpconst/src/gas/testsuite/gas/arm/vfpv3-32drs.d ./gas/testsuite/gas/arm/vfpv3-32drs.d
--- ../../binutils-csl-fpconst/src/gas/testsuite/gas/arm/vfpv3-32drs.d	2006-04-03 01:03:34.000000000 +0100
+++ ./gas/testsuite/gas/arm/vfpv3-32drs.d	2006-04-26 00:02:29.000000000 +0100
@@ -23,9 +23,9 @@ Disassembly of section \.text:
 0[0-9a-f]+ <[^>]+> edca5b01 	vstr	d21, \[sl, #4\]
 0[0-9a-f]+ <[^>]+> ecba5b04 	vldmia	sl!, {d5-d6}
 0[0-9a-f]+ <[^>]+> ecfa2b06 	vldmia	sl!, {d18-d20}
-0[0-9a-f]+ <[^>]+> ecba5b05 	vldmia	sl!, {d5-d6}
-0[0-9a-f]+ <[^>]+> ecfa2b07 	vldmia	sl!, {d18-d20}
-0[0-9a-f]+ <[^>]+> ed7a2b05 	vldmdb	sl!, {d18-d19}
+0[0-9a-f]+ <[^>]+> ecba5b05 	fldmiax	sl!, {d5-d6}
+0[0-9a-f]+ <[^>]+> ecfa2b07 	fldmiax	sl!, {d18-d20}
+0[0-9a-f]+ <[^>]+> ed7a2b05 	fldmdbx	sl!, {d18-d19}
 0[0-9a-f]+ <[^>]+> ecc94b0a 	vstmia	r9, {d20-d24}
 0[0-9a-f]+ <[^>]+> eeb03bc5 	fabsd	d3, d5
 0[0-9a-f]+ <[^>]+> eeb0cbe2 	fabsd	d12, d18
diff -Nurp ../../binutils-csl-fpconst/src/opcodes/arm-dis.c ./opcodes/arm-dis.c
--- ../../binutils-csl-fpconst/src/opcodes/arm-dis.c	2006-04-24 22:51:00.000000000 +0100
+++ ./opcodes/arm-dis.c	2006-04-26 00:48:32.000000000 +0100
@@ -209,12 +209,12 @@ static const struct opcode32 coprocessor
   {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 
   /* Register load/store */
+  {FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r%21'!, %B"},
+  {FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r%21'!, %B"},
+  {FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
+  {FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
   {FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %C"},
   {FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %C"},
-  {FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %B"},
-  {FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %B"},
-  {FPU_NEON_EXT_V1, 0x0d000b00, 0x0f900f00, "vstmdb%c\t%16-19r%21'!, %B"},
-  {FPU_NEON_EXT_V1, 0x0d100b00, 0x0f900f00, "vldmdb%c\t%16-19r%21'!, %B"},
 
   /* Data transfer between ARM and NEON registers */
   {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},

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