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[patch] Arm rbit encoding bug
- From: Paul Brook <paul at codesourcery dot com>
- To: binutils at sourceware dot org
- Date: Tue, 18 Jul 2006 22:06:25 +0100
- Subject: [patch] Arm rbit encoding bug
The patch below corrects the encoding of the Arm RBIT instruction.
Tested with cross to arm-none-eabi.
Ok?
Paul
2006-07-18 Paul Brook <paul@codesourcery.com>
gas/
* config/tc-arm.c (insns): Fix rbit Arm opcode.
gas/testsuite/
* gas/arm/archv6t2.d: Adjust expected output for rbit.
opcodes/
* armd-dis.c (arm_opcodes): Fix rbit opcode.
Index: gas/config/tc-arm.c
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/config/tc-arm.c,v
retrieving revision 1.278
diff -u -p -r1.278 tc-arm.c
--- gas/config/tc-arm.c 21 Jun 2006 14:20:24 -0000 1.278
+++ gas/config/tc-arm.c 15 Jul 2006 22:19:24 -0000
@@ -14746,7 +14758,7 @@ static const struct asm_opcode insns[] =
TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
TCE(movw, 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
TCE(movt, 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
- TCE(rbit, 3ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
+ TCE(rbit, 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
Index: gas/testsuite/gas/arm/archv6t2.d
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/testsuite/gas/arm/archv6t2.d,v
retrieving revision 1.1
diff -u -p -r1.1 archv6t2.d
--- gas/testsuite/gas/arm/archv6t2.d 15 Mar 2005 20:38:00 -0000 1.1
+++ gas/testsuite/gas/arm/archv6t2.d 15 Jul 2006 22:36:28 -0000
@@ -24,10 +24,10 @@ Disassembly of section .text:
0+40 <[^>]+> e7a00059 sbfx r0, r9, #0, #1
0+44 <[^>]+> e7a008d0 sbfx r0, r0, #17, #1
0+48 <[^>]+> e7b10050 sbfx r0, r0, #0, #18
-0+4c <[^>]+> e3ff0f30 rbit r0, r0
-0+50 <[^>]+> 13ff0f30 rbitne r0, r0
-0+54 <[^>]+> e3ff9f30 rbit r9, r0
-0+58 <[^>]+> e3ff0f39 rbit r0, r9
+0+4c <[^>]+> e6ff0f30 rbit r0, r0
+0+50 <[^>]+> 16ff0f30 rbitne r0, r0
+0+54 <[^>]+> e6ff9f30 rbit r9, r0
+0+58 <[^>]+> e6ff0f39 rbit r0, r9
0+5c <[^>]+> e0600090 mls r0, r0, r0, r0
0+60 <[^>]+> 10600090 mlsne r0, r0, r0, r0
0+64 <[^>]+> e0690090 mls r9, r0, r0, r0
Index: opcodes/arm-dis.c
===================================================================
RCS file: /var/cvsroot/src-cvs/src/opcodes/arm-dis.c,v
retrieving revision 1.68
diff -u -p -r1.68 arm-dis.c
--- opcodes/arm-dis.c 5 Jul 2006 17:08:47 -0000 1.68
+++ opcodes/arm-dis.c 15 Jul 2006 22:41:04 -0000
@@ -761,7 +761,7 @@ static const struct opcode32 arm_opcodes
{ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%c%6's%5?hbt\t%12-15r, %s"},
{ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"},
{ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"},
- {ARM_EXT_V6T2, 0x03ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"},
+ {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"},
{ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r,
#%7-11d, #%16-20W"},
/* ARM V6Z instructions. */