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Re: .reloc pseudo
On Mon, Mar 26, 2007 at 10:10:06AM -0400, Daniel Jacobowitz wrote:
> Do I really see an exciting new feature with neither NEWS nor tests?
Well, I did have some tests to commit.
gas/
* NEWS: Mention ".reloc".
gas/testsuite/
* gas/ppc/reloc.s: New.
* gas/ppc/reloc.d: New.
ld/testsuite/
* ld-spu/spu.exp (embed_test): New.
* ld-spu/ear.s: New.
* ld-spu/ear.d: New.
* ld-spu/embed.rd: New.
* ld-spu/ovl2.s: New.
* ld-spu/ovl2.d: New.
Index: gas/NEWS
===================================================================
RCS file: /cvs/src/src/gas/NEWS,v
retrieving revision 1.84
diff -u -p -r1.84 NEWS
--- gas/NEWS 20 Sep 2006 11:35:10 -0000 1.84
+++ gas/NEWS 27 Mar 2007 06:58:42 -0000
@@ -1,4 +1,7 @@
-*- text -*-
+* Added gas .reloc pseudo. This is a low-level interface for creating
+ relocations.
+
* Add support for x86_64 PE+ target.
* Add support for Score target.
Index: gas/testsuite/gas/ppc/reloc.d
===================================================================
RCS file: gas/testsuite/gas/ppc/reloc.d
diff -N gas/testsuite/gas/ppc/reloc.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/ppc/reloc.d 27 Mar 2007 06:58:49 -0000
@@ -0,0 +1,12 @@
+#readelf: -r --wide
+#name: reloc
+
+Relocation section '\.rela\.data' at .* contains 2 entries:
+ Offset Info Type Sym\. Value Symbol's Name \+ Addend
+0+08 .* R_PPC_ADDR32 .* y \+ f+fc
+0+0c .* R_PPC_ADDR32 .* y \+ 0
+
+Relocation section '\.rela\.data\.other' at .* contains 2 entries:
+ Offset Info Type Sym\. Value Symbol's Name \+ Addend
+0+00 .* R_PPC_ADDR32 .* x \+ 0
+0+04 .* R_PPC_ADDR32 .* x \+ f+fc
Index: gas/testsuite/gas/ppc/reloc.s
===================================================================
RCS file: gas/testsuite/gas/ppc/reloc.s
diff -N gas/testsuite/gas/ppc/reloc.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/ppc/reloc.s 27 Mar 2007 06:58:49 -0000
@@ -0,0 +1,13 @@
+ .reloc x+8, R_PPC_ADDR32, y-4
+
+ .data
+x:
+ .long 0,0,0,0
+
+ .section .data.other,"aw",@progbits
+y:
+ .long 0,0,0,0
+
+ .reloc 0, R_PPC_ADDR32, x
+ .reloc y+4, R_PPC_ADDR32, x-4
+ .reloc x+12, R_PPC_ADDR32, y
Index: ld/testsuite/ld-spu/ear.d
===================================================================
RCS file: ld/testsuite/ld-spu/ear.d
diff -N ld/testsuite/ld-spu/ear.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-spu/ear.d 27 Mar 2007 06:07:44 -0000
@@ -0,0 +1,30 @@
+#as:
+#objdump: -Dr
+#name: ear
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+00 <_start>:
+ 0: 32 00 00 00 br 0
+ 0: SPU_REL16 _start
+
+Disassembly of section \.data:
+
+0+00 <_EAR_main>:
+ \.\.\.
+
+0+20 <_EAR_foo>:
+ \.\.\.
+Disassembly of section \.toe:
+
+0+00 <_EAR_>:
+ \.\.\.
+
+0+10 <_EAR_bar>:
+ \.\.\.
+Disassembly of section \.data\.blah:
+
+0+00 <_EAR_blah>:
+ \.\.\.
Index: ld/testsuite/ld-spu/ear.s
===================================================================
RCS file: ld/testsuite/ld-spu/ear.s
diff -N ld/testsuite/ld-spu/ear.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-spu/ear.s 27 Mar 2007 06:07:44 -0000
@@ -0,0 +1,25 @@
+ .text
+ .global _start
+_start:
+ br _start
+
+#test old-style toe _EAR_ syms
+ .section .toe,"a",@nobits
+_EAR_:
+ .space 16
+_EAR_bar:
+ .space 16
+
+#test new-style _EAR_ syms
+ .data
+_EAR_main:
+ .space 16
+
+#new ones don't need to be 16 bytes apart
+ .space 16
+_EAR_foo:
+ .space 16
+
+ .section .data.blah,"aw",@progbits
+_EAR_blah:
+ .space 16
Index: ld/testsuite/ld-spu/embed.rd
===================================================================
RCS file: ld/testsuite/ld-spu/embed.rd
diff -N ld/testsuite/ld-spu/embed.rd
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-spu/embed.rd 27 Mar 2007 06:07:44 -0000
@@ -0,0 +1,16 @@
+
+Relocation section '\.rela\.rodata\.speelf' at .* contains 3 entries:
+ Offset Info Type Sym\. Value Symbol's Name \+ Addend
+00000184 00000601 R_PPC_ADDR32 00000000 main \+ 0
+000001a4 00000901 R_PPC_ADDR32 00000000 foo \+ 0
+000001b4 00000701 R_PPC_ADDR32 00000000 blah \+ 0
+
+Relocation section '\.rela\.data' at .* contains 2 entries:
+ Offset Info Type Sym\. Value Symbol's Name \+ Addend
+00000004 00000201 R_PPC_ADDR32 00000000 \.rodata\.speelf \+ 0
+00000008 00000401 R_PPC_ADDR32 00000000 \.data\.spetoe \+ 0
+
+Relocation section '\.rela\.data\.spetoe' at .* contains 2 entries:
+ Offset Info Type Sym\. Value Symbol's Name \+ Addend
+00000004 00000201 R_PPC_ADDR32 00000000 \.rodata\.speelf \+ 0
+00000014 00000a01 R_PPC_ADDR32 00000000 bar \+ 0
Index: ld/testsuite/ld-spu/ovl2.d
===================================================================
RCS file: ld/testsuite/ld-spu/ovl2.d
diff -N ld/testsuite/ld-spu/ovl2.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-spu/ovl2.d 27 Mar 2007 06:07:44 -0000
@@ -0,0 +1,81 @@
+#source: ovl2.s
+#ld: -N -T ovl.lnk --emit-relocs
+#objdump: -D -r
+
+.*elf32-spu
+
+Disassembly of section \.text:
+
+00000100 <_start>:
+ 100: 33 00 06 00 brsl \$0,130 <00000000\.ovl_call\.f1_a1> # 130
+ 100: SPU_REL16 f1_a1
+ 104: 33 00 03 80 brsl \$0,120 <00000000\.ovl_call\.10:4> # 120
+ 104: SPU_REL16 setjmp
+ 108: 32 7f ff 00 br 100 <_start> # 100
+ 108: SPU_REL16 _start
+
+0000010c <setjmp>:
+ 10c: 35 00 00 00 bi \$0
+
+00000110 <longjmp>:
+ 110: 35 00 00 00 bi \$0
+ ...
+
+00000120 <00000000\.ovl_call.10:4>:
+ 120: 42 00 86 4f ila \$79,268 # 10c
+ 124: 40 20 00 00 nop \$0
+ 128: 42 00 00 4e ila \$78,0
+ 12c: 32 00 0a 80 br 180 <__ovly_load> # 180
+
+00000130 <00000000\.ovl_call.f1_a1>:
+ 130: 42 02 00 4f ila \$79,1024 # 400
+ 134: 40 20 00 00 nop \$0
+ 138: 42 00 00 ce ila \$78,1
+ 13c: 32 00 08 80 br 180 <__ovly_load> # 180
+
+00000140 <00000000\.ovl_call\._SPUEAR_f1_a2>:
+ 140: 42 02 00 4f ila \$79,1024 # 400
+ 144: 40 20 00 00 nop \$0
+ 148: 42 00 01 4e ila \$78,2
+ 14c: 32 00 06 80 br 180 <__ovly_load> # 180
+#...
+Disassembly of section \.ov_a1:
+
+00000400 <f1_a1>:
+ 400: 35 00 00 00 bi \$0
+ \.\.\.
+Disassembly of section \.ov_a2:
+
+00000400 <_SPUEAR_f1_a2>:
+ 400: 32 7f a2 00 br 110 <longjmp> # 110
+ 400: SPU_REL16 longjmp
+ \.\.\.
+Disassembly of section \.data:
+
+00000410 <_ovly_table>:
+ 410: 00 00 04 00 .*
+ 414: 00 00 00 10 .*
+ 418: 00 00 02 c0 .*
+ 41c: 00 00 00 01 .*
+ 420: 00 00 04 00 .*
+ 424: 00 00 00 10 .*
+ 428: 00 00 02 d0 .*
+ 42c: 00 00 00 01 .*
+
+00000430 <_ovly_buf_table>:
+ 430: 00 00 00 00 .*
+Disassembly of section \.toe:
+
+00000440 <_EAR_>:
+ \.\.\.
+Disassembly of section \.note\.spu_name:
+
+.* <\.note\.spu_name>:
+.*: 00 00 00 08 .*
+.*: 00 00 00 0c .*
+.*: 00 00 00 01 .*
+.*: 53 50 55 4e .*
+.*: 41 4d 45 00 .*
+.*: 74 6d 70 64 .*
+.*: 69 72 2f 64 .*
+.*: 75 6d 70 00 .*
Index: ld/testsuite/ld-spu/ovl2.s
===================================================================
RCS file: ld/testsuite/ld-spu/ovl2.s
diff -N ld/testsuite/ld-spu/ovl2.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/testsuite/ld-spu/ovl2.s 27 Mar 2007 06:07:44 -0000
@@ -0,0 +1,35 @@
+ .text
+ .p2align 2
+ .global _start
+_start:
+ brsl lr,f1_a1
+ brsl lr,setjmp
+ br _start
+
+ .type setjmp,@function
+setjmp:
+ bi lr
+ .size setjmp,.-setjmp
+
+ .type longjmp,@function
+longjmp:
+ bi lr
+ .size longjmp,.-longjmp
+
+ .section .ov_a1,"ax",@progbits
+ .p2align 2
+ .global f1_a1
+ .type f1_a1,@function
+f1_a1:
+ bi lr
+ .size f1_a1,.-f1_a1
+
+ .section .ov_a2,"ax",@progbits
+ .p2align 2
+ .type f1_a2,@function
+f1_a2:
+ br longjmp
+ .size f1_a2,.-f1_a2
+
+_SPUEAR_f1_a2 = f1_a2
+ .global _SPUEAR_f1_a2
Index: ld/testsuite/ld-spu/spu.exp
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-spu/spu.exp,v
retrieving revision 1.1
diff -u -p -r1.1 spu.exp
--- ld/testsuite/ld-spu/spu.exp 25 Oct 2006 06:49:21 -0000 1.1
+++ ld/testsuite/ld-spu/spu.exp 27 Mar 2007 06:07:44 -0000
@@ -20,8 +20,72 @@ if { ![istarget "spu-*-*"] } {
return
}
+proc embed_test { } {
+ global subdir srcdir
+ global AS ASFLAGS LD LDFLAGS READELF READELFFLAGS
+
+ set cmd "$AS $ASFLAGS -o tmpdir/ear.o $srcdir/$subdir/ear.s"
+ send_log "$cmd\n"
+ set cmdret [catch "exec $cmd" comp_output]
+ set comp_output [prune_warnings $comp_output]
+ if { $cmdret != 0 || $comp_output != ""} then {
+ send_log "$comp_output\n"
+ verbose "$comp_output" 3
+ fail "ear assembly"
+ return
+ }
+
+ set cmd "$LD $LDFLAGS -o tmpdir/ear tmpdir/ear.o"
+ send_log "$cmd\n"
+ set cmdret [catch "exec $cmd" comp_output]
+ set comp_output [prune_warnings $comp_output]
+ if { $cmdret != 0 || $comp_output != ""} then {
+ send_log "$comp_output\n"
+ verbose "$comp_output" 3
+ fail "ear link"
+ return
+ }
+
+ set cmd "sh $srcdir/../../binutils/embedspu.sh -m32 ear tmpdir/ear tmpdir/embed.o"
+ send_log "$cmd\n"
+ set cmdret [catch "exec $cmd" comp_output]
+ set comp_output [prune_warnings $comp_output]
+ if { $cmdret != 0 || $comp_output != ""} then {
+ send_log "$comp_output\n"
+ verbose "$comp_output" 3
+ if { [regexp "unknown pseudo-op: `.reloc'" $comp_output] } {
+ untested "ear embedspu"
+ return
+ }
+ fail "ear embedspu"
+ return
+ }
+
+ set cmd "$READELF $READELFFLAGS -r --wide tmpdir/embed.o > tmpdir/embed.out"
+ send_log "$cmd\n"
+ set cmdret [catch "exec $cmd" comp_output]
+ set comp_output [prune_warnings $comp_output]
+ if { $cmdret != 0 || $comp_output != ""} then {
+ send_log "$comp_output\n"
+ verbose "$comp_output" 3
+ fail "ear embed readelf"
+ return
+ }
+
+ if { [regexp_diff "tmpdir/embed.out" $srcdir/$subdir/embed.rd] } then {
+ fail "ear embed output"
+ return
+ }
+
+ pass "ear embed"
+}
+
set rd_test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
foreach sputest $rd_test_list {
verbose [file rootname $sputest]
run_dump_test [file rootname $sputest]
}
+
+if { [isbuild "powerpc*-*-linux*"] } {
+ embed_test
+}
--
Alan Modra
IBM OzLabs - Linux Technology Centre