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Thumb-2 ldrd misassembly


The attached patch below fixes assembly and disassembly of writeback 
addressing modes on Thumb-2 doubleword load/store instructions.

Tested on arm-none-eabi.
Applied to CVS head.

Paul

2007-06-05  Paul Brook  <paul@codesourcery.com>

	gas/
	* config/tc-arm.c (insns): Correct Thumb-2 ldrd/strd opcodes.

	gas/testsuite/
	* gas/arm/thumb32.d: Add writeback addressing mode tests.
	* gas/arm/thumb32.s: Update expected output.

	opcodes/
	* arm-dis.c (thumb32_opcodes): Display writeback ldrd/strd addresses.
Index: gas/config/tc-arm.c
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/config/tc-arm.c,v
retrieving revision 1.328
diff -u -p -r1.328 tc-arm.c
--- gas/config/tc-arm.c	31 May 2007 14:50:16 -0000	1.328
+++ gas/config/tc-arm.c	5 Jun 2007 18:55:49 -0000
@@ -15017,8 +15017,8 @@ static const struct asm_opcode insns[] =
 #undef ARM_VARIANT
 #define ARM_VARIANT &arm_ext_v5e /*  ARM Architecture 5TE.  */
  TUF(pld,	450f000, f810f000, 1, (ADDR),		     pld,  t_pld),
- TC3(ldrd,	00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
- TC3(strd,	00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
+ TC3(ldrd,	00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
+ TC3(strd,	00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
 
  TCE(mcrr,	c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
  TCE(mrrc,	c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
Index: gas/testsuite/gas/arm/thumb32.d
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/testsuite/gas/arm/thumb32.d,v
retrieving revision 1.22
diff -u -p -r1.22 thumb32.d
--- gas/testsuite/gas/arm/thumb32.d	25 May 2007 23:13:23 -0000	1.22
+++ gas/testsuite/gas/arm/thumb32.d	5 Jun 2007 20:41:15 -0000
@@ -963,3 +963,41 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> f3de 8f00 	subs	pc, lr, #0
 0[0-9a-f]+ <[^>]+> f3de 8f04 	subs	pc, lr, #4
 0[0-9a-f]+ <[^>]+> f3de 8fff 	subs	pc, lr, #255
+0[0-9a-f]+ <[^>]+> e9f9 240c 	ldrd	r2, r4, \[r9, #48\]!
+0[0-9a-f]+ <[^>]+> e979 240c 	ldrd	r2, r4, \[r9, #-48\]!
+0[0-9a-f]+ <[^>]+> e9e9 240c 	strd	r2, r4, \[r9, #48\]!
+0[0-9a-f]+ <[^>]+> e969 240c 	strd	r2, r4, \[r9, #-48\]!
+0[0-9a-f]+ <[^>]+> e8f9 240c 	ldrd	r2, r4, \[r9\], #48
+0[0-9a-f]+ <[^>]+> e879 240c 	ldrd	r2, r4, \[r9\], #-48
+0[0-9a-f]+ <[^>]+> e8e9 240c 	strd	r2, r4, \[r9\], #48
+0[0-9a-f]+ <[^>]+> e869 240c 	strd	r2, r4, \[r9\], #-48
+0[0-9a-f]+ <[^>]+> f8d5 1301 	ldr.w	r1, \[r5, #769]
+0[0-9a-f]+ <[^>]+> f855 1f30 	ldr.w	r1, \[r5, #48]!
+0[0-9a-f]+ <[^>]+> f855 1d30 	ldr.w	r1, \[r5, #-48]!
+0[0-9a-f]+ <[^>]+> f855 1b30 	ldr.w	r1, \[r5\], #48
+0[0-9a-f]+ <[^>]+> f855 1930 	ldr.w	r1, \[r5\], #-48
+0[0-9a-f]+ <[^>]+> f855 1009 	ldr.w	r1, \[r5, r9\]
+0[0-9a-f]+ <[^>]+> f895 1301 	ldrb.w	r1, \[r5, #769]
+0[0-9a-f]+ <[^>]+> f815 1f30 	ldrb.w	r1, \[r5, #48]!
+0[0-9a-f]+ <[^>]+> f815 1d30 	ldrb.w	r1, \[r5, #-48]!
+0[0-9a-f]+ <[^>]+> f815 1b30 	ldrb.w	r1, \[r5\], #48
+0[0-9a-f]+ <[^>]+> f815 1930 	ldrb.w	r1, \[r5\], #-48
+0[0-9a-f]+ <[^>]+> f815 1009 	ldrb.w	r1, \[r5, r9\]
+0[0-9a-f]+ <[^>]+> f995 1301 	ldrsb.w	r1, \[r5, #769]
+0[0-9a-f]+ <[^>]+> f915 1f30 	ldrsb.w	r1, \[r5, #48]!
+0[0-9a-f]+ <[^>]+> f915 1d30 	ldrsb.w	r1, \[r5, #-48]!
+0[0-9a-f]+ <[^>]+> f915 1b30 	ldrsb.w	r1, \[r5\], #48
+0[0-9a-f]+ <[^>]+> f915 1930 	ldrsb.w	r1, \[r5\], #-48
+0[0-9a-f]+ <[^>]+> f915 1009 	ldrsb.w	r1, \[r5, r9\]
+0[0-9a-f]+ <[^>]+> f8b5 1301 	ldrh.w	r1, \[r5, #769]
+0[0-9a-f]+ <[^>]+> f835 1f30 	ldrh.w	r1, \[r5, #48]!
+0[0-9a-f]+ <[^>]+> f835 1d30 	ldrh.w	r1, \[r5, #-48]!
+0[0-9a-f]+ <[^>]+> f835 1b30 	ldrh.w	r1, \[r5\], #48
+0[0-9a-f]+ <[^>]+> f835 1930 	ldrh.w	r1, \[r5\], #-48
+0[0-9a-f]+ <[^>]+> f835 1009 	ldrh.w	r1, \[r5, r9\]
+0[0-9a-f]+ <[^>]+> f9b5 1301 	ldrsh.w	r1, \[r5, #769]
+0[0-9a-f]+ <[^>]+> f935 1f30 	ldrsh.w	r1, \[r5, #48]!
+0[0-9a-f]+ <[^>]+> f935 1d30 	ldrsh.w	r1, \[r5, #-48]!
+0[0-9a-f]+ <[^>]+> f935 1b30 	ldrsh.w	r1, \[r5\], #48
+0[0-9a-f]+ <[^>]+> f935 1930 	ldrsh.w	r1, \[r5\], #-48
+0[0-9a-f]+ <[^>]+> f935 1009 	ldrsh.w	r1, \[r5, r9\]
Index: gas/testsuite/gas/arm/thumb32.s
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/testsuite/gas/arm/thumb32.s,v
retrieving revision 1.12
diff -u -p -r1.12 thumb32.s
--- gas/testsuite/gas/arm/thumb32.s	25 May 2007 23:13:24 -0000	1.12
+++ gas/testsuite/gas/arm/thumb32.s	5 Jun 2007 19:57:06 -0000
@@ -780,3 +780,26 @@ srs:
 	subs pc, lr, #0
 	subs pc, lr, #4
 	subs pc, lr, #255
+
+	ldrd r2, r4, [r9, #48]!
+	ldrd r2, r4, [r9, #-48]!
+	strd r2, r4, [r9, #48]!
+	strd r2, r4, [r9, #-48]!
+	ldrd r2, r4, [r9], #48
+	ldrd r2, r4, [r9], #-48
+	strd r2, r4, [r9], #48
+	strd r2, r4, [r9], #-48
+
+	.macro ldaddr op
+	ldr\op	r1, [r5, #0x301]
+	ldr\op	r1, [r5, #0x30]!
+	ldr\op	r1, [r5, #-0x30]!
+	ldr\op	r1, [r5], #0x30
+	ldr\op	r1, [r5], #-0x30
+	ldr\op	r1, [r5, r9]
+	.endm
+	ldaddr
+	ldaddr b
+	ldaddr sb
+	ldaddr h
+	ldaddr sh
Index: opcodes/arm-dis.c
===================================================================
RCS file: /var/cvsroot/src-cvs/src/opcodes/arm-dis.c,v
retrieving revision 1.83
diff -u -p -r1.83 arm-dis.c
--- opcodes/arm-dis.c	24 Apr 2007 13:21:32 -0000	1.83
+++ opcodes/arm-dis.c	5 Jun 2007 19:19:07 -0000
@@ -1403,8 +1403,10 @@ static const struct opcode32 thumb32_opc
   {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
   {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
   {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
-  {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"},
-  {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"},
+  {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"},
+  {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"},
+  {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"},
+  {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"},
   {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
   {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
 

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