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PATCH: Add tests for 64bit insns with one register operand
- From: "H.J. Lu" <hjl at lucon dot org>
- To: binutils at sources dot redhat dot com
- Date: Wed, 29 Aug 2007 12:40:45 -0700
- Subject: PATCH: Add tests for 64bit insns with one register operand
I am checking in this patch to add tests for 64bit insns with one
register operand.
H.J.
----
2007-08-29 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run x86-64-reg and x86-64-reg-intel.
* gas/i386/x86-64-reg.s: New. Add tests for instructions
with one register operand.
* gas/i386/x86-64-reg-intel.d: Likewise.
* gas/i386/x86-64-reg.d: Likewise.
--- gas/i386/i386.exp.reg 2007-08-29 08:43:38.000000000 -0700
+++ gas/i386/i386.exp 2007-08-29 12:30:09.000000000 -0700
@@ -193,6 +193,8 @@ if [expr ([istarget "i*86-*-*"] || [ista
run_dump_test "x86-64-simd-intel"
run_dump_test "x86-64-mem"
run_dump_test "x86-64-mem-intel"
+ run_dump_test "x86-64-reg"
+ run_dump_test "x86-64-reg-intel"
if { ![istarget "*-*-aix*"]
&& ![istarget "*-*-beos*"]
--- gas/i386/x86-64-reg-intel.d.reg 2007-08-29 12:30:55.000000000 -0700
+++ gas/i386/x86-64-reg-intel.d 2007-08-29 12:29:43.000000000 -0700
@@ -0,0 +1,47 @@
+#source: x86-64-reg.s
+#as: -J
+#objdump: -dw -Mintel
+#name: x86-64 reg (Intel mode)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2
+[ ]*[a-f0-9]+: 66 41 0f 71 d2 02 psrlw xmm10,0x2
+[ ]*[a-f0-9]+: 0f 71 e6 02 psraw mm6,0x2
+[ ]*[a-f0-9]+: 66 41 0f 71 e2 02 psraw xmm10,0x2
+[ ]*[a-f0-9]+: 0f 71 f6 02 psllw mm6,0x2
+[ ]*[a-f0-9]+: 66 41 0f 71 f2 02 psllw xmm10,0x2
+[ ]*[a-f0-9]+: 0f 72 d6 02 psrld mm6,0x2
+[ ]*[a-f0-9]+: 66 41 0f 72 d2 02 psrld xmm10,0x2
+[ ]*[a-f0-9]+: 0f 72 e6 02 psrad mm6,0x2
+[ ]*[a-f0-9]+: 66 41 0f 72 e2 02 psrad xmm10,0x2
+[ ]*[a-f0-9]+: 0f 72 f6 02 pslld mm6,0x2
+[ ]*[a-f0-9]+: 66 41 0f 72 f2 02 pslld xmm10,0x2
+[ ]*[a-f0-9]+: 0f 73 d6 02 psrlq mm6,0x2
+[ ]*[a-f0-9]+: 66 41 0f 73 d2 02 psrlq xmm10,0x2
+[ ]*[a-f0-9]+: 66 41 0f 73 da 02 psrldq xmm10,0x2
+[ ]*[a-f0-9]+: 0f 73 f6 02 psllq mm6,0x2
+[ ]*[a-f0-9]+: 66 41 0f 73 f2 02 psllq xmm10,0x2
+[ ]*[a-f0-9]+: 66 41 0f 73 fa 02 pslldq xmm10,0x2
+[ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2
+[ ]*[a-f0-9]+: 66 0f 71 d2 02 psrlw xmm2,0x2
+[ ]*[a-f0-9]+: 0f 71 e6 02 psraw mm6,0x2
+[ ]*[a-f0-9]+: 66 0f 71 e2 02 psraw xmm2,0x2
+[ ]*[a-f0-9]+: 0f 71 f6 02 psllw mm6,0x2
+[ ]*[a-f0-9]+: 66 0f 71 f2 02 psllw xmm2,0x2
+[ ]*[a-f0-9]+: 0f 72 d6 02 psrld mm6,0x2
+[ ]*[a-f0-9]+: 66 0f 72 d2 02 psrld xmm2,0x2
+[ ]*[a-f0-9]+: 0f 72 e6 02 psrad mm6,0x2
+[ ]*[a-f0-9]+: 66 0f 72 e2 02 psrad xmm2,0x2
+[ ]*[a-f0-9]+: 0f 72 f6 02 pslld mm6,0x2
+[ ]*[a-f0-9]+: 66 0f 72 f2 02 pslld xmm2,0x2
+[ ]*[a-f0-9]+: 0f 73 d6 02 psrlq mm6,0x2
+[ ]*[a-f0-9]+: 66 0f 73 d2 02 psrlq xmm2,0x2
+[ ]*[a-f0-9]+: 66 0f 73 da 02 psrldq xmm2,0x2
+[ ]*[a-f0-9]+: 0f 73 f6 02 psllq mm6,0x2
+[ ]*[a-f0-9]+: 66 0f 73 f2 02 psllq xmm2,0x2
+[ ]*[a-f0-9]+: 66 0f 73 fa 02 pslldq xmm2,0x2
+#pass
--- gas/i386/x86-64-reg.d.reg 2007-08-29 12:30:51.000000000 -0700
+++ gas/i386/x86-64-reg.d 2007-08-29 12:29:01.000000000 -0700
@@ -0,0 +1,46 @@
+#as: -J
+#objdump: -dw
+#name: x86-64 reg
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 0f 71 d6 02 psrlw \$0x2,%mm6
+[ ]*[a-f0-9]+: 66 41 0f 71 d2 02 psrlw \$0x2,%xmm10
+[ ]*[a-f0-9]+: 0f 71 e6 02 psraw \$0x2,%mm6
+[ ]*[a-f0-9]+: 66 41 0f 71 e2 02 psraw \$0x2,%xmm10
+[ ]*[a-f0-9]+: 0f 71 f6 02 psllw \$0x2,%mm6
+[ ]*[a-f0-9]+: 66 41 0f 71 f2 02 psllw \$0x2,%xmm10
+[ ]*[a-f0-9]+: 0f 72 d6 02 psrld \$0x2,%mm6
+[ ]*[a-f0-9]+: 66 41 0f 72 d2 02 psrld \$0x2,%xmm10
+[ ]*[a-f0-9]+: 0f 72 e6 02 psrad \$0x2,%mm6
+[ ]*[a-f0-9]+: 66 41 0f 72 e2 02 psrad \$0x2,%xmm10
+[ ]*[a-f0-9]+: 0f 72 f6 02 pslld \$0x2,%mm6
+[ ]*[a-f0-9]+: 66 41 0f 72 f2 02 pslld \$0x2,%xmm10
+[ ]*[a-f0-9]+: 0f 73 d6 02 psrlq \$0x2,%mm6
+[ ]*[a-f0-9]+: 66 41 0f 73 d2 02 psrlq \$0x2,%xmm10
+[ ]*[a-f0-9]+: 66 41 0f 73 da 02 psrldq \$0x2,%xmm10
+[ ]*[a-f0-9]+: 0f 73 f6 02 psllq \$0x2,%mm6
+[ ]*[a-f0-9]+: 66 41 0f 73 f2 02 psllq \$0x2,%xmm10
+[ ]*[a-f0-9]+: 66 41 0f 73 fa 02 pslldq \$0x2,%xmm10
+[ ]*[a-f0-9]+: 0f 71 d6 02 psrlw \$0x2,%mm6
+[ ]*[a-f0-9]+: 66 0f 71 d2 02 psrlw \$0x2,%xmm2
+[ ]*[a-f0-9]+: 0f 71 e6 02 psraw \$0x2,%mm6
+[ ]*[a-f0-9]+: 66 0f 71 e2 02 psraw \$0x2,%xmm2
+[ ]*[a-f0-9]+: 0f 71 f6 02 psllw \$0x2,%mm6
+[ ]*[a-f0-9]+: 66 0f 71 f2 02 psllw \$0x2,%xmm2
+[ ]*[a-f0-9]+: 0f 72 d6 02 psrld \$0x2,%mm6
+[ ]*[a-f0-9]+: 66 0f 72 d2 02 psrld \$0x2,%xmm2
+[ ]*[a-f0-9]+: 0f 72 e6 02 psrad \$0x2,%mm6
+[ ]*[a-f0-9]+: 66 0f 72 e2 02 psrad \$0x2,%xmm2
+[ ]*[a-f0-9]+: 0f 72 f6 02 pslld \$0x2,%mm6
+[ ]*[a-f0-9]+: 66 0f 72 f2 02 pslld \$0x2,%xmm2
+[ ]*[a-f0-9]+: 0f 73 d6 02 psrlq \$0x2,%mm6
+[ ]*[a-f0-9]+: 66 0f 73 d2 02 psrlq \$0x2,%xmm2
+[ ]*[a-f0-9]+: 66 0f 73 da 02 psrldq \$0x2,%xmm2
+[ ]*[a-f0-9]+: 0f 73 f6 02 psllq \$0x2,%mm6
+[ ]*[a-f0-9]+: 66 0f 73 f2 02 psllq \$0x2,%xmm2
+[ ]*[a-f0-9]+: 66 0f 73 fa 02 pslldq \$0x2,%xmm2
+#pass
--- gas/i386/x86-64-reg.s.reg 2007-08-29 12:30:48.000000000 -0700
+++ gas/i386/x86-64-reg.s 2007-08-29 12:28:20.000000000 -0700
@@ -0,0 +1,44 @@
+# Check 64bit instructions with one register operand
+
+ .text
+_start:
+psrlw $2, %mm6
+psrlw $2, %xmm10
+psraw $2, %mm6
+psraw $2, %xmm10
+psllw $2, %mm6
+psllw $2, %xmm10
+psrld $2, %mm6
+psrld $2, %xmm10
+psrad $2, %mm6
+psrad $2, %xmm10
+pslld $2, %mm6
+pslld $2, %xmm10
+psrlq $2, %mm6
+psrlq $2, %xmm10
+psrldq $2, %xmm10
+psllq $2, %mm6
+psllq $2, %xmm10
+pslldq $2, %xmm10
+
+.intel_syntax noprefix
+psrlw mm6, 2
+psrlw xmm2, 2
+psraw mm6, 2
+psraw xmm2, 2
+psllw mm6, 2
+psllw xmm2, 2
+psrld mm6, 2
+psrld xmm2, 2
+psrad mm6, 2
+psrad xmm2, 2
+pslld mm6, 2
+pslld xmm2, 2
+psrlq mm6, 2
+psrlq xmm2, 2
+psrldq xmm2, 2
+psllq mm6, 2
+psllq xmm2, 2
+pslldq xmm2, 2
+
+.p2align 4,0