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PATCH: Fix movddup in Intel syntax
- From: "H.J. Lu" <hjl at lucon dot org>
- To: binutils at sources dot redhat dot com
- Date: Tue, 15 Jan 2008 16:04:05 -0800
- Subject: PATCH: Fix movddup in Intel syntax
I am checking in this patch to fix movddup in Intel syntax.
H.J.
---
gas/testsuite/
2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/prescott.s: Add tests for movddup in Intel syntax.
* gas/i386/x86-64-prescott.s: Likewise.
* gas/i386/prescott.d: Updated.
* gas/i386/x86-64-prescott.d: Likewise.
opcodes/
2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Use Qword on movddup.
* i386-tbl.h: Regenerated.
Index: gas/testsuite/gas/i386/prescott.d
===================================================================
--- gas/testsuite/gas/i386/prescott.d (revision 1269)
+++ gas/testsuite/gas/i386/prescott.d (working copy)
@@ -34,4 +34,6 @@ Disassembly of section .text:
69: 0f 01 c9 [ ]*mwait %eax,%ecx
6c: 67 0f 01 c8 [ ]*monitor %ax,%ecx,%edx
70: 67 0f 01 c8 [ ]*monitor %ax,%ecx,%edx
- ...
+ 74: f2 0f 12 38 [ ]*movddup \(%eax\),%xmm7
+ 78: f2 0f 12 38 [ ]*movddup \(%eax\),%xmm7
+#pass
Index: gas/testsuite/gas/i386/prescott.s
===================================================================
--- gas/testsuite/gas/i386/prescott.s (revision 1269)
+++ gas/testsuite/gas/i386/prescott.s (working copy)
@@ -32,4 +32,6 @@ foo:
monitor %ax,%ecx,%edx
addr16 monitor
- .p2align 4,0
+ .intel_syntax noprefix
+ movddup xmm7,[eax]
+ movddup xmm7,QWORD PTR [eax]
Index: gas/testsuite/gas/i386/x86-64-prescott.d
===================================================================
--- gas/testsuite/gas/i386/x86-64-prescott.d (revision 1269)
+++ gas/testsuite/gas/i386/x86-64-prescott.d (working copy)
@@ -34,4 +34,6 @@ Disassembly of section .text:
69: 0f 01 c9 [ ]*mwait %rax,%rcx
6c: 67 0f 01 c8 [ ]*monitor %eax,%rcx,%rdx
70: 67 0f 01 c8 [ ]*monitor %eax,%rcx,%rdx
- ...
+ 74: f2 0f 12 38 [ ]*movddup \(%rax\),%xmm7
+ 78: f2 0f 12 38 [ ]*movddup \(%rax\),%xmm7
+#pass
Index: gas/testsuite/gas/i386/x86-64-prescott.s
===================================================================
--- gas/testsuite/gas/i386/x86-64-prescott.s (revision 1269)
+++ gas/testsuite/gas/i386/x86-64-prescott.s (working copy)
@@ -32,4 +32,6 @@ foo:
monitor %eax,%rcx,%rdx
addr32 monitor
- .p2align 4,0
+ .intel_syntax noprefix
+ movddup xmm7,[rax]
+ movddup xmm7,QWORD PTR [rax]
Index: opcodes/i386-tbl.h
===================================================================
--- opcodes/i386-tbl.h (revision 1288)
+++ opcodes/i386-tbl.h (working copy)
@@ -10919,7 +10919,7 @@ const template i386_optab[] =
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
- 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
+ 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
1, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
Index: opcodes/i386-opc.tbl
===================================================================
--- opcodes/i386-opc.tbl (revision 1288)
+++ opcodes/i386-opc.tbl (working copy)
@@ -1275,7 +1275,7 @@ monitor, 0, 0xf01, 0xc8, 2, CpuSSE3, No_
monitor, 3, 0xf01, 0xc8, 2, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0, { Reg16|Reg32, Reg32, Reg32 }
// Need to ensure only "monitor %rax/%eax,%rcx,%rdx" is accepted.
monitor, 3, 0xf01, 0xc8, 2, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|AddrPrefixOp0|NoRex64, { Reg32|Reg64, Reg64, Reg64 }
-movddup, 2, 0xf20f12, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
+movddup, 2, 0xf20f12, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
movshdup, 2, 0xf30f16, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
movsldup, 2, 0xf30f12, None, 2, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
mwait, 0, 0xf01, 0xc9, 2, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }