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Re: [PATCH] x86/Intel: fix indirect far jmp/call with operand size specified
- From: "H.J. Lu" <hjl dot tools at gmail dot com>
- To: "Jan Beulich" <jbeulich at novell dot com>
- Cc: binutils at sourceware dot org
- Date: Thu, 21 Feb 2008 08:44:06 -0800
- Subject: Re: [PATCH] x86/Intel: fix indirect far jmp/call with operand size specified
- References: <47BDB2BE.76E4.0078.0@novell.com>
Hi Jan,
Do you have testcases?
H.J.
On Thu, Feb 21, 2008 at 8:19 AM, Jan Beulich <jbeulich@novell.com> wrote:
> Far jumps and calls were broken due to missing permissions to use
> certain operand size operators on their operands.
> Additionally, jmp and call, which really behave identically as far as
> operands are concerned, were out of sync in a few more respects.
>
> opcodes/
> 2008-02-21 Jan Beulich <jbeulich@novell.com>
>
> * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
> and Fword for far indirect jmp. Allow Reg16 and Word for near
> indirect jmp on x86-64. Disallow Fword for lcall.
> * i386-tbl.h: Re-generate.
>
> --- 2008-02-13/opcodes/i386-opc.tbl 2008-02-13 11:13:38.000000000 +0100
> +++ 2008-02-13/opcodes/i386-opc.tbl 2008-02-21 16:56:08.000000000 +0100
> @@ -322,17 +322,17 @@ call, 1, 0xff, 0x2, 1, Cpu64, Modrm|Defa
> // Intel Syntax
> call, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
> // Intel Syntax
> -call, 1, 0xff, 0x3, 1, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute }
> +call, 1, 0xff, 0x3, 1, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute }
> lcall, 2, 0x9a, None, 1, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
> -lcall, 1, 0xff, 0x3, 1, 0, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute }
> +lcall, 1, 0xff, 0x3, 1, 0, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute }
>
> jmp, 1, 0xeb, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 }
> jmp, 1, 0xff, 0x4, 1, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|JumpAbsolute }
> -jmp, 1, 0xff, 0x4, 1, Cpu64, Modrm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
> +jmp, 1, 0xff, 0x4, 1, Cpu64, Modrm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|JumpAbsolute }
> // Intel Syntax.
> jmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
> // Intel Syntax.
> -jmp, 1, 0xff, 0x5, 1, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute }
> +jmp, 1, 0xff, 0x5, 1, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute }
> ljmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm16|Imm32 }
> ljmp, 1, 0xff, 0x5, 1, 0, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute }
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