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powerpc_opcodes ordering
- From: Alan Modra <amodra at bigpond dot net dot au>
- To: binutils at sourceware dot org
- Date: Fri, 7 Mar 2008 09:33:19 +1030
- Subject: powerpc_opcodes ordering
This patch orders and formats powerpc_opcodes. I started the ordering
exercise to verify the comment above some PPCEFS instructions:
/* Some of these conflict with AltiVec, so move them before, since
PPCVEC includes the PPC_OPCODE_PPC set. */
Instead, I found this to be a false assertion. With the table better
ordered, it's much easier to see opcode conflicts, especially when the
opcode uses different macros. For example, the following two
instructions have identical opcodes:
{"macchwso", XO (4, 236,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, {RS, RA, RB}},
opcodes/
* ppc-opc.c (powerpc_opcodes): Order and format.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Tidy. Add code to test
for strict ordering of powerpc_opcodes, but disable for now.
Note: diff -w so the ordering changes can be seen.
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.103
diff -u -p -w -r1.103 ppc-opc.c
--- opcodes/ppc-opc.c 29 Jan 2008 08:24:43 -0000 1.103
+++ opcodes/ppc-opc.c 6 Mar 2008 22:30:12 -0000
@@ -1693,8 +1693,11 @@ extract_tbr (unsigned long insn,
The disassembler reads the table in order and prints the first
instruction which matches, so this table is sorted to put more
- specific instructions before more general instructions. It is also
- sorted by major opcode. */
+ specific instructions before more general instructions.
+
+ This table must be sorted by major opcode. Please try to keep it
+ vaguely sorted within major opcode too, except of course where
+ constrained otherwise by disassembler operation. */
const struct powerpc_opcode powerpc_opcodes[] = {
{ "attn", X(0,256), X_MASK, POWER4, { 0 } },
@@ -1745,589 +1748,558 @@ const struct powerpc_opcode powerpc_opco
{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
-{ "dcbz_l", X(4,1014), XRT_MASK, PPCPS, { RA, RB } },
{ "ps_cmpu0", X(4 ,0), X_MASK|(3<<21),PPCPS, { BF, FRA, FRB } },
+{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vrlb", VX (4, 4), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, {VD, VA, VB}},
{ "psq_lx", XW(4,6,0), XW_MASK, PPCPS, { FRT, RA, RB, PSWM, PSQM } },
+{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, {VD, VA, VB}},
{ "psq_stx", XW(4,7,0), XW_MASK, PPCPS, { FRS, RA, RB, PSWM, PSQM } },
+{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"mulhhwu", XRC(4, 8,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"mulhhwu.", XRC(4, 8,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
{ "ps_sum0", A(4 ,10,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
{ "ps_sum0.", A(4 ,10,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
{ "ps_sum1", A(4 ,11,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
{ "ps_sum1.", A(4 ,11,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
{ "ps_muls0", A(4 ,12,0), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
+{"machhwu", XO (4, 12,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{ "ps_muls0.", A(4 ,12,1), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
+{"machhwu.", XO (4, 12,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{ "ps_muls1", A(4 ,13,0), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
{ "ps_muls1.", A(4 ,13,1), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
{ "ps_madds0", A(4 ,14,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
{ "ps_madds0.", A(4 ,14,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
{ "ps_madds1", A(4 ,15,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
{ "ps_madds1.", A(4 ,15,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
+{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
+{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
{ "ps_div", A(4,18,0), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
{ "ps_div.", A(4,18,1), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
+{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
+{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
{ "ps_sub", A(4,20,0), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
{ "ps_sub.", A(4,20,1), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
{ "ps_add", A(4,21,0), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
{ "ps_add.", A(4,21,1), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, {VD, VA, VB, VC}},
+{"vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, {VD, VA, VB, SHB}},
{ "ps_sel", A(4,23,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, {VD, VA, VC, VB}},
{ "ps_sel.", A(4,23,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, {VD, VA, VC, VB}},
{ "ps_res", A(4,24,0), AFRAFRC_MASK, PPCPS, { FRT, FRB } },
{ "ps_res.", A(4,24,1), AFRAFRC_MASK, PPCPS, { FRT, FRB } },
{ "ps_mul", A(4,25,0), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
{ "ps_mul.", A(4,25,1), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
{ "ps_rsqrte", A(4 ,26,0), AFRAFRC_MASK, PPCPS, { FRT, FRB } },
{ "ps_rsqrte.", A(4 ,26,1), AFRAFRC_MASK, PPCPS, { FRT, FRB } },
-{ "ps_madd", A(4,29,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
-{ "ps_madd.", A(4,29,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
{ "ps_msub", A(4,28,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
{ "ps_msub.", A(4,28,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{"ps_madd", A (4, 29,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
+{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}},
{ "ps_nmsub", A(4,30,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
{ "ps_nmsub.", A(4,30,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
{ "ps_nmadd", A(4,31,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
{ "ps_nmadd.", A(4,31,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
{ "ps_cmpo0", X(4 ,32), X_MASK|(3<<21),PPCPS, { BF, FRA, FRB } },
+{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vrlh", VX (4, 68), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, {VD, VA, VB}},
{ "psq_lux", XW(4,38,0), XW_MASK, PPCPS, { FRT, RA, RB, PSWM, PSQM } },
+{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, {VD, VA, VB}},
{ "psq_stux", XW(4,39,0), XW_MASK, PPCPS, { FRS, RA, RB, PSWM, PSQM } },
+{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, {VD, VA, VB}},
{ "ps_neg", XRC(4 ,40,0), XRA_MASK, PPCPS, { FRT, FRB } },
+{"mulhhw", XRC(4, 40,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
{ "ps_neg.", XRC(4 ,40,1), XRA_MASK, PPCPS, { FRT, FRB } },
+{"mulhhw.", XRC(4, 40,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"machhw", XO (4, 44,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"machhw.", XO (4, 44,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmachhw", XO (4, 46,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmachhw.", XO (4, 46,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{ "ps_cmpu1", X(4 ,64), X_MASK|(3<<21), PPCPS, { BF, FRA, FRB } },
+{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vrlw", VX (4, 132), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, {VD, VA, VB}},
{ "ps_mr", XRC(4 ,72,0), XRA_MASK, PPCPS, { FRT, FRB } },
{ "ps_mr.", XRC(4 ,72,1), XRA_MASK, PPCPS, { FRT, FRB } },
+{"machhwsu", XO (4, 76,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"machhwsu.", XO (4, 76,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{ "ps_cmpo1", X(4 ,96), X_MASK|(3<<21), PPCPS, { BF, FRA, FRB } },
+{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"machhws", XO (4, 108,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"machhws.", XO (4, 108,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmachhws", XO (4, 110,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmachhws.", XO (4, 110,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vslb", VX (4, 260), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vrefp", VX (4, 266), VX_MASK, PPCVEC, {VD, VB}},
+{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, {VD, VA, VB}},
{ "ps_nabs", XRC(4 ,136,0), XRA_MASK, PPCPS, { FRT, FRB } },
+{"mulchwu", XRC(4, 136,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
{ "ps_nabs.", XRC(4 ,136,1), XRA_MASK, PPCPS, { FRT, FRB } },
-{ "ps_abs", XRC(4,264,0), XRA_MASK, PPCPS, { FRT, FRB } },
-{ "ps_abs.", XRC(4,264,1), XRA_MASK, PPCPS, { FRT, FRB } },
-{ "ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
-{ "ps_merge00.",XOPS(4,528,1), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
-{ "ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
-{ "ps_merge01.",XOPS(4,560,1), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
-{ "ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
-{ "ps_merge10.",XOPS(4,592,1), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
-{ "ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
-{ "ps_merge11.",XOPS(4,624,1), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
-{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{"mulchwu.", XRC(4, 136,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
+{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vslh", VX (4, 324), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vrsqrtefp", VX (4, 330), VX_MASK, PPCVEC, {VD, VB}},
+{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, {VD, VA, VB}},
{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
+{"macchw", XO (4, 172,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"macchw.", XO (4, 172,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
-{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
-
- /* Double-precision opcodes. */
- /* Some of these conflict with AltiVec, so move them before, since
- PPCVEC includes the PPC_OPCODE_PPC set. */
-{ "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
-{ "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
-{ "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
-{ "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
-{ "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
-{ "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
-{ "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
-{ "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
- /* End of double-precision opcodes. */
-
{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
-{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
-{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
-{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
+{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vslw", VX (4, 388), VX_MASK, PPCVEC, {VD, VA, VB}},
{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
+{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"macchwsu", XO (4, 204,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"macchwsu.", XO (4, 204,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"vsl", VX (4, 452), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
-{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
-{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
-{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
-{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
-{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
-{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
-{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
-{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
-{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
-{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
-{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
-{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
-{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
-{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
-{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
-{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
-{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
-{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
-{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
-{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
-{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
-{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
-
+{"macchws", XO (4, 236,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"macchws.", XO (4, 236,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmacchws", XO (4, 238,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmacchws.", XO (4, 238,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
+{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, {VD, VA, VB}},
{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
+{"vminub", VX (4, 514), VX_MASK, PPCVEC, {VD, VA, VB}},
{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
+{"vsrb", VX (4, 516), VX_MASK, PPCVEC, {VD, VA, VB}},
{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
+{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
+{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, {VD, VA, VB}},
{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
+{"vrfin", VX (4, 522), VX_MASK, PPCVEC, {VD, VB}},
{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
+{"vspltb", VX (4, 524), VX_MASK, PPCVEC, {VD, VB, UIMM}},
{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
-
+{"vupkhsb", VX (4, 526), VX_MASK, PPCVEC, {VD, VB}},
{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
-
+{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, {FRT, FRB}},
+{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, {FRT, FRB}},
{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
+{"evxor", VX (4, 534), VX_MASK, PPCSPE, {RS, RA, RB}},
{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
+{"evnor", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evnot", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, BBA}},
{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
+{"evorc", VX (4, 539), VX_MASK, PPCSPE, {RS, RA, RB}},
{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
-{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
-{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
-{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
+{"evsrws", VX (4, 545), VX_MASK, PPCSPE, {RS, RA, RB}},
{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
+{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, {RS, RA, EVUIMM}},
+{"evslw", VX (4, 548), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evslwi", VX (4, 550), VX_MASK, PPCSPE, {RS, RA, EVUIMM}},
+{"evrlw", VX (4, 552), VX_MASK, PPCSPE, {RS, RA, RB}},
{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
+{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, {RS, RA, EVUIMM}},
{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
+{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, {CRFD, RA, RB}},
{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
+{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, {CRFD, RA, RB}},
{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
+{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vminuh", VX (4, 578), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vsrh", VX (4, 580), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vrfiz", VX (4, 586), VX_MASK, PPCVEC, {VD, VB}},
+{"vsplth", VX (4, 588), VX_MASK, PPCVEC, {VD, VB, UIMM}},
+{"vupkhsh", VX (4, 590), VX_MASK, PPCVEC, {VD, VB}},
{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
-
-{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
-{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
-{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
-{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
-{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
-{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
-{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
-{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
-{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
-{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
-
+{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vadduws", VX (4, 640), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"evfssub", VX (4, 641), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vminuw", VX (4, 642), VX_MASK, PPCVEC, {VD, VA, VB}},
{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
+{"vsrw", VX (4, 644), VX_MASK, PPCVEC, {VD, VA, VB}},
{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
-{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
+{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
+{"vrfip", VX (4, 650), VX_MASK, PPCVEC, {VD, VB}},
{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
+{"vspltw", VX (4, 652), VX_MASK, PPCVEC, {VD, VB, UIMM}},
{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
+{"vupklsb", VX (4, 654), VX_MASK, PPCVEC, {VD, VB}},
{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
-{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
-{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
-
+{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, {RS, RB}},
+{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, {RS, RB}},
+{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, {CRFD, RA, RB}},
+{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, {CRFD, RA, RB}},
+{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, {CRFD, RA, RB}},
+{"efsadd", VX (4, 704), VX_MASK, PPCEFS, {RS, RA, RB}},
+{"efssub", VX (4, 705), VX_MASK, PPCEFS, {RS, RA, RB}},
{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
+{"vsr", VX (4, 708), VX_MASK, PPCVEC, {VD, VA, VB}},
{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
-{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
-{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
+{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
+{"vrfim", VX (4, 714), VX_MASK, PPCVEC, {VD, VB}},
{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
+{"vupklsh", VX (4, 718), VX_MASK, PPCVEC, {VD, VB}},
+{"efscfd", VX (4, 719), VX_MASK, PPCEFS, {RS, RB}},
{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
-{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
-{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
-
-{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
-
+{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, {RS, RB}},
+{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, {RS, RB}},
+{"efststgt", VX (4, 732), VX_MASK, PPCEFS, {CRFD, RA, RB}},
+{"efststlt", VX (4, 733), VX_MASK, PPCEFS, {CRFD, RA, RB}},
+{"efststeq", VX (4, 734), VX_MASK, PPCEFS, {CRFD, RA, RB}},
+{"efdadd", VX (4, 736), VX_MASK, PPCEFS, {RS, RA, RB}},
+{"efdsub", VX (4, 737), VX_MASK, PPCEFS, {RS, RA, RB}},
+{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, {RS, RB}},
+{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, {RS, RB}},
+{"efdabs", VX (4, 740), VX_MASK, PPCEFS, {RS, RA}},
+{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, {RS, RA}},
+{"efdneg", VX (4, 742), VX_MASK, PPCEFS, {RS, RA}},
+{"efdmul", VX (4, 744), VX_MASK, PPCEFS, {RS, RA, RB}},
+{"efddiv", VX (4, 745), VX_MASK, PPCEFS, {RS, RA, RB}},
+{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, {RS, RB}},
+{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, {RS, RB}},
+{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, {CRFD, RA, RB}},
+{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, {CRFD, RA, RB}},
+{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, {CRFD, RA, RB}},
+{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, {RS, RB}},
+{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, {RS, RB}},
+{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, {RS, RB}},
+{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, {RS, RB}},
+{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, {RS, RB}},
+{"efdctui", VX (4, 756), VX_MASK, PPCEFS, {RS, RB}},
+{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, {RS, RB}},
+{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, {RS, RB}},
+{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, {RS, RB}},
+{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, {RS, RB}},
+{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, {RS, RB}},
+{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, {CRFD, RA, RB}},
+{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, {CRFD, RA, RB}},
+{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, {CRFD, RA, RB}},
+{"evlddx", VX (4, 768), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"evldd", VX (4, 769), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
+{"evldwx", VX (4, 770), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vminsb", VX (4, 770), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"evldw", VX (4, 771), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
+{"evldhx", VX (4, 772), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vsrab", VX (4, 772), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"evldh", VX (4, 773), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
+{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}},
+{"vcfux", VX (4, 778), VX_MASK, PPCVEC, {VD, VB, UIMM}},
+{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vspltisb", VX (4, 780), VX_MASK, PPCVEC, {VD, SIMM}},
+{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}},
+{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}},
+{"mullhwu", XRC(4, 392,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"mullhwu.", XRC(4, 392,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
+{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
+{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
+{"maclhwu", XO (4, 396,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"maclhwu.", XO (4, 396,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
+{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
+{"evstddx", VX (4, 800), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evstdd", VX (4, 801), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
+{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evstdw", VX (4, 803), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
+{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evstdh", VX (4, 805), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}},
+{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
+{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evstwho", VX (4, 821), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
+{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
+{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}},
+{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vminsh", VX (4, 834), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vsrah", VX (4, 836), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, {VD, VB, UIMM}},
+{"vspltish", VX (4, 844), VX_MASK, PPCVEC, {VD, SIMM}},
+{"vupkhpx", VX (4, 846), VX_MASK, PPCVEC, {VD, VB}},
+{"mullhw", XRC(4, 424,0), X_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"mullhw.", XRC(4, 424,1), X_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"maclhw", XO (4, 428,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"maclhw.", XO (4, 428,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmaclhw", XO (4, 430,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmaclhw.", XO (4, 430,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vminsw", VX (4, 898), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vsraw", VX (4, 900), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, {VD, VB, UIMM}},
+{"vspltisw", VX (4, 908), VX_MASK, PPCVEC, {VD, SIMM}},
+{"maclhwsu", XO (4, 460,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"maclhwsu.", XO (4, 460,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, {VD, VB, UIMM}},
+{"vupklpx", VX (4, 974), VX_MASK, PPCVEC, {VD, VB}},
+{"maclhws", XO (4, 492,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"maclhws.", XO (4, 492,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmaclhws", XO (4, 494,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmaclhws.", XO (4, 494,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"vsububm", VX (4,1024), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vavgub", VX (4,1026), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vand", VX (4,1028), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vslo", VX (4,1036), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"machhwuo", XO (4, 12,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"machhwuo.", XO (4, 12,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
+{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
+{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vavguh", VX (4,1090), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vandc", VX (4,1092), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
-
{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
-
+{"vminfp", VX (4,1098), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vsro", VX (4,1100), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, {RS, RA, RB}},
{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
+{"machhwo", XO (4, 44,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
+{"machhwo.", XO (4, 44,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"nmachhwo", XO (4, 46,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmachhwo.", XO (4, 46,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
+{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
+{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, {RS, RA, RB}},
{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
-{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
+{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vavguw", VX (4,1154), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vor", VX (4,1156), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"machhwsuo", XO (4, 76,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"machhwsuo.", XO (4, 76,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
+{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
-{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
-
-{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
-{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
+{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, {RS, RA}},
{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
-{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
-
+{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, {RS, RA}},
{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
-
+{"vxor", VX (4,1220), VX_MASK, PPCVEC, {VD, VA, VB}},
{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
+{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
+{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, {RS, RA}},
+{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, {RS, RA}},
+{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, {RS, RA}},
+{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, {RS, RA}},
+{"machhwso", XO (4, 108,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"machhwso.", XO (4, 108,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmachhwso", XO (4, 110,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmachhwso.", XO (4, 110,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
+{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}},
+{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vnor", VX (4,1284), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"macchwuo", XO (4, 140,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"macchwuo.", XO (4, 140,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"macchwo", XO (4, 172,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"macchwo.", XO (4, 172,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"nmacchwo", XO (4, 174,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmacchwo.", XO (4, 174,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"macchwsuo", XO (4, 204,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"macchwsuo.", XO (4, 204,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"macchwso", XO (4, 236,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"macchwso.", XO (4, 236,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, {RS, RA, RB}},
+{"nmacchwso", XO (4, 238,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmacchwso.", XO (4, 238,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"vsububs", VX (4,1536), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"mfvscr", VX (4,1540), VX_MASK, PPCVEC, {VD}},
+{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"mtvscr", VX (4,1604), VX_MASK, PPCVEC, {VB}},
+{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"maclhwuo", XO (4, 396,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"maclhwuo.", XO (4, 396,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"maclhwo", XO (4, 428,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"maclhwo.", XO (4, 428,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmaclhwo", XO (4, 430,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmaclhwo.", XO (4, 430,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, {VD, VA, VB}},
+{"maclhwsuo", XO (4, 460,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"maclhwsuo.", XO (4, 460,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, {VD, VA, VB}},
+{"maclhwso", XO (4, 492,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"maclhwso.", XO (4, 492,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmaclhwso", XO (4, 494,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}},
+{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, {RA, RB}},
{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
@@ -2401,111 +2373,52 @@ const struct powerpc_opcode powerpc_opco
{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
-{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
-{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
-{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
-{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
-{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
-{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
-{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
-{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
-{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
-{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
-{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
-{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
-{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
-{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
+
{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
-{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
-{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
+{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
+{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
+{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}},
{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
+{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
+{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
+{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
+{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
+{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
+{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
-{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
-{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
-{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
+{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
+{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
+{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}},
{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
+{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
+{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
+{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
+{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
+{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
+{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
@@ -2524,39 +2437,89 @@ const struct powerpc_opcode powerpc_opco
{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
-{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
-{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
+{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
+{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
+{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, {CR, BD}},
{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
+{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
+{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
+{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, {CR, BDA}},
{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
+{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
+{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
+{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, {CR, BDA}},
{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
-{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
-{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
-{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
-{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
-{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
-{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
-{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
-{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
-{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
-{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
-{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
-{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
+
+{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
+{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
+{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}},
+{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
+{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
+{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}},
+{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
+{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
+{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
+{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
+{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
+{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
+{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
+{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
+{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}},
+{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
+{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
+{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}},
+{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
+{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
+{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}},
+{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
+{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
+{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}},
+{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
+{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
+{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, {CR, BD}},
+{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
+{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
+{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, {CR, BD}},
+{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
+{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
+{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, {CR, BDA}},
+{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
+{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
+{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, {CR, BDA}},
+{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
+{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
+{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, {CR, BD}},
+{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}},
+{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}},
+{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BD}},
+{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
+{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
+{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, {CR, BD}},
+{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}},
+{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}},
+{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BD}},
+{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
+{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
+{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, {CR, BDA}},
+{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
+{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
+{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDA}},
+{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
+{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
+{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, {CR, BDA}},
+{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}},
+{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}},
+{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDA}},
+
{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
@@ -2569,22 +2532,19 @@ const struct powerpc_opcode powerpc_opco
{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
-{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
-{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
-{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
-{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
-{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
-{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
-{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
-{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
-{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
-{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
-{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
-{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
-{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
-{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
-{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
-{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
+{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}},
+{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}},
+{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, {BI, BD}},
+{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}},
+{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}},
+{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, {BI, BD}},
+{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}},
+{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}},
+{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, {BI, BDA}},
+{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}},
+{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}},
+{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, {BI, BDA}},
+
{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
@@ -2601,6 +2561,19 @@ const struct powerpc_opcode powerpc_opco
{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
+
+{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}},
+{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}},
+{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, {BI, BD}},
+{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}},
+{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}},
+{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, {BI, BD}},
+{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}},
+{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}},
+{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, {BI, BDA}},
+{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}},
+{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}},
+{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, {BI, BDA}},
{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
@@ -2611,20 +2584,26 @@ const struct powerpc_opcode powerpc_opco
{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
-{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
-{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
-{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
-{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
-{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
-{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
-{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
-{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
-{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
-{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
-{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
-{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
-{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
-{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
+{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}},
+{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, {BI, BDA}},
+
+{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BDM}},
+{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BDP}},
+{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BD}},
+{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, {BI, BD}},
+{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BDM}},
+{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BDP}},
+{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BD}},
+{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, {BI, BD}},
+{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDMA}},
+{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDPA}},
+{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDA}},
+{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, {BI, BDA}},
+{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDMA}},
+{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDPA}},
+{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDA}},
+{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, {BI, BDA}},
+
{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
@@ -2638,9 +2617,9 @@ const struct powerpc_opcode powerpc_opco
{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
-{ "sc", SC(17,1,0), SC_MASK, PPC, { LEV } },
{ "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
{ "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
+{"sc", SC(17,1,0), SC_MASK, PPC, {LEV}},
{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
@@ -2651,226 +2630,230 @@ const struct powerpc_opcode powerpc_opco
{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
-{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
-{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
-{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
-{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
-{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
+{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, {0}},
{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
-{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
+{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, {0}},
{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
+{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, {0}},
+{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, {0}},
+{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, {0}},
+{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, {0}},
+{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, {0}},
+{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, {0}},
+{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, {0}},
+{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, {0}},
+{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, {0}},
+{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, {0}},
+{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, {0}},
{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
-{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+
{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
+{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
+{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
+{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
-{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
-{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
-{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
-{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
-{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
-{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
-{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
+{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
+{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
+{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
+{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
+{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
+{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
+{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, {CR}},
+{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, {CR}},
+{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}},
+
+{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, {BI}},
+{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
+{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, {BI}},
+{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
+{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
+{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
+{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, {BI}},
+{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
+{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, {BI}},
+{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
+{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
+{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
-{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
+{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, {BI}},
+{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
+{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, {BI}},
+{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, {BI}},
+{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, {BI}},
{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
-{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
+{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
-{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
-{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
+{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
-{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
-{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
-{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
+{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, {BI}},
+{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
+{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, {BI}},
+{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, {BI}},
+{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
+{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, {BI}},
+{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}},
+{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}},
+{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, {BI}},
+{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, {BI}},
+{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, {BI}},
+{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, {BI}},
+
{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
+{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, {BOE, BI}},
+{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, {BOE, BI}},
{ "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
-{ "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
+{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, {BO, BI, BH}},
{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
+
{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
@@ -2916,154 +2899,158 @@ const struct powerpc_opcode powerpc_opco
{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
-{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+
{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
-{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
-{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
-{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
-{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
-{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
+{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}},
+{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}},
+{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}},
+{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}},
+
{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
-{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
+{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, {BI}},
{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
+{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, {BI}},
+{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, {BI}},
+{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, {BI}},
{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
+{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, {BI}},
+{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, {BI}},
+{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, {BI}},
+{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, {BI}},
+{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, {BI}},
+{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, {BI}},
+{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, {BI}},
+{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, {BI}},
+{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, {BI}},
+{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, {BI}},
+
{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
-{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
+{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, {BOE, BI}},
{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
{ "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
-{ "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
+{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, {BO, BI, BH}},
{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
+
{ "bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, { BO, BI } },
{ "bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, { BO, BI } },
@@ -3083,10 +3070,9 @@ const struct powerpc_opcode powerpc_opco
{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
-{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
-
{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
+{"rlmi.", M(22,1), M_MASK, M601, {RA, RS, RB, MBE, ME}},
{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
@@ -3177,18 +3163,15 @@ const struct powerpc_opcode powerpc_opco
{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
+{"lvsl", X(31,6), X_MASK, PPCVEC, {VD, RA, RB}},
+{"lvebx", X(31,7), X_MASK, PPCVEC, {VD, RA, RB}},
+
{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
-{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
-{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
@@ -3197,29 +3180,21 @@ const struct powerpc_opcode powerpc_opco
{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
-{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
-{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
-{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
+{"mfcr", XFXM(31,19,0,0), XRARB_MASK, NOPOWER4|COM, {RT}},
+{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, {RT, FXM4}},
{ "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
-{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } },
-{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
{ "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
{ "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } },
-{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
@@ -3252,14 +3227,21 @@ const struct powerpc_opcode powerpc_opco
{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
+{"lvsr", X(31,38), X_MASK, PPCVEC, {VD, RA, RB}},
+{"lvehx", X(31,39), X_MASK, PPCVEC, {VD, RA, RB}},
+
+{"iselgt", X(31,47), X_MASK, PPCISEL, {RT, RA, RB}},
+
+{"lvewx", X(31,71), X_MASK, PPCVEC, {VD, RA, RB}},
+
+{"iseleq", X(31,79), X_MASK, PPCISEL, {RT, RA, RB}},
+
+{"isel", XISEL(31,15), XISEL_MASK, PPCISEL, {RT, RA, RB, CRB}},
+
{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
-{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
-{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
-{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
-{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
@@ -3268,16 +3250,16 @@ const struct powerpc_opcode powerpc_opco
{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
-{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
-
-{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
-
{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
+{"dcbste", X(31,62), XRT_MASK, BOOKE64, {RA, RB}},
+
+{"lwzuxe", X(31,63), X_MASK, BOOKE64, {RT, RAL, RB}},
+
{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
@@ -3318,15 +3300,13 @@ const struct powerpc_opcode powerpc_opco
{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
+{"lvx", X(31,103), X_MASK, PPCVEC, {VD, RA, RB}},
+
{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
-{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
-{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
-{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
-{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
@@ -3349,29 +3329,23 @@ const struct powerpc_opcode powerpc_opco
{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
+{"stvebx", X(31,135), X_MASK, PPCVEC, {VS, RA, RB}},
+
{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
-{ "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
{ "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
-{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
+{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, {FXM, RS}},
+{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, {FXM, RS}},
{ "mtmsr", X(31,146), XRLARB_MASK, COM, { RS, A_L } },
@@ -3382,10 +3356,6 @@ const struct powerpc_opcode powerpc_opco
{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
-{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
-
-{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
-
{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
@@ -3394,9 +3364,16 @@ const struct powerpc_opcode powerpc_opco
{ "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } },
+{"stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, {RS, RA0, RB}},
+
+{"stwxe", X(31,159), X_MASK, BOOKE64, {RS, RA0, RB}},
+
{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
+
+{"stvehx", X(31,167), X_MASK, PPCVEC, {VS, RA, RB}},
+
{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } },
@@ -3413,23 +3390,17 @@ const struct powerpc_opcode powerpc_opco
{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
+{"stvewx", X(31,199), X_MASK, PPCVEC, {VS, RA, RB}},
+
{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
-{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
-{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
-{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
-{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
-{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
-{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
-{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
-{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
@@ -3447,37 +3418,25 @@ const struct powerpc_opcode powerpc_opco
{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
+{"stvx", X(31,231), X_MASK, PPCVEC, {VS, RA, RB}},
+
{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
-{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
-{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
-{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
-{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
-{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
-{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
-{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
-{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
-{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
-{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
@@ -3496,19 +3455,15 @@ const struct powerpc_opcode powerpc_opco
{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
+{"icbt", X(31,262), XRT_MASK, PPC403, {RA, RB}},
+
{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
-{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
-{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
{ "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
@@ -3578,8 +3533,6 @@ const struct powerpc_opcode powerpc_opco
{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
-{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
-{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
@@ -3588,25 +3541,22 @@ const struct powerpc_opcode powerpc_opco
{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
-{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
+{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, {RT}},
{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
{ "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } },
{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
-{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
-{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
-{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
@@ -3626,52 +3576,36 @@ const struct powerpc_opcode powerpc_opco
{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
-{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
+{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, {RT, SPRG}},
+{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, {RT}},
+{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, {RT}},
+{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, {RT}},
+{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, {RT}},
{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
-{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
-{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
-{ "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
-{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
-{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
-{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
-{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
-{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
-{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
-{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
-{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
-{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
-{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
-{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
-{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
-{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
-{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
-{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
-{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
-{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
@@ -3692,11 +3626,11 @@ const struct powerpc_opcode powerpc_opco
{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
+{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, {RT, SPRBAT}},
{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
+{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, {RT, SPRBAT}},
{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
-{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
-{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
@@ -3704,8 +3638,8 @@ const struct powerpc_opcode powerpc_opco
{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
-{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
+{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, {RT}},
{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
@@ -3739,26 +3673,42 @@ const struct powerpc_opcode powerpc_opco
{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
+{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, {RT}},
{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
+{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, {RT}},
+{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, {RT}},
+{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, {RT}},
+{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, {RT}},
{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
-{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
+{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, {RT}},
{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
+{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, {RT}},
{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
+{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, {RT}},
+{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, {RT}},
{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
+{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, {RT}},
+{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, {RT}},
{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
+{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, {RT}},
+{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, {RT}},
+{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, {RT}},
+{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, {RT}},
+{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, {RT}},
+{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, {RT}},
{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
@@ -3775,31 +3725,29 @@ const struct powerpc_opcode powerpc_opco
{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
-{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
{ "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
-{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
-{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
-
-{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
+{"lvxl", X(31,359), X_MASK, PPCVEC, {VD, RA, RB}},
{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
-{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
-{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
-{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
-{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
+{"mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, {RT}},
+{"mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, {RT}},
+{"mftb", X(31,371), X_MASK, CLASSIC, {RT, TBR}},
+
{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
+{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, {RA, RB, STRM}},
+
{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
@@ -3809,10 +3757,8 @@ const struct powerpc_opcode powerpc_opco
{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
-{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
-{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
@@ -3820,26 +3766,9 @@ const struct powerpc_opcode powerpc_opco
{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
-{ "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
-
-{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
-
-{ "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
-
-{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
-
-{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
-
-{ "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
-
-{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
-
{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
-{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
-{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
-
{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
@@ -3847,21 +3776,14 @@ const struct powerpc_opcode powerpc_opco
{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
-
-{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
-
-{ "cctpl", 0x7c210b78, 0xffffffff, CELL, { 0 }},
-{ "cctpm", 0x7c421378, 0xffffffff, CELL, { 0 }},
-{ "cctph", 0x7c631b78, 0xffffffff, CELL, { 0 }},
-{ "db8cyc", 0x7f9ce378, 0xffffffff, CELL, { 0 }},
-{ "db10cyc", 0x7fbdeb78, 0xffffffff, CELL, { 0 }},
-{ "db12cyc", 0x7fdef378, 0xffffffff, CELL, { 0 }},
-{ "db16cyc", 0x7ffffb78, 0xffffffff, CELL, { 0 }},
+
{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
+{"sthuxe", X(31,447), X_MASK, BOOKE64, {RS, RAS, RB}},
+
{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
@@ -3898,21 +3820,19 @@ const struct powerpc_opcode powerpc_opco
{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
+{"dccci", X(31,454), XRT_MASK, PPC403|PPC440, {RA, RB}},
+
{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
-{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
-{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
-{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
-{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
-{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
-{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
+
+{"mtpmr", X(31,462), X_MASK, PPCPMR, {PMR, RS}},
{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
@@ -3930,14 +3850,11 @@ const struct powerpc_opcode powerpc_opco
{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
{ "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } },
{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
-{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
-{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
-{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
@@ -3971,32 +3888,19 @@ const struct powerpc_opcode powerpc_opco
{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
-{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
-{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
-{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
-{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
-{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
-{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
-{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
-{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
-{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
-{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
-{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
-{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
-{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
@@ -4017,11 +3921,11 @@ const struct powerpc_opcode powerpc_opco
{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
+{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, {SPRBAT, RS}},
{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
+{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, {SPRBAT, RS}},
{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
-{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
-{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
@@ -4035,26 +3939,42 @@ const struct powerpc_opcode powerpc_opco
{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
+{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, {RS}},
{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
+{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, {RS}},
+{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, {RS}},
+{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, {RS}},
+{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, {RS}},
{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
-{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
+{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, {RS}},
{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
-{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
-{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
+{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, {RS}},
{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
+{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, {RS}},
+{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, {RS}},
{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
+{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, {RS}},
+{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, {RS}},
{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
+{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, {RS}},
+{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, {RS}},
{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
+{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, {RS}},
+{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, {RS}},
+{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, {RS}},
+{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, {RS}},
+{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, {RS}},
+{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, {RS}},
{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
@@ -4077,29 +3997,21 @@ const struct powerpc_opcode powerpc_opco
{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
-{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
-
{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
+{"stvxl", X(31,487), X_MASK, PPCVEC, {VS, RA, RB}},
+
{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
-{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
-{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
-{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
-{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
-{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
-{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
-{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
-{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
@@ -4107,12 +4019,27 @@ const struct powerpc_opcode powerpc_opco
{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
+{"cmpb", X(31,508), X_MASK, POWER6, {RA, RS, RB}},
+
{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
-{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
+
+{"lvlx", X(31,519), X_MASK, CELL, {VD, RA0, RB}},
+
+{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
+{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
+{"subco", XO(31,8,1,0), XO_MASK, PPC, {RT, RB, RA}},
+{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
+{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
+{"subco.", XO(31,8,1,1), XO_MASK, PPC, {RT, RB, RA}},
+
+{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
+{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
+{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
+{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
@@ -4144,8 +4071,17 @@ const struct powerpc_opcode powerpc_opco
{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
+{"mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, {BF}},
+
{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
+{"lvrx", X(31,551), X_MASK, CELL, {VD, RA0, RB}},
+
+{"subfo", XO(31,40,1,0), XO_MASK, PPC, {RT, RA, RB}},
+{"subo", XO(31,40,1,0), XO_MASK, PPC, {RT, RB, RA}},
+{"subfo.", XO(31,40,1,1), XO_MASK, PPC, {RT, RA, RB}},
+{"subo.", XO(31,40,1,1), XO_MASK, PPC, {RT, RB, RA}},
+
{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
@@ -4157,18 +4093,23 @@ const struct powerpc_opcode powerpc_opco
{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
+{"msync", X(31,598), 0xffffffff, BOOKE, {0}},
{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
-{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
-
{ "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } },
+{"nego", XO(31,104,1,0), XORB_MASK, COM, {RT, RA}},
+{"nego.", XO(31,104,1,1), XORB_MASK, COM, {RT, RA}},
+
+{"mulo", XO(31,107,1,0), XO_MASK, M601, {RT, RA, RB}},
+{"mulo.", XO(31,107,1,1), XO_MASK, M601, {RT, RA, RB}},
+
{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
@@ -4177,6 +4118,18 @@ const struct powerpc_opcode powerpc_opco
{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
+{"stvlx", X(31,647), X_MASK, CELL, {VS, RA0, RB}},
+
+{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
+{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
+{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
+{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
+
+{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
+{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
+{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
+{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
+
{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
{ "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
@@ -4199,6 +4152,8 @@ const struct powerpc_opcode powerpc_opco
{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
+{"stvrx", X(31,679), X_MASK, CELL, {VS, RA0, RB}},
+
{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
@@ -4206,6 +4161,16 @@ const struct powerpc_opcode powerpc_opco
{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
+{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, {RT, RA}},
+{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, {RT, RA}},
+{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, {RT, RA}},
+{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, {RT, RA}},
+
+{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, {RT, RA}},
+{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, {RT, RA}},
+{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, {RT, RA}},
+{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, {RT, RA}},
+
{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
@@ -4218,9 +4183,26 @@ const struct powerpc_opcode powerpc_opco
{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
-
{ "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } },
+{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, {RT, RA}},
+{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, {RT, RA}},
+{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, {RT, RA}},
+{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, {RT, RA}},
+
+{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, {RT, RA, RB}},
+{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, {RT, RA, RB}},
+
+{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, {RT, RA}},
+{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, {RT, RA}},
+{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, {RT, RA}},
+{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, {RT, RA}},
+
+{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
+{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
+{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
+{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
+
{ "dcba", X(31,758), XRT_MASK, PPC405 | PPC7450 | BOOKE, { RA, RB } },
{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
@@ -4232,6 +4214,16 @@ const struct powerpc_opcode powerpc_opco
{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
+{"lvlxl", X(31,775), X_MASK, CELL, {VD, RA0, RB}},
+
+{"dozo", XO(31,264,1,0), XO_MASK, M601, {RT, RA, RB}},
+{"dozo.", XO(31,264,1,1), XO_MASK, M601, {RT, RA, RB}},
+
+{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, {RT, RA, RB}},
+{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, {RT, RA, RB}},
+{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, {RT, RA, RB}},
+{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, {RT, RA, RB}},
+
{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
@@ -4239,6 +4231,9 @@ const struct powerpc_opcode powerpc_opco
{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
+{"lfqx", X(31,791), X_MASK, POWER2, {FRT, RA, RB}},
+{"lfdpx", X(31,791), X_MASK, POWER6, {FRT, RA, RB}},
+
{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
@@ -4250,20 +4245,29 @@ const struct powerpc_opcode powerpc_opco
{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
-{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
+
+{"lvrxl", X(31,807), X_MASK, CELL, {VD, RA0, RB}},
{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
{ "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
-{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
+
+{"lfqux", X(31,823), X_MASK, POWER2, {FRT, RA, RB}},
{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
+{"sradi", XS(31,413,0), XS_MASK, PPC64, {RA, RS, SH6}},
+{"sradi.", XS(31,413,1), XS_MASK, PPC64, {RA, RS, SH6}},
+
+{"divo", XO(31,331,1,0), XO_MASK, M601, {RT, RA, RB}},
+{"divo.", XO(31,331,1,1), XO_MASK, M601, {RT, RA, RB}},
+{"lduxe", X(31,831), X_MASK, BOOKE64, {RT, RA0, RB}},
+
{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
{ "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
@@ -4273,19 +4277,34 @@ const struct powerpc_opcode powerpc_opco
{ "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
+{"abso", XO(31,360,1,0), XORB_MASK, M601, {RT, RA}},
+{"abso.", XO(31,360,1,1), XORB_MASK, M601, {RT, RA}},
+
+{"divso", XO(31,363,1,0), XO_MASK, M601, {RT, RA, RB}},
+{"divso.", XO(31,363,1,1), XO_MASK, M601, {RT, RA, RB}},
+
{ "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
+{"stvlxl", X(31,903), X_MASK, CELL, {VS, RA0, RB}},
+
+{"subfe64o", XO(31,392,1,0), XO_MASK, BOOKE64, {RT, RA, RB}},
+
+{"adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, {RT, RA, RB}},
+
{ "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
+
{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RTO, RA, RB } },
{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RTO, RA, RB } },
-
{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
{ "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
+{"stfqx", X(31,919), X_MASK, POWER2, {FRS, RA, RB}},
+{"stfdpx", X(31,919), X_MASK, POWER6, {FRS, RA, RB}},
+
{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
@@ -4301,12 +4320,16 @@ const struct powerpc_opcode powerpc_opco
{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
+{"stvrxl", X(31,935), X_MASK, CELL, {VS, RA0, RB}},
+
{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
{ "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
{ "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
+{"stfqux", X(31,951), X_MASK, POWER2, {FRS, RA, RB}},
+
{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
@@ -4317,6 +4340,16 @@ const struct powerpc_opcode powerpc_opco
{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
+{"subfze64o", XO(31,456,1,0), XORB_MASK, BOOKE64, {RT, RA}},
+
+{"divduo", XO(31,457,1,0), XO_MASK, PPC64, {RT, RA, RB}},
+{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, {RT, RA, RB}},
+
+{"addze64o", XO(31,458,1,0), XORB_MASK, BOOKE64, {RT, RA}},
+
+{"divwuo", XO(31,459,1,0), XO_MASK, PPC, {RT, RA, RB}},
+{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, {RT, RA, RB}},
+
{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
@@ -4331,43 +4364,46 @@ const struct powerpc_opcode powerpc_opco
{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
-{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
-
{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
+{"icread", X(31,998), XRT_MASK, PPC403|PPC440, {RA, RB}},
+
+{"nabso", XO(31,488,1,0), XORB_MASK, M601, {RT, RA}},
+{"subfme64o", XO(31,488,1,0), XORB_MASK, BOOKE64, {RT, RA}},
+{"nabso.", XO(31,488,1,1), XORB_MASK, M601, {RT, RA}},
+
+{"divdo", XO(31,489,1,0), XO_MASK, PPC64, {RT, RA, RB}},
+{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, {RT, RA, RB}},
+
+{"addme64o", XO(31,490,1,0), XORB_MASK, BOOKE64, {RT, RA}},
+
+{"divwo", XO(31,491,1,0), XO_MASK, PPC, {RT, RA, RB}},
+{"divwo.", XO(31,491,1,1), XO_MASK, PPC, {RT, RA, RB}},
+
{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
{ "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
-{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
-{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
-{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
-{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
-{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
-{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
-{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
-{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
-{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
-{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
-{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
-{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
-{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
+{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4, {RA, RB}},
-/* New load/store left/right index vector instructions that are in the Cell only. */
-{ "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
-{ "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
-{ "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
-{ "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
-{ "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
-{ "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
-{ "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
-{ "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
+{"cctpl", 0x7c210b78, 0xffffffff, CELL, {0}},
+{"cctpm", 0x7c421378, 0xffffffff, CELL, {0}},
+{"cctph", 0x7c631b78, 0xffffffff, CELL, {0}},
+
+{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, {RA, RB, STRM}},
+{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, {RA, RB, STRM}},
+{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, {0}},
+
+{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, {0}},
+{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, {0}},
+{"db12cyc", 0x7fdef378, 0xffffffff, CELL, {0}},
+{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, {0}},
{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
@@ -4451,9 +4487,7 @@ const struct powerpc_opcode powerpc_opco
{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
-
{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
-
{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
{ "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
@@ -4576,9 +4610,7 @@ const struct powerpc_opcode powerpc_opco
{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
-
{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
-
{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
Index: gas/config/tc-ppc.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-ppc.c,v
retrieving revision 1.134
diff -u -p -w -r1.134 tc-ppc.c
--- gas/config/tc-ppc.c 1 Mar 2008 07:24:47 -0000 1.134
+++ gas/config/tc-ppc.c 6 Mar 2008 22:56:30 -0000
@@ -1255,7 +1255,6 @@ ppc_setup_opcodes (void)
const struct powerpc_macro *macro;
const struct powerpc_macro *macro_end;
bfd_boolean bad_insn = FALSE;
- unsigned long prev_opcode = 0;
if (ppc_hash != NULL)
hash_die (ppc_hash);
@@ -1303,17 +1302,56 @@ ppc_setup_opcodes (void)
{
const unsigned char *o;
unsigned long omask = op->mask;
- unsigned long major_opcode = PPC_OP (op->opcode);
- /* The major opcodes had better be sorted. Code in the disassembler
- assumes the insns are sorted according to major opcode. */
- if (major_opcode < prev_opcode)
+ if (op != powerpc_opcodes)
+ {
+ /* The major opcodes had better be sorted. Code in the
+ disassembler assumes the insns are sorted according to
+ major opcode. */
+ if (PPC_OP (op[0].opcode) < PPC_OP (op[-1].opcode))
{
as_bad (_("major opcode is not sorted for %s"),
op->name);
bad_insn = TRUE;
}
- prev_opcode = major_opcode;
+
+ /* Warn if the table isn't more strictly ordered.
+ Unfortunately it doesn't seem possible to order the
+ table on much more than the major opcode, which makes
+ it difficult to implement a binary search in the
+ disassembler. The problem is that we have multiple
+ ways to disassemble instructions, and we usually want
+ to choose a more specific form (with more bits set in
+ the opcode) than a more general form. eg. all of the
+ following are equivalent:
+ bne label # opcode = 0x40820000, mask = 0xff830003
+ bf 2,label # opcode = 0x40800000, mask = 0xff800003
+ bc 4,2,label # opcode = 0x40000000, mask = 0xfc000003
+
+ There are also cases where the table needs to be out
+ of order to disassemble the correct instruction for
+ processor variants. eg. "lhae" booke64 insn must be
+ found before "ld" ppc64 insn. */
+ else if (0)
+ {
+ unsigned long t1 = op[0].opcode;
+ unsigned long t2 = op[-1].opcode;
+
+ if (((t1 ^ t2) & 0xfc0007ff) == 0
+ && (t1 & 0xfc0006df) == 0x7c000286)
+ {
+ /* spr field is split. */
+ t1 = ((t1 & ~0x1ff800)
+ | ((t1 & 0xf800) << 5) | ((t1 & 0x1f0000) >> 5));
+ t2 = ((t2 & ~0x1ff800)
+ | ((t2 & 0xf800) << 5) | ((t2 & 0x1f0000) >> 5));
+ }
+ if (t1 < t2)
+ as_warn (_("%s (%08lx %08lx) after %s (%08lx %08lx)"),
+ op[0].name, op[0].opcode, op[0].mask,
+ op[-1].name, op[-1].opcode, op[-1].mask);
+ }
+ }
/* The mask had better not trim off opcode bits. */
if ((op->opcode & omask) != op->opcode)
--
Alan Modra
Australia Development Lab, IBM