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[PATCH]: MIPS: Add handling for R14000, R16000 CPUs (mapped to R10000)
- From: Kumba <kumba at gentoo dot org>
- To: binutils at sourceware dot org
- Date: Sat, 22 Nov 2008 22:21:19 -0500
- Subject: [PATCH]: MIPS: Add handling for R14000, R16000 CPUs (mapped to R10000)
A patch I sent into gcc awhile back adds support for the -march=r10000 family of
processors (R10000, R12000, R14000, R16000). The attached patch completes this
support in binutils by adding the R14000 and R16000 parameters.
If I missed something, please let me know!
Joshua Kinard
Gentoo/MIPS
kumba@gentoo.org
2008-11-22 Joshua Kinard <kumba@gentoo.org>
* bfd/aoutx.h (NAME): Add case statements for bfd_mach_mips14000,
bfd_mach_mips16000.
* bfd/archures.c (bfd_architecture): Add .#defines for
bfd_mach_mips14000, bfd_mach_mips16000.
* bfd/bfd-in2.h (bfd_architecture): Add #defines for
bfd_mach_mips14000, bfd_mach_mips16000.
* bfd/cpu-mips.c: Add enums I_mips14000, I_mips16000.
(arch_info_struct): Add refs to R14000, R16000.
* bfd/elfxx-mips.c (mips_set_isa_flags): Handle bfd_mach_mips14000
bfd_mach_mips16000.
(mips_mach_extensions): Map R14000, R16000 to R10000.
* gas/config/tc-mips.c (hilo_interlocks): Handle CPU_R14000,
CPU_R16000.
(mips_cpu_info_table): Add r14000, r16000.
* gas/doc/c-mips.texi: Add entries for 14000, 16000.
* include/opcode/mips.h: Define CPU_R14000, CPU_R16000.
(OPCODE_IS_MEMBER): Include R14000, R16000 in test.
* opcodes/mips-dis.c (mips_arch_choices): Add r14000, r16000.
Index: bfd/aoutx.h
===================================================================
RCS file: /cvs/src/src/bfd/aoutx.h,v
retrieving revision 1.72
diff -u -p -r1.72 aoutx.h
--- bfd/aoutx.h 9 Aug 2007 23:14:55 -0000 1.72
+++ bfd/aoutx.h 23 Nov 2008 02:44:00 -0000
@@ -786,6 +786,8 @@ NAME (aout, machine_type) (enum bfd_arch
case bfd_mach_mips9000:
case bfd_mach_mips10000:
case bfd_mach_mips12000:
+ case bfd_mach_mips14000:
+ case bfd_mach_mips16000:
case bfd_mach_mips16:
case bfd_mach_mipsisa32:
case bfd_mach_mipsisa32r2:
Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.132
diff -u -p -r1.132 archures.c
--- bfd/archures.c 9 Aug 2008 05:35:12 -0000 1.132
+++ bfd/archures.c 23 Nov 2008 02:44:00 -0000
@@ -167,6 +167,8 @@ DESCRIPTION
.#define bfd_mach_mips9000 9000
.#define bfd_mach_mips10000 10000
.#define bfd_mach_mips12000 12000
+.#define bfd_mach_mips14000 14000
+.#define bfd_mach_mips16000 16000
.#define bfd_mach_mips16 16
.#define bfd_mach_mips5 5
.#define bfd_mach_mips_loongson_2e 3001
Index: bfd/bfd-in2.h
===================================================================
RCS file: /cvs/src/src/bfd/bfd-in2.h,v
retrieving revision 1.456
diff -u -p -r1.456 bfd-in2.h
--- bfd/bfd-in2.h 4 Oct 2008 17:18:36 -0000 1.456
+++ bfd/bfd-in2.h 23 Nov 2008 02:44:00 -0000
@@ -1789,6 +1789,8 @@ enum bfd_architecture
#define bfd_mach_mips9000 9000
#define bfd_mach_mips10000 10000
#define bfd_mach_mips12000 12000
+#define bfd_mach_mips14000 14000
+#define bfd_mach_mips16000 16000
#define bfd_mach_mips16 16
#define bfd_mach_mips5 5
#define bfd_mach_mips_loongson_2e 3001
Index: bfd/cpu-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-mips.c,v
retrieving revision 1.29
diff -u -p -r1.29 cpu-mips.c
--- bfd/cpu-mips.c 4 Feb 2008 19:15:52 -0000 1.29
+++ bfd/cpu-mips.c 23 Nov 2008 02:44:00 -0000
@@ -80,6 +80,8 @@ enum
I_mips9000,
I_mips10000,
I_mips12000,
+ I_mips14000,
+ I_mips16000,
I_mips16,
I_mips5,
I_mipsisa32,
@@ -116,6 +118,8 @@ static const bfd_arch_info_type arch_inf
N (64, 64, bfd_mach_mips9000, "mips:9000", FALSE, NN(I_mips9000)),
N (64, 64, bfd_mach_mips10000,"mips:10000", FALSE, NN(I_mips10000)),
N (64, 64, bfd_mach_mips12000,"mips:12000", FALSE, NN(I_mips12000)),
+ N (64, 64, bfd_mach_mips14000,"mips:14000", FALSE, NN(I_mips14000)),
+ N (64, 64, bfd_mach_mips16000,"mips:16000", FALSE, NN(I_mips16000)),
N (64, 64, bfd_mach_mips16, "mips:16", FALSE, NN(I_mips16)),
N (64, 64, bfd_mach_mips5, "mips:mips5", FALSE, NN(I_mips5)),
N (32, 32, bfd_mach_mipsisa32, "mips:isa32", FALSE, NN(I_mipsisa32)),
Index: bfd/elfxx-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/elfxx-mips.c,v
retrieving revision 1.250
diff -u -p -r1.250 elfxx-mips.c
--- bfd/elfxx-mips.c 9 Sep 2008 03:17:13 -0000 1.250
+++ bfd/elfxx-mips.c 23 Nov 2008 02:44:02 -0000
@@ -10400,6 +10400,8 @@ mips_set_isa_flags (bfd *abfd)
case bfd_mach_mips8000:
case bfd_mach_mips10000:
case bfd_mach_mips12000:
+ case bfd_mach_mips14000:
+ case bfd_mach_mips16000:
val = E_MIPS_ARCH_4;
break;
@@ -12124,6 +12126,8 @@ static const struct mips_mach_extension
/* R10000 extensions. */
{ bfd_mach_mips12000, bfd_mach_mips10000 },
+ { bfd_mach_mips14000, bfd_mach_mips10000 },
+ { bfd_mach_mips16000, bfd_mach_mips10000 },
/* R5000 extensions. Note: the vr5500 ISA is an extension of the core
vr5400 ISA, but doesn't include the multimedia stuff. It seems
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.398
diff -u -p -r1.398 tc-mips.c
--- gas/config/tc-mips.c 6 Nov 2008 19:49:26 -0000 1.398
+++ gas/config/tc-mips.c 23 Nov 2008 02:44:03 -0000
@@ -472,6 +472,8 @@ static int mips_32bitmode = 0;
|| mips_opts.arch == CPU_R4010 \
|| mips_opts.arch == CPU_R10000 \
|| mips_opts.arch == CPU_R12000 \
+ || mips_opts.arch == CPU_R14000 \
+ || mips_opts.arch == CPU_R16000 \
|| mips_opts.arch == CPU_RM7000 \
|| mips_opts.arch == CPU_VR5500 \
)
@@ -15090,6 +15092,8 @@ static const struct mips_cpu_info mips_c
{ "r8000", 0, ISA_MIPS4, CPU_R8000 },
{ "r10000", 0, ISA_MIPS4, CPU_R10000 },
{ "r12000", 0, ISA_MIPS4, CPU_R12000 },
+ { "r14000", 0, ISA_MIPS4, CPU_R14000 },
+ { "r16000", 0, ISA_MIPS4, CPU_R16000 },
{ "vr5000", 0, ISA_MIPS4, CPU_R5000 },
{ "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
{ "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
Index: gas/doc/c-mips.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-mips.texi,v
retrieving revision 1.45
diff -u -p -r1.45 c-mips.texi
--- gas/doc/c-mips.texi 28 Apr 2008 17:06:28 -0000 1.45
+++ gas/doc/c-mips.texi 23 Nov 2008 02:44:03 -0000
@@ -239,6 +239,8 @@ rm7000,
rm9000,
10000,
12000,
+14000,
+16000,
4kc,
4km,
4kp,
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.60
diff -u -p -r1.60 mips.h
--- include/opcode/mips.h 6 Nov 2008 19:32:42 -0000 1.60
+++ include/opcode/mips.h 23 Nov 2008 02:44:04 -0000
@@ -632,6 +632,8 @@ static const unsigned int mips_isa_table
#define CPU_RM9000 9000
#define CPU_R10000 10000
#define CPU_R12000 12000
+#define CPU_R14000 14000
+#define CPU_R16000 16000
#define CPU_MIPS16 16
#define CPU_MIPS32 32
#define CPU_MIPS32R2 33
@@ -661,7 +663,8 @@ static const unsigned int mips_isa_table
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
- || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
+ || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \
+ || cpu == CPU_R16000) \
&& ((insn)->membership & INSN_10000) != 0) \
|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
|| (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.75
diff -u -p -r1.75 mips-dis.c
--- opcodes/mips-dis.c 6 Nov 2008 19:40:10 -0000 1.75
+++ opcodes/mips-dis.c 23 Nov 2008 02:44:04 -0000
@@ -409,6 +409,10 @@ const struct mips_arch_choice mips_arch_
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4,
+ mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4,
+ mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },