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old binutils-2.13-msp.diff and binutils 2.19
- From: Andrew Randrianasulu <randrik_a at yahoo dot com>
- To: binutils at sourceware dot org
- Date: Sat, 22 Nov 2008 21:17:27 -0800 (PST)
- Subject: old binutils-2.13-msp.diff and binutils 2.19
- Reply-to: randrik_a at yahoo dot com
Hello. While trying to move forward this patch, i faced with duplicated opcode in opcodes/mips-ops.c One "vmulu" was defined for Octeon, and one - for SGI O2 VICE coprocessor. After commenting out one from Octeon
- my [patched] binutils finally was able to pass gcc-3.4.6 compilation.
I saw some duplicates in this file, apart from my case, but i'm
really unsure what to do in this case? Move patch parts around?
But moving them in random order will break assembler, already learned
this ....
Also I'm lost in gas/config/tc-mips.c Original patch was designed for
(K, m, n) and i changed it for (+K, +m,+n). But i'm really lost in those big switches there. Right now my new code disabled, looking at old patch
i must add some logic before yet another switch. Or add goto ...
Old patch is here: http://www.linux-mips.org/~glaurung/VICE/binutils-2.13-msp.diff
and my [very incomplete] patch below.
----
--- binutils-2.19/gas/config/tc-mips.c 2008-08-08 19:24:49.000000000 +0000
+++ binutils-2.19-patched/gas/config/tc-mips.c 2008-11-22 07:21:48.000000000 +0000
@@ -8384,6 +8384,10 @@
case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
+ // msp hack 1
+ case 'K': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
+ USE_BITS (OP_MASK_FT, OP_SH_FT); break;
+ // msp hack 1 end!
case 'I': break;
case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
@@ -8395,7 +8399,13 @@
case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
-
+ // msp hack 2
+
+ case 'm': USE_BITS (OP_MASK_LOWVSEL, OP_SH_LOWVSEL);
+ USE_BITS (OP_MASK_FS, OP_SH_FS); break;
+ case 'n': USE_BITS (OP_MASK_LOWVSEL, OP_SH_LOWVSEL);
+ USE_BITS (OP_MASK_FT, OP_SH_FT); break;
+ // mps hack 2 end!
default:
as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
c, opc->name, opc->args);
@@ -8933,6 +8943,15 @@
case '+': /* Opcode extension character. */
switch (*++args)
{
+ // msp hack start
+
+ // case 'K': /* MSP vector or element. */
+ // case 'm': /* MSP MFC2/MTC2 source register. */
+ // case 'n': /* MSP LWC2/SWC2 dest register. */
+ /*
+ is_mdmx = 1;
+ */
+ // msp hack end!
case '1': /* UDI immediates. */
case '2':
case '3':
@@ -9055,7 +9074,79 @@
case 'D':
/* +D is for disassembly only; never match. */
break;
-
+#if 0
+ // msp hack 5
+ case 'm':
+ case 'n':
+ is_mdmx = 1;
+ /* Need to fix the MSP low vector/scalar select bits. */
+ if (*s == '[')
+ {
+ int max_el = 15;
+ s++;
+ my_getExpression(&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ if (imm_expr.X_add_number > max_el)
+ as_bad(_("Bad element selector %ld"),
+ (long) imm_expr.X_add_number);
+ imm_expr.X_add_number &= max_el;
+ ip->insn_opcode |= ((imm_expr.X_add_number)
+ << OP_SH_LOWVSEL);
+ if (*s != ']')
+ as_warn(_("Expecting ']' found '%s'"), s);
+ else
+ s++;
+ }
+ if(c == 'm')
+ ip->insn_opcode |= regno << OP_SH_FS;
+ if(c == 'n')
+ ip->insn_opcode |= regno << OP_SH_FT;
+ break;
+ case 'K':
+ is_mdmx = 1;
+ /* Need to fix the MSP high vector/scalar select bits. */
+ if (*s == '[')
+ {
+ int max_el;
+ s++;
+ my_getExpression(&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ if(*s == 'q') {
+ /* quarter select */
+ max_el = 1; s++;
+ ip->insn_opcode |= 0x2 << OP_SH_VSEL;
+ }
+ else if(*s == 'h') {
+ /* half select */
+ max_el = 3; s++;
+ ip->insn_opcode |= 0x4 << OP_SH_VSEL;
+ } else {
+ /* scalar select */
+ max_el = 7;
+ ip->insn_opcode |= 0x8 << OP_SH_VSEL;
+ }
+ if (*s != ']') {
+ as_warn(_("Expecting ']' found '%s'"), s);
+ }
+ else {
+ s++;
+ }
+
+ if (imm_expr.X_add_number > max_el)
+ as_bad(_("Bad element selector %ld"),
+ (long) imm_expr.X_add_number);
+ imm_expr.X_add_number &= max_el;
+ ip->insn_opcode |= imm_expr.X_add_number
+ << OP_SH_VSEL;
+ }
+ ip->insn_opcode |= regno << OP_SH_FT;
+ break;
+ // msp hack 5 end!
+#endif
case 'I':
/* "+I" is like "I", except that imm2_expr is used. */
my_getExpression (&imm2_expr, s);
@@ -9124,7 +9215,7 @@
imm_expr.X_op = O_absent;
s = expr_end;
continue;
-
+
case 'p':
/* cins, cins32, exts and exts32 position field. Give error
if it's not in the valid range. */
@@ -9519,7 +9610,10 @@
s_reset = s;
if (reg_lookup (&s, rtype, ®no))
{
- if ((regno & 1) != 0
+ if ((regno & 1) != 0
+// msp hack - 4
+// if (((regno & 1) != 0 && !is_mdmx)
+// msp hack 4 end!
&& HAVE_32BIT_FPRS
&& ! mips_oddfpreg_ok (ip->insn_mo, argnum))
as_warn (_("Float register should be even, was %d"),
--- binutils-2.19/include/opcode/mips.h 2008-06-12 21:44:53.000000000 +0000
+++ binutils-2.19-patched/include/opcode/mips.h 2008-11-21 20:01:31.000000000 +0000
@@ -140,6 +140,10 @@
#define OP_MASK_VSEL 0x1f
#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
but 0x8-0xf don't select bytes. */
+// vice msp hack!
+#define OP_SH_LOWVSEL 7 /* The vsel field of {mf/mt/lw/sw}c2 */
+#define OP_MASK_LOWVSEL 0xf
+
#define OP_SH_VECBYTE 22
#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
#define OP_SH_VECALIGN 21
@@ -351,6 +355,13 @@
"Y" MDMX source register (OP_*_FS)
"Z" MDMX source register (OP_*_FT)
+// msp hack !!
+
+ VICE MSP/Nintendo64 RCP instruction operands
+ "+m" vector source for MFC2/MTC2 operations (OP_*_LOWVSEL and OP_*_FS)
+ "+n" vector dest for LWC2/SWC2 operations (OP_*_LOWVSEL and OP_*_FT)
+ "+K" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
+
DSP ASE usage:
"2" 2 bit unsigned immediate for byte align (OP_*_BP)
"3" 3 bit unsigned immediate (OP_*_SA3)
@@ -409,8 +420,8 @@
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
"1234"
- "ABCDEFGHIPQSTX"
- "pstx"
+ "ABCDEFGHIKPQSTX"
+ "mnpstx"
*/
/* These are the bits which may be set in the pinfo field of an
--- binutils-2.19/opcodes/mips-dis.c 2008-07-10 19:05:28.000000000 +0000
+++ binutils-2.19-patched/opcodes/mips-dis.c 2008-11-21 20:04:27.000000000 +0000
@@ -853,7 +853,48 @@
msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
(*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
break;
-
+ // msp hack!
+ case 'm':
+ case 'n':
+ {
+ unsigned int vsel = (l >> OP_SH_LOWVSEL) & OP_MASK_LOWVSEL;
+
+ (*info->fprintf_func) (info->stream, "$v%d[%d]",
+ (l >> OP_SH_FS) & OP_MASK_FS,
+ vsel);
+ }
+ break;
+
+ case 'K':
+ {
+ unsigned int vsel = (l >> OP_SH_LOWVSEL) & OP_MASK_LOWVSEL;
+
+ if(vsel)
+ {
+ if(vsel & 8)
+ (*info->fprintf_func) (info->stream, "$v%d[%d]",
+ (l >> OP_SH_FS) & OP_MASK_FS,
+ vsel & 7);
+ else if(vsel & 4)
+ (*info->fprintf_func) (info->stream, "$v%d[%dh]",
+ (l >> OP_SH_FS) & OP_MASK_FS,
+ vsel & 3);
+ else if(vsel & 2)
+ (*info->fprintf_func) (info->stream, "$v%d[%dq]",
+ (l >> OP_SH_FS) & OP_MASK_FS,
+ vsel & 1);
+ else if(vsel & 1)
+ (*info->fprintf_func) (info->stream, "$v%d[?]", /* unknown code */
+ (l >> OP_SH_FS) & OP_MASK_FS);
+ } else {
+ (*info->fprintf_func) (info->stream, "$v%d",
+ (l >> OP_SH_FS) & OP_MASK_FS);
+ }
+ }
+ break;
+
+ // end of msp hack!
+
case 't': /* Coprocessor 0 reg name */
(*info->fprintf_func) (info->stream, "%s",
mips_cp0_names[(l >> OP_SH_RT) &
--- binutils-2.19/opcodes/mips-opc.c 2008-07-07 19:11:15.000000000 +0000
+++ binutils-2.19-patched/opcodes/mips-opc.c 2008-11-22 15:53:19.000000000 +0000
@@ -108,6 +108,10 @@
/* MIPS64 MDMX ASE support. */
#define MX INSN_MDMX
+/* SGI O2 VICE MSP and Nintendo 64 RCP support */
+#define MSP INSN_MDMX /* TEMP */
+
+
#define IL2E (INSN_LOONGSON_2E)
#define IL2F (INSN_LOONGSON_2F)
@@ -788,6 +792,24 @@
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
+// msp hack part 3!
+/* TEMP new MSP load insn */
+{"lbv", "+n,o(b)", 0xc8000000, 0xfc00f800, LDD|RD_b|WR_T, 0, MSP },
+{"lsv", "+n,o(b)", 0xc8000800, 0xfc00f800, LDD|RD_b|WR_T, 0, MSP },
+{"llv", "+n,o(b)", 0xc8001000, 0xfc00f800, LDD|RD_b|WR_T, 0, MSP },
+{"ldv", "+n,o(b)", 0xc8001800, 0xfc00f800, LDD|RD_b|WR_T, 0, MSP },
+{"lqv", "+n,o(b)", 0xc8002000, 0xfc00f800, LDD|RD_b|WR_T, 0, MSP },
+{"lrv", "Z,o(b)", 0xc8002800, 0xfc00ffc0, LDD|RD_b|WR_T, 0, MSP },
+{"lpv", "+n,o(b)", 0xc8003000, 0xfc00f800, LDD|RD_b|WR_T, 0, MSP },
+{"luv", "+n,o(b)", 0xc8003800, 0xfc00f800, LDD|RD_b|WR_T, 0, MSP },
+{"lxv", "+n,o(b)", 0xc8004000, 0xfc00f800, LDD|RD_b|WR_T, 0, MSP },
+{"lzv", "+n,o(b)", 0xc8004800, 0xfc00f800, LDD|RD_b|WR_T, 0, MSP },
+{"lhv", "+n,o(b)", 0xc8005000, 0xfc00f800, LDD|RD_b|WR_T, 0, MSP },
+{"lfv", "+n,o(b)", 0xc8005800, 0xfc00f800, LDD|RD_b|WR_T, 0, MSP },
+{"lav", "+n,o(b)", 0xc8006000, 0xfc00f800, LDD|RD_b|WR_T, 0, MSP },
+{"ltv", "+n,o(b)", 0xc8006800, 0xfc00f800, LDD|RD_b|WR_T, 0, MSP },
+// msp hack part 3 end!
+
{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
@@ -1306,6 +1328,24 @@
{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
+// msp hack part 6
+ /* TEMP new MSP store insn */
+{"sbv", "+n,o(b)", 0xe8000000, 0xfc00f800, SM|RD_b|RD_T, 0, MSP },
+{"ssv", "+n,o(b)", 0xe8000800, 0xfc00f800, SM|RD_b|RD_T, 0, MSP },
+{"slv", "+n,o(b)", 0xe8001000, 0xfc00f800, SM|RD_b|RD_T, 0, MSP },
+{"sdv", "+n,o(b)", 0xe8001800, 0xfc00f800, SM|RD_b|RD_T, 0, MSP },
+{"sqv", "+n,o(b)", 0xe8002000, 0xfc00f800, SM|RD_b|RD_T, 0, MSP },
+{"srv", "Z,o(b)", 0xe8002800, 0xfc00ffc0, SM|RD_b|RD_T, 0, MSP },
+{"spv", "+n,o(b)", 0xe8003000, 0xfc00f800, SM|RD_b|RD_T, 0, MSP },
+{"suv", "+n,o(b)", 0xe8003800, 0xfc00f800, SM|RD_b|RD_T, 0, MSP },
+{"sxv", "+n,o(b)", 0xe8004000, 0xfc00f800, SM|RD_b|RD_T, 0, MSP },
+{"szv", "+n,o(b)", 0xe8004800, 0xfc00f800, SM|RD_b|RD_T, 0, MSP },
+{"shv", "+n,o(b)", 0xe8005000, 0xfc00f800, SM|RD_b|RD_T, 0, MSP },
+{"sfv", "+n,o(b)", 0xe8005800, 0xfc00f800, SM|RD_b|RD_T, 0, MSP },
+{"sav", "+n,o(b)", 0xe8006000, 0xfc00f800, SM|RD_b|RD_T, 0, MSP },
+{"stv", "+n,o(b)", 0xe8006800, 0xfc00f800, SM|RD_b|RD_T, 0, MSP },
+
+// msp hack part 6 end!
{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 },
{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 },
@@ -1385,9 +1425,99 @@
{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 },
{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 },
{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 },
+// msp ahck part 7
+/* TEMP: new MSP vector operations ( ! = illegal instruction ) */
+{"vmulf", "X,Y,+K", 0x4a000000, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmulu", "X,Y,+K", 0x4a000001, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vrndpl", "X,+K", 0x4a000002, 0xfe00f83f, WR_D|RD_T, 0, MSP },
+{"vrndph", "X,+K", 0x4a000802, 0xfe00f83f, WR_D|RD_T, 0, MSP },
+{"vmulq", "X,Y,+K", 0x4a000003, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmudl", "X,Y,+K", 0x4a000004, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmudm", "X,Y,+K", 0x4a000005, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmudn", "X,Y,+K", 0x4a000006, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmudh", "X,Y,+K", 0x4a000007, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmacf", "X,Y,+K", 0x4a000008, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmacu", "X,Y,+K", 0x4a000009, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vrndnl", "X,+K", 0x4a00000a, 0xfe00f83f, WR_D|RD_S|RD_T, 0, MSP },
+{"vrndnh", "X,+K", 0x4a00080a, 0xfe00f83f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmacq", "X,Y,+K", 0x4a00000b, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmadl", "X,Y,+K", 0x4a00000c, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmadm", "X,Y,+K", 0x4a00000d, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmadn", "X,Y,+K", 0x4a00000e, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmadh", "X,Y,+K", 0x4a00000f, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vadd", "X,Y,+K", 0x4a000010, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vsub", "X,Y,+K", 0x4a000011, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vsut", "X,Y,+K", 0x4a000012, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vabs", "X,Y,+K", 0x4a000013, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vaddc", "X,Y,+K", 0x4a000014, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vsubc", "X,Y,+K", 0x4a000015, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vaddb", "X,Y,Z,O", 0x4a000016, 0xff00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vaddb", "X,Y,Z", 0x4a000016, 0xffe0003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vsubb", "X,Y,Z,O", 0x4a000017, 0xff00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vsubb", "X,Y,Z", 0x4a000017, 0xffe0003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vaccb", "X,Y,Z,O", 0x4a000018, 0xff00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vaccb", "X,Y,Z", 0x4a000018, 0xffe0003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vsucb", "X,Y,Z,O", 0x4a000019, 0xff00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vsucb", "X,Y,Z", 0x4a000019, 0xffe0003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vsad", "X,Y,Z", 0x4a00001a, 0xffe0003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vsac", "X,Y,Z", 0x4a00001b, 0xffe0003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vsumh", "X", 0x4a00001c, 0xfffff83f, WR_D, 0, MSP },
+{"vsumm", "X", 0x4a20001c, 0xfffff83f, WR_D, 0, MSP },
+{"vsuml", "X", 0x4a40001c, 0xfffff83f, WR_D, 0, MSP },
+{"vsawh", "X,Y", 0x4a00001d, 0xffff003f, WR_D|RD_S, 0, MSP },
+{"vsawm", "X,Y", 0x4a20001d, 0xffff003f, WR_D|RD_S, 0, MSP },
+{"vsawl", "X,Y", 0x4a40001d, 0xffff003f, WR_D|RD_S, 0, MSP },
+{"vacc", "X,Y,+K", 0x4a00001e, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vsuc", "X,Y,+K", 0x4a00001f, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vlt", "X,Y,+K", 0x4a000020, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"veq", "X,Y,+K", 0x4a000021, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vne", "X,Y,+K", 0x4a000022, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vge", "X,Y,+K", 0x4a000023, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vch"/*!*/, "X,Y,+K", 0x4a000024, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vcl", "X,Y,+K", 0x4a000025, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmrg", "X,Y,+K", 0x4a000026, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vcr", "X,Y,+K", 0x4a000027, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+
+{"vand", "X,Y,+K", 0x4a000028, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vnand", "X,Y,+K", 0x4a000029, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vor", "X,Y,+K", 0x4a00002a, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vnor", "X,Y,+K", 0x4a00002b, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vxor", "X,Y,+K", 0x4a00002c, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vnxor", "X,Y,+K", 0x4a00002d, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vunk", "X,Y,+K", 0x4a00002e, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+ /* ! */
+ /* ! */
+{"vsumb", "X,Y,Z,O", 0x4a000030, 0xff00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vsumb", "X,Y,Z", 0x4a000030, 0xffe0003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vsacb", "X,Y,Z,O", 0x4a000031, 0xff00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vsacb", "X,Y,Z", 0x4a000031, 0xffe0003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmulb", "X,Y,Z,O", 0x4a000032, 0xff00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmulb", "X,Y,Z", 0x4a000032, 0xffe0003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmulbn", "X,Y,Z,O", 0x4a000033, 0xff00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmulbn", "X,Y,Z", 0x4a000033, 0xffe0003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmacb", "X,Y,Z,O", 0x4a000034, 0xff00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmacb", "X,Y,Z", 0x4a000034, 0xffe0003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmsucb", "X,Y,Z,O", 0x4a000035, 0xff00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vmsucb", "X,Y,Z", 0x4a000035, 0xffe0003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vrndl", "X,+K", 0x4a000036, 0xfe00f83f, WR_D|RD_T, 0, MSP },
+{"vrndh", "X,+K", 0x4a000836, 0xfe00f83f, WR_D|RD_T, 0, MSP },
+{"vrndbl", "X,O", 0x4a000037, 0xff1ff83f, WR_D, 0, MSP },
+{"vrndbl", "X", 0x4a000837, 0xfffff83f, WR_D, 0, MSP },
+{"vrndbh", "X,O", 0x4a000037, 0xff1ff83f, WR_D, 0, MSP },
+{"vrndbh", "X", 0x4a000837, 0xfffff83f, WR_D, 0, MSP },
+{"vextt"/*!*/, "X,Y,+K", 0x4a000038, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vextq"/*!*/, "X,Y,+K", 0x4a000039, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vextn"/*!*/, "X,Y,+K", 0x4a00003a, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vinst"/*!*/, "X,Y,+K", 0x4a00003b, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vinsq"/*!*/, "X,Y,+K", 0x4a00003c, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+{"vinsn"/*!*/, "X,Y,+K", 0x4a00003d, 0xfe00003f, WR_D|RD_S|RD_T, 0, MSP },
+ /* ! */
+ /* ! */
+
+// msp hack part 7 end!
{"v3mulu", "d,v,t", 0x70000011, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
{"vmm0", "d,v,t", 0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
-{"vmulu", "d,v,t", 0x7000000f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
+// {"vmulu", "d,v,t", 0x7000000f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 },
{"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 },
{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX },
@@ -1489,7 +1619,15 @@
{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 },
{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
+// msp hack part 1
+{"cfc2c", "t", 0x48400000, 0xffe0ffff, LCD|WR_t|RD_C2, 0, MSP },
+{"cfc2o", "t", 0x48400800, 0xffe0ffff, LCD|WR_t|RD_C2, 0, MSP },
+// msp hack part 1 end!
{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
+// msp hack part 2
+{"ctc2c", "t", 0x48c00000, 0xffe0ffff, COD|RD_t|WR_CC, 0, MSP },
+{"ctc2o", "t", 0x48c00800, 0xffe0ffff, COD|RD_t|WR_CC, 0, MSP },
+// msp hack part 2 end!
{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 },
{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 },
{"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT },
@@ -1497,11 +1635,17 @@
{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 },
{"dmtc2", "t,i", 0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, IOCT },
{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
+// msp hack part 4
+{"mfc2", "t,+m", 0x48000000, 0xffe0007f, LCD|WR_t|RD_C2, 0, MSP },
+// msp hack part 4 end!
{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 },
{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 },
{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 },
{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 },
{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 },
+// msp hack part 5
+{"mtc2", "t,+m", 0x48800000, 0xffe0007f, COD|RD_t|WR_C2|WR_CC, 0, MSP },
+// msp hack part 5 end!
{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 },
{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 },
{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 },