RE: MIPS PLT entry

["Maciej W. Rozycki" <macro at linux-mips dot org>]

On Mon, 15 Jun 2009, Fu, Chao-Ying wrote:

> >  There is a data dependency between the L[WD] instruction and the JR 
> > instruction and therefore for MIPS I processors you need an 
> > intermediate 
> > instruction to fill the load delay slot.  Of course if building for a 
> > higher processor (and in particular for LD, where it is 
> > guaranteed) you 
> > may swap the instructions, but it cannot be unconditional.
> 
>   Yes.  But, this design may hurt the performance.  If a CPU fetches
> 4 instructions per cycle, it will need to fetch again for the 5th instruction next cycle
> and execute the 5th instruction in pipeline stages.  And this 5th instruction is just 
> an unused instruction.

 The default sequence is out of question -- with MIPS I processors a 
failure to observe the load delay slot will make code completely unusable 
-- there is no interlock.  Correctness first, performance second.

>   Maybe we need to have conditional compilation on this file for MIPS1 CPUs and
> all other MIPS processors.  Thanks!
> 
> Ex:
> #ifdef FOR_MIPS1
> ...
> #else
> ...
> #endif

 No, it cannot be done at the BFD build time -- this why I suggested for 
such a fixup to be made by LD based on ISA flags stored in the ELF files 
being linked (or actually the resulting output ISA flags).  It should be 
pretty straightforward -- _bfd_mips_elf_finish_dynamic_symbol(), which is 
the place to do such shuffling should have all the needed information 
readily available.

 If you don't feel comfortable with making the adjustments I have in mind, 
then I can see if I can find some time to have a look into an 
implementation.  It may take a few days however.

  Maciej