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RE: MIPS PLT entry
- From: "Fu, Chao-Ying" <fu at mips dot com>
- To: "Richard Sandiford" <rdsandiford at googlemail dot com>
- Cc: "Maciej W. Rozycki" <macro at linux-mips dot org>, <binutils at sourceware dot org>
- Date: Thu, 16 Jul 2009 15:35:18 -0700
- Subject: RE: MIPS PLT entry
Richard Sandiford wrote:
> "Fu, Chao-Ying" <fu@mips.com> writes:
> >> >
> >> > ... it's trivial to implement it flexibly, so that both MIPS
> >> > I support is
> >> > retained and newer platforms benefit from a faster sequence,
> >> > and I plan to
> >> > do so unless Chao-Ying beats me, ;) so I see no point in
> doing it
> >> > otherwise.
> >>
> > Hi Maciej,
> >
> > I didn't see your patch, so I made a patch. Do you think
> > this patch does what you plan to do? Thanks a lot!
>
> Looks good.
>
> > @@ -8630,10 +8638,12 @@ _bfd_mips_elf_size_dynamic_sections (bfd
> > s->size += mips_elf_hash_table (info)->compact_rel_size;
> > else if (s == htab->splt)
> > {
> > - /* If the last PLT entry has a branch delay slot, allocate
> > + /* For MIPS1, if the last PLT entry has a branch
> delay slot, allocate
> > room for an extra nop to fill the delay slot. */
> > - if (!htab->is_vxworks && s->size > 0)
> > - s->size += 4;
> > + if (((elf_elfheader (output_bfd)->e_flags & EF_MIPS_ARCH)
> > + == E_MIPS_ARCH_1)
> > + && !htab->is_vxworks && s->size > 0)
> > + s->size += 4;
>
> I think the elf_elfheader condition ought to be in a macro:
>
> #define LOAD_INTERLOCKS_P(abfd) \
> ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_1)
>
> since some MIPS I targets (like the tx39) had load interlocks too.
> Put it with other similar macros like PIC_OBJECT_P.
>
> OK with that change, thanks. Are there no regressions in the
> ld testsuite?
>
I tested targets as mips-linux-gnu and mipsisa32r2-linux-gnu. Three new
fails for mips-linux-gnu and four for mipsisa32r2-linux-gnu:
Ex:
FAIL: MIPS16 PIC test 3 <---- This is only for mipsisa32r2-linux-gnu.
FAIL: PIC and non-PIC test 3 (executable)
FAIL: PIC and non-PIC test 5 (executable)
FAIL: PIC and non-PIC test 6 (o32 executable)
All fails are due to the new PLT design for non-MIPS1 CPUs.
I fixed three new fails for mips-linux-gnu.
The remaining one for mipsisa32r2-linux-gnu does not show up for mips-linux-gnu,
so I didn't fix it. Maybe we can pass mips1 to AS/LD for MIPS16 PIC tests
in "mips-elf.exp".
Here is the new patch. Please check it. Thanks a lot!
Regards,
Chao-ying
bfd/ChangeLog
2009-07-16 Chao-ying Fu <fu@mips.com>
* elfxx-mips.c (LOAD_INTERLOCKS_P): New define.
(mips_exec_fast_plt_entry): New table.
(_bfd_mips_elf_size_dynamic_sections): For CPUs without load
interlocking, the last PLT entry needs a nop in the branch delay slot.
(_bfd_mips_elf_finish_dynamic_symbol): For CPUs with load itnerlocking,
we can use the fast PLT entry that doesn't need the 5th instruction.
ld/testsuite/ChangeLog
2009-07-16 Chao-ying Fu <fu@mips.com>
* ld-mips-elf/pic-and-nonpic-3b.dd,
ld-mips-elf/pic-and-nonpic-5b.dd,
ld-mips-elf/pic-and-nonpic-6-o32.dd: Updated to use new PLT entries.
Index: src/bfd/elfxx-mips.c
===================================================================
--- src.orig/bfd/elfxx-mips.c 2009-07-16 14:37:51.739876000 -0700
+++ src/bfd/elfxx-mips.c 2009-07-16 14:46:31.267532000 -0700
@@ -662,6 +662,12 @@ static struct mips_got_info *mips_elf_go
/* This will be used when we sort the dynamic relocation records. */
static bfd *reldyn_sorting_bfd;
+/* True if ABFD is for CPUs with load interlocking that include
+ non-MIPS1 CPUs and R3900. */
+#define LOAD_INTERLOCKS_P(abfd) \
+ (((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) != E_MIPS_ARCH_1) \
+ || ((elf_elfheader (abfd)->e_flags & EF_MIPS_MACH) == E_MIPS_MACH_3900))
+
/* True if ABFD is a PIC object. */
#define PIC_OBJECT_P(abfd) \
((elf_elfheader (abfd)->e_flags & EF_MIPS_PIC) != 0)
@@ -923,6 +929,14 @@ static const bfd_vma mips_exec_plt_entry
0x03200008 /* jr $25 */
};
+/* This plt entry is for non-MIPS1 CPUs that have load interlocking. */
+static const bfd_vma mips_exec_fast_plt_entry[] = {
+ 0x3c0f0000, /* lui $15, %hi(.got.plt entry) */
+ 0x01f90000, /* l[wd] $25, %lo(.got.plt entry)($15) */
+ 0x03200008, /* jr $25 */
+ 0x25f80000 /* addiu $24, $15, %lo(.got.plt entry) */
+};
+
/* The format of the first PLT entry in a VxWorks executable. */
static const bfd_vma mips_vxworks_exec_plt0_entry[] = {
0x3c190000, /* lui t9, %hi(_GLOBAL_OFFSET_TABLE_) */
@@ -8631,9 +8645,11 @@ _bfd_mips_elf_size_dynamic_sections (bfd
else if (s == htab->splt)
{
/* If the last PLT entry has a branch delay slot, allocate
- room for an extra nop to fill the delay slot. */
- if (!htab->is_vxworks && s->size > 0)
- s->size += 4;
+ room for an extra nop to fill the delay slot.
+ This is for CPUs without load interlocking. */
+ if (!LOAD_INTERLOCKS_P (output_bfd)
+ && !htab->is_vxworks && s->size > 0)
+ s->size += 4;
}
else if (! CONST_STRNEQ (name, ".init")
&& s != htab->sgot
@@ -9352,11 +9368,23 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd
load = MIPS_ELF_LOAD_WORD (output_bfd);
/* Fill in the PLT entry itself. */
- plt_entry = mips_exec_plt_entry;
+ if (!LOAD_INTERLOCKS_P (output_bfd))
+ plt_entry = mips_exec_plt_entry;
+ else
+ plt_entry = mips_exec_fast_plt_entry;
bfd_put_32 (output_bfd, plt_entry[0] | got_address_high, loc);
bfd_put_32 (output_bfd, plt_entry[1] | got_address_low | load, loc + 4);
- bfd_put_32 (output_bfd, plt_entry[2] | got_address_low, loc + 8);
- bfd_put_32 (output_bfd, plt_entry[3], loc + 12);
+
+ if (!LOAD_INTERLOCKS_P (output_bfd))
+ {
+ bfd_put_32 (output_bfd, plt_entry[2] | got_address_low, loc + 8);
+ bfd_put_32 (output_bfd, plt_entry[3], loc + 12);
+ }
+ else
+ {
+ bfd_put_32 (output_bfd, plt_entry[2], loc + 8);
+ bfd_put_32 (output_bfd, plt_entry[3] | got_address_low, loc + 12);
+ }
/* Emit an R_MIPS_JUMP_SLOT relocation against the .got.plt entry. */
mips_elf_output_dynamic_relocation (output_bfd, htab->srelplt,
Index: src/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.dd
===================================================================
--- src.orig/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.dd 2008-08-08 12:24:49.000000000 -0700
+++ src/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.dd 2009-07-16 14:56:26.453751000 -0700
@@ -22,9 +22,8 @@ Disassembly of section \.plt:
00043040 <foo@plt>:
.*: 3c0f0008 lui t7,0x8
.*: 8df91008 lw t9,4104\(t7\)
-.*: 25f81008 addiu t8,t7,4104
.*: 03200008 jr t9
-.*: 00000000 nop
+.*: 25f81008 addiu t8,t7,4104
Disassembly of section \.text:
Index: src/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.dd
===================================================================
--- src.orig/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.dd 2008-08-08 12:24:49.000000000 -0700
+++ src/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.dd 2009-07-16 14:57:20.436712000 -0700
@@ -16,9 +16,8 @@ Disassembly of section \.plt:
00043060 <foo@plt>:
.*: 3c0f0008 lui t7,0x8
.*: 8df91008 lw t9,4104\(t7\)
-.*: 25f81008 addiu t8,t7,4104
.*: 03200008 jr t9
-.*: 00000000 nop
+.*: 25f81008 addiu t8,t7,4104
Disassembly of section .text:
Index: src/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd
===================================================================
--- src.orig/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd 2008-08-08 12:24:49.000000000 -0700
+++ src/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd 2009-07-16 14:59:56.474517000 -0700
@@ -27,21 +27,20 @@ Disassembly of section \.plt:
00043060 <extf4@plt>:
.*: 3c0f0008 lui t7,0x8
.*: 8df91008 lw t9,4104\(t7\)
-.*: 25f81008 addiu t8,t7,4104
.*: 03200008 jr t9
+.*: 25f81008 addiu t8,t7,4104
00043070 <extf5@plt>:
.*: 3c0f0008 lui t7,0x8
.*: 8df9100c lw t9,4108\(t7\)
-.*: 25f8100c addiu t8,t7,4108
.*: 03200008 jr t9
+.*: 25f8100c addiu t8,t7,4108
00043080 <extf3@plt>:
.*: 3c0f0008 lui t7,0x8
.*: 8df91010 lw t9,4112\(t7\)
-.*: 25f81010 addiu t8,t7,4112
.*: 03200008 jr t9
-.*: 00000000 nop
+.*: 25f81010 addiu t8,t7,4112
Disassembly of section \.text: