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PATCH: Check implicit registers only for instructions with 3 operands or less.
- From: "H.J. Lu" <hongjiu dot lu at intel dot com>
- To: binutils at sources dot redhat dot com
- Date: Fri, 17 Jul 2009 10:06:23 -0700
- Subject: PATCH: Check implicit registers only for instructions with 3 operands or less.
- Reply-to: "H.J. Lu" <hjl dot tools at gmail dot com>
Hi,
I checked in this patch to check implicit registers only for instructions
with 3 operands or less.
H.J.
---
Index: ChangeLog
===================================================================
--- ChangeLog (revision 6425)
+++ ChangeLog (working copy)
@@ -1,3 +1,8 @@
+2009-07-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (md_assemble): Check implicit registers
+ only for instructions with 3 operands or less.
+
2009-07-17 Nick Clifton <nickc@redhat.com>
* config/tc-avr.c (md_apply_fix): Cast fixup reloc type to avoid
Index: config/tc-i386.c
===================================================================
--- config/tc-i386.c (revision 6425)
+++ config/tc-i386.c (working copy)
@@ -3378,12 +3378,15 @@ md_assemble (char *line)
if (i.types[0].bitfield.imm1)
i.imm_operands = 0; /* kludge for shift insns. */
- for (j = 0; j < i.operands; j++)
- if (i.types[j].bitfield.inoutportreg
- || i.types[j].bitfield.shiftcount
- || i.types[j].bitfield.acc
- || i.types[j].bitfield.floatacc)
- i.reg_operands--;
+ /* We only need to check those implicit registers for instructions
+ with 3 operands or less. */
+ if (i.operands <= 3)
+ for (j = 0; j < i.operands; j++)
+ if (i.types[j].bitfield.inoutportreg
+ || i.types[j].bitfield.shiftcount
+ || i.types[j].bitfield.acc
+ || i.types[j].bitfield.floatacc)
+ i.reg_operands--;
/* ImmExt should be processed after SSE2AVX. */
if (!i.tm.opcode_modifier.sse2avx