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Blackfin: add -mcpu option to gas
- From: Bernd Schmidt <bernds_cb1 at t-online dot de>
- To: binutils at sources dot redhat dot com
- Date: Tue, 11 Aug 2009 20:43:28 +0100
- Subject: Blackfin: add -mcpu option to gas
This patch, by Jie Zhang, adds a -mcpu option to the Blackfin assembler.
One use of this is to implement checks for certain hardware anomalies.
Bernd
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Index: ChangeLog
===================================================================
RCS file: /cvs/src/src/gas/ChangeLog,v
retrieving revision 1.3890
diff -c -p -r1.3890 ChangeLog
*** ChangeLog 11 Aug 2009 18:28:29 -0000 1.3890
--- ChangeLog 11 Aug 2009 18:42:13 -0000
***************
*** 12,17 ****
--- 12,38 ----
decode_dsp32alu_0, decode_dsp32shift_0, decode_dsp32shitimm_0,
insn_regmask): New functions.
+ From Jie Zhang <jie.zhang@analog.com>
+ * config/tc-bfin.h (bfin_anomaly_checks): Declare.
+ (AC_05000074): Define.
+ (ENABLE_AC_05000074): Define.
+ * config/tc-bfin.c (enum bfin_cpu_type): New.
+ (bfin_cpu_t): Typedef.
+ (bfin_cpu_type): Define.
+ (bfin_si_revision): Define.
+ (bfin_anomaly_checks): Define.
+ (struct bfin_cpu): New.
+ (bfin_cpus[]): New. (struct bfin_cpu_isa): Define.
+ (bfin_isa): New global variable.
+ (OPTION_MCPU): Define.
+ (md_longopts[]): Add -mcpu option.
+ (md_parse_option): Deal with -mcpu option and initialize
+ bfin_anomaly_checks.
+ * doc/c-bfin.texi: Rename BFIN to Blackfin throughout. Document
+ -mcpu option.
+ * config/bfin-parse.y (gen_multi_instr_1): Check anomaly
+ 05000074.
+
2009-08-11 Mike Frysinger <vapier@gentoo.org>
* config/bfin-parse.y (binary): Change "compiler" to "assembler".
Index: config/bfin-parse.y
===================================================================
RCS file: /cvs/src/src/gas/config/bfin-parse.y,v
retrieving revision 1.23
diff -c -p -r1.23 bfin-parse.y
*** config/bfin-parse.y 11 Aug 2009 18:28:29 -0000 1.23
--- config/bfin-parse.y 11 Aug 2009 18:42:13 -0000
*************** gen_multi_instr_1 (INSTR_T dsp32, INSTR_
*** 394,399 ****
--- 394,409 ----
if ((mask1 & mask2) || (mask1 & mask3) || (mask2 & mask3))
yyerror ("resource conflict in multi-issue instruction");
+
+ /* Anomaly 05000074 */
+ if (ENABLE_AC_05000074
+ && (dsp32->value & 0xf780) == 0xc680
+ && ((dsp16_grp1->value & 0xfe40) == 0x9240
+ || (dsp16_grp1->value & 0xfe08) == 0xba08
+ || (dsp16_grp1->value & 0xfc00) == 0xbc00))
+ yyerror ("anomaly 05000074 - Multi-Issue Instruction with \
+ dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
+
return bfin_gen_multi_instr (dsp32, dsp16_grp1, dsp16_grp2);
}
Index: config/tc-bfin.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-bfin.c,v
retrieving revision 1.22
diff -c -p -r1.22 tc-bfin.c
*** config/tc-bfin.c 11 Aug 2009 18:28:29 -0000 1.22
--- config/tc-bfin.c 11 Aug 2009 18:42:14 -0000
*************** const char EXP_CHARS[] = "eE";
*** 305,318 ****
--- 305,482 ----
As in 0f12.456 or 0d1.2345e12. */
const char FLT_CHARS[] = "fFdDxX";
+ typedef enum bfin_cpu_type
+ {
+ BFIN_CPU_UNKNOWN,
+ BFIN_CPU_BF512,
+ BFIN_CPU_BF514,
+ BFIN_CPU_BF516,
+ BFIN_CPU_BF518,
+ BFIN_CPU_BF522,
+ BFIN_CPU_BF523,
+ BFIN_CPU_BF524,
+ BFIN_CPU_BF525,
+ BFIN_CPU_BF526,
+ BFIN_CPU_BF527,
+ BFIN_CPU_BF531,
+ BFIN_CPU_BF532,
+ BFIN_CPU_BF533,
+ BFIN_CPU_BF534,
+ BFIN_CPU_BF536,
+ BFIN_CPU_BF537,
+ BFIN_CPU_BF538,
+ BFIN_CPU_BF539,
+ BFIN_CPU_BF542,
+ BFIN_CPU_BF542M,
+ BFIN_CPU_BF544,
+ BFIN_CPU_BF544M,
+ BFIN_CPU_BF547,
+ BFIN_CPU_BF547M,
+ BFIN_CPU_BF548,
+ BFIN_CPU_BF548M,
+ BFIN_CPU_BF549,
+ BFIN_CPU_BF549M,
+ BFIN_CPU_BF561
+ } bfin_cpu_t;
+
+ bfin_cpu_t bfin_cpu_type = BFIN_CPU_UNKNOWN;
+ /* -msi-revision support. There are three special values:
+ -1 -msi-revision=none.
+ 0xffff -msi-revision=any. */
+ int bfin_si_revision;
+
+ unsigned int bfin_anomaly_checks = 0;
+
+ struct bfin_cpu
+ {
+ const char *name;
+ bfin_cpu_t type;
+ int si_revision;
+ unsigned int anomaly_checks;
+ };
+
+ struct bfin_cpu bfin_cpus[] =
+ {
+ {"bf512", BFIN_CPU_BF512, 0x0001, AC_05000074},
+ {"bf512", BFIN_CPU_BF512, 0x0000, AC_05000074},
+
+ {"bf514", BFIN_CPU_BF514, 0x0001, AC_05000074},
+ {"bf514", BFIN_CPU_BF514, 0x0000, AC_05000074},
+
+ {"bf516", BFIN_CPU_BF516, 0x0001, AC_05000074},
+ {"bf516", BFIN_CPU_BF516, 0x0000, AC_05000074},
+
+ {"bf518", BFIN_CPU_BF518, 0x0001, AC_05000074},
+ {"bf518", BFIN_CPU_BF518, 0x0000, AC_05000074},
+
+ {"bf522", BFIN_CPU_BF522, 0x0002, AC_05000074},
+ {"bf522", BFIN_CPU_BF522, 0x0001, AC_05000074},
+ {"bf522", BFIN_CPU_BF522, 0x0000, AC_05000074},
+
+ {"bf523", BFIN_CPU_BF523, 0x0002, AC_05000074},
+ {"bf523", BFIN_CPU_BF523, 0x0001, AC_05000074},
+ {"bf523", BFIN_CPU_BF523, 0x0000, AC_05000074},
+
+ {"bf524", BFIN_CPU_BF524, 0x0002, AC_05000074},
+ {"bf524", BFIN_CPU_BF524, 0x0001, AC_05000074},
+ {"bf524", BFIN_CPU_BF524, 0x0000, AC_05000074},
+
+ {"bf525", BFIN_CPU_BF525, 0x0002, AC_05000074},
+ {"bf525", BFIN_CPU_BF525, 0x0001, AC_05000074},
+ {"bf525", BFIN_CPU_BF525, 0x0000, AC_05000074},
+
+ {"bf526", BFIN_CPU_BF526, 0x0002, AC_05000074},
+ {"bf526", BFIN_CPU_BF526, 0x0001, AC_05000074},
+ {"bf526", BFIN_CPU_BF526, 0x0000, AC_05000074},
+
+ {"bf527", BFIN_CPU_BF527, 0x0002, AC_05000074},
+ {"bf527", BFIN_CPU_BF527, 0x0001, AC_05000074},
+ {"bf527", BFIN_CPU_BF527, 0x0000, AC_05000074},
+
+ {"bf531", BFIN_CPU_BF531, 0x0006, AC_05000074},
+ {"bf531", BFIN_CPU_BF531, 0x0005, AC_05000074},
+ {"bf531", BFIN_CPU_BF531, 0x0004, AC_05000074},
+ {"bf531", BFIN_CPU_BF531, 0x0003, AC_05000074},
+
+ {"bf532", BFIN_CPU_BF532, 0x0006, AC_05000074},
+ {"bf532", BFIN_CPU_BF532, 0x0005, AC_05000074},
+ {"bf532", BFIN_CPU_BF532, 0x0004, AC_05000074},
+ {"bf532", BFIN_CPU_BF532, 0x0003, AC_05000074},
+
+ {"bf533", BFIN_CPU_BF533, 0x0006, AC_05000074},
+ {"bf533", BFIN_CPU_BF533, 0x0005, AC_05000074},
+ {"bf533", BFIN_CPU_BF533, 0x0004, AC_05000074},
+ {"bf533", BFIN_CPU_BF533, 0x0003, AC_05000074},
+
+ {"bf534", BFIN_CPU_BF534, 0x0003, AC_05000074},
+ {"bf534", BFIN_CPU_BF534, 0x0002, AC_05000074},
+ {"bf534", BFIN_CPU_BF534, 0x0001, AC_05000074},
+
+ {"bf536", BFIN_CPU_BF536, 0x0003, AC_05000074},
+ {"bf536", BFIN_CPU_BF536, 0x0002, AC_05000074},
+ {"bf536", BFIN_CPU_BF536, 0x0001, AC_05000074},
+
+ {"bf537", BFIN_CPU_BF537, 0x0003, AC_05000074},
+ {"bf537", BFIN_CPU_BF537, 0x0002, AC_05000074},
+ {"bf537", BFIN_CPU_BF537, 0x0001, AC_05000074},
+
+ {"bf538", BFIN_CPU_BF538, 0x0005, AC_05000074},
+ {"bf538", BFIN_CPU_BF538, 0x0004, AC_05000074},
+ {"bf538", BFIN_CPU_BF538, 0x0003, AC_05000074},
+ {"bf538", BFIN_CPU_BF538, 0x0002, AC_05000074},
+
+ {"bf539", BFIN_CPU_BF539, 0x0005, AC_05000074},
+ {"bf539", BFIN_CPU_BF539, 0x0004, AC_05000074},
+ {"bf539", BFIN_CPU_BF539, 0x0003, AC_05000074},
+ {"bf539", BFIN_CPU_BF539, 0x0002, AC_05000074},
+
+ {"bf542m", BFIN_CPU_BF542M, 0x0003, AC_05000074},
+
+ {"bf542", BFIN_CPU_BF542, 0x0002, AC_05000074},
+ {"bf542", BFIN_CPU_BF542, 0x0001, AC_05000074},
+ {"bf542", BFIN_CPU_BF542, 0x0000, AC_05000074},
+
+ {"bf544m", BFIN_CPU_BF544M, 0x0003, AC_05000074},
+
+ {"bf544", BFIN_CPU_BF544, 0x0002, AC_05000074},
+ {"bf544", BFIN_CPU_BF544, 0x0001, AC_05000074},
+ {"bf544", BFIN_CPU_BF544, 0x0000, AC_05000074},
+
+ {"bf547m", BFIN_CPU_BF547M, 0x0003, AC_05000074},
+
+ {"bf547", BFIN_CPU_BF547, 0x0002, AC_05000074},
+ {"bf547", BFIN_CPU_BF547, 0x0001, AC_05000074},
+ {"bf547", BFIN_CPU_BF547, 0x0000, AC_05000074},
+
+ {"bf548m", BFIN_CPU_BF548M, 0x0003, AC_05000074},
+
+ {"bf548", BFIN_CPU_BF548, 0x0002, AC_05000074},
+ {"bf548", BFIN_CPU_BF548, 0x0001, AC_05000074},
+ {"bf548", BFIN_CPU_BF548, 0x0000, AC_05000074},
+
+ {"bf549m", BFIN_CPU_BF549M, 0x0003, AC_05000074},
+
+ {"bf549", BFIN_CPU_BF549, 0x0002, AC_05000074},
+ {"bf549", BFIN_CPU_BF549, 0x0001, AC_05000074},
+ {"bf549", BFIN_CPU_BF549, 0x0000, AC_05000074},
+
+ {"bf561", BFIN_CPU_BF561, 0x0005, AC_05000074},
+ {"bf561", BFIN_CPU_BF561, 0x0003, AC_05000074},
+ {"bf561", BFIN_CPU_BF561, 0x0002, AC_05000074},
+
+ {NULL, 0, 0, 0}
+ };
+
/* Define bfin-specific command-line options (there are none). */
const char *md_shortopts = "";
#define OPTION_FDPIC (OPTION_MD_BASE)
#define OPTION_NOPIC (OPTION_MD_BASE + 1)
+ #define OPTION_MCPU (OPTION_MD_BASE + 2)
struct option md_longopts[] =
{
+ { "mcpu", required_argument, NULL, OPTION_MCPU },
{ "mfdpic", no_argument, NULL, OPTION_FDPIC },
{ "mnopic", no_argument, NULL, OPTION_NOPIC },
{ "mno-fdpic", no_argument, NULL, OPTION_NOPIC },
*************** md_parse_option (int c ATTRIBUTE_UNUSED,
*** 330,335 ****
--- 494,569 ----
default:
return 0;
+ case OPTION_MCPU:
+ {
+ const char *p, *q;
+ int i;
+
+ i = 0;
+ while ((p = bfin_cpus[i].name) != NULL)
+ {
+ if (strncmp (arg, p, strlen (p)) == 0)
+ break;
+ i++;
+ }
+
+ if (p == NULL)
+ {
+ error ("-mcpu=%s is not valid", arg);
+ return 0;
+ }
+
+ bfin_cpu_type = bfin_cpus[i].type;
+
+ q = arg + strlen (p);
+
+ if (*q == '\0')
+ {
+ bfin_si_revision = bfin_cpus[i].si_revision;
+ bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks;
+ }
+ else if (strcmp (q, "-none") == 0)
+ bfin_si_revision = -1;
+ else if (strcmp (q, "-any") == 0)
+ {
+ bfin_si_revision = 0xffff;
+ while (bfin_cpus[i].type == bfin_cpu_type)
+ {
+ bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks;
+ i++;
+ }
+ }
+ else
+ {
+ unsigned int si_major, si_minor;
+ int rev_len, n;
+
+ rev_len = strlen (q);
+
+ if (sscanf (q, "-%u.%u%n", &si_major, &si_minor, &n) != 2
+ || n != rev_len
+ || si_major > 0xff || si_minor > 0xff)
+ {
+ invalid_silicon_revision:
+ error ("-mcpu=%s has invalid silicon revision", arg);
+ return 0;
+ }
+
+ bfin_si_revision = (si_major << 8) | si_minor;
+
+ while (bfin_cpus[i].type == bfin_cpu_type
+ && bfin_cpus[i].si_revision != bfin_si_revision)
+ i++;
+
+ if (bfin_cpus[i].type != bfin_cpu_type)
+ goto invalid_silicon_revision;
+
+ bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks;
+ }
+
+ break;
+ }
+
case OPTION_FDPIC:
bfin_flags |= EF_BFIN_FDPIC;
bfin_pic_flag = "-mfdpic";
Index: config/tc-bfin.h
===================================================================
RCS file: /cvs/src/src/gas/config/tc-bfin.h,v
retrieving revision 1.6
diff -c -p -r1.6 tc-bfin.h
*** config/tc-bfin.h 12 Aug 2008 23:39:30 -0000 1.6
--- config/tc-bfin.h 11 Aug 2009 18:42:14 -0000
*************** extern long md_pcrel_from_section (struc
*** 78,81 ****
--- 78,87 ----
/* This target is buggy, and sets fix size too large. */
#define TC_FX_SIZE_SLACK(FIX) 2
+ extern unsigned int bfin_anomaly_checks;
+
+ /* Anomaly checking */
+ #define AC_05000074 0x00000001
+ #define ENABLE_AC_05000074 (bfin_anomaly_checks & AC_05000074)
+
/* end of tc-bfin.h */
Index: doc/c-bfin.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-bfin.texi,v
retrieving revision 1.2
diff -c -p -r1.2 c-bfin.texi
*** doc/c-bfin.texi 24 Jul 2006 13:49:49 -0000 1.2
--- doc/c-bfin.texi 11 Aug 2009 18:42:14 -0000
***************
*** 14,27 ****
@cindex Blackfin support
@menu
! * BFIN Syntax:: BFIN Syntax
! * BFIN Directives:: BFIN Directives
@end menu
! @node BFIN Syntax
@section Syntax
! @cindex BFIN syntax
! @cindex syntax, BFIN
@table @code
@item Special Characters
--- 14,73 ----
@cindex Blackfin support
@menu
! * Blackfin Options:: Blackfin Options
! * Blackfin Syntax:: Blackfin Syntax
! * Blackfin Directives:: Blackfin Directives
@end menu
! @node Blackfin Options
! @section Options
! @cindex Blackfin options (none)
! @cindex options for Blackfin (none)
!
! @table @code
!
! @cindex @code{-mcpu=} command line option, Blackfin
! @item -mcpu=@var{processor}@r{[}-@var{sirevision}@r{]}
! This option specifies the target processor. The optional @var{sirevision}
! is not used in assembler. It's here such that GCC can easily pass down its
! @code{-mcpu=} option. The assembler will issue an
! error message if an attempt is made to assemble an instruction which
! will not execute on the target processor. The following processor names are
! recognized:
! @code{bf522},
! @code{bf523},
! @code{bf524},
! @code{bf525},
! @code{bf526},
! @code{bf527},
! @code{bf531},
! @code{bf532},
! @code{bf533},
! @code{bf534},
! @code{bf535} (not implemented yet),
! @code{bf536},
! @code{bf537},
! @code{bf538},
! @code{bf539},
! @code{bf542},
! @code{bf542m},
! @code{bf544},
! @code{bf544m},
! @code{bf547},
! @code{bf547m},
! @code{bf548},
! @code{bf548m},
! @code{bf549},
! @code{bf549m},
! and
! @code{bf561}.
!
! @end table
!
! @node Blackfin Syntax
@section Syntax
! @cindex Blackfin syntax
! @cindex syntax, Blackfin
@table @code
@item Special Characters
*************** the Blackfin(r) Processor Instruction Se
*** 164,173 ****
@end table
! @node BFIN Directives
@section Directives
! @cindex BFIN directives
! @cindex directives, BFIN
The following directives are provided for compatibility with the VDSP assembler.
--- 210,219 ----
@end table
! @node Blackfin Directives
@section Directives
! @cindex Blackfin directives
! @cindex directives, Blackfin
The following directives are provided for compatibility with the VDSP assembler.