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Re: [PATCH] Add LWP support for upcoming AMD Orochi processor
Hi,
On Thu, Nov 5, 2009 at 15:45, H.J. Lu <hjl.tools@gmail.com> wrote:
> There is no 32bit LWP test. Is LWP 64bit only? If yes, you need to
> add Cpu64 to LWP insns.
>
> Also please update doc/c-i386.texi.
>
LWP is supported both in 64 and 32 bit modes.
Fixed like this:
2009-11-05 Sebastian Pop <sebastian.pop@amd.com>
Quentin Neill <quentin.neill@amd.com>
* gas/config/tc-i386.c (cpu_arch): Add CPU_LWP_FLAGS.
(build_vex_prefix): Handle xop09 and xop0a.
(build_modrm_byte): Handle vexlwp.
(md_show_usage): Add lwp.
* gas/doc/c-i386.texi (i386-LWP): New section.
* gas/testsuite/gas/i386/i386.exp: Run x86-64-lwp in 64-bit mode,
run lwp in 32-bit mode.
* gas/testsuite/gas/i386/x86-64-lwp.d: New.
* gas/testsuite/gas/i386/x86-64-lwp.s: New.
* gas/testsuite/gas/i386/lwp.d: New.
* gas/testsuite/gas/i386/lwp.s: New.
* opcodes/i386-dis.c (OP_LWPCB_E): New.
(OP_LWP_E): New.
(OP_LWP_I): New.
(USE_XOP_8F_TABLE): New.
(XOP_8F_TABLE): New.
(REG_XOP_LWPCB): New.
(REG_XOP_LWP): New.
(XOP_09): New.
(XOP_0A): New.
(reg_table): Redirect REG_8F to XOP_8F_TABLE.
Add entries for REG_XOP_LWPCB and REG_XOP_LWP.
(xop_table): New.
(get_valid_dis386): Handle USE_XOP_8F_TABLE.
Use the offsets VEX_0F, VEX_0F38, and VEX_0F3A instead of their values
to access to the vex_table.
(OP_LWPCB_E): New.
(OP_LWP_E): New.
(OP_LWP_I): New.
* opcodes/i386-gen.c (cpu_flag_init): Add CPU_LWP_FLAGS, CpuLWP.
(cpu_flags): Add CpuLWP.
(opcode_modifiers): Add VexLWP, XOP09, and XOP0A.
* opcodes/i386-opc.h (CpuLWP): New.
(i386_cpu_flags): Add bit cpulwp.
(VexLWP): New.
(XOP09): New.
(XOP0A): New.
(i386_opcode_modifier): Add vexlwp, xop09, and xop0a.
* opcodes/i386-opc.tbl (llwpcb): Added.
(lwpval): Added.
(lwpins): Added.
Tested on x86-64-linux with make -k check.
Ok to commit?
Thanks,
Sebastian Pop
--
AMD / Open Source Compiler Engineering / GNU Tools
2009-11-05 Sebastian Pop <sebastian.pop@amd.com>
Quentin Neill <quentin.neill@amd.com>
* gas/config/tc-i386.c (cpu_arch): Add CPU_LWP_FLAGS.
(build_vex_prefix): Handle xop09 and xop0a.
(build_modrm_byte): Handle vexlwp.
(md_show_usage): Add lwp.
* gas/doc/c-i386.texi (i386-LWP): New section.
* gas/testsuite/gas/i386/i386.exp: Run x86-64-lwp in 64-bit mode,
run lwp in 32-bit mode.
* gas/testsuite/gas/i386/x86-64-lwp.d: New.
* gas/testsuite/gas/i386/x86-64-lwp.s: New.
* gas/testsuite/gas/i386/lwp.d: New.
* gas/testsuite/gas/i386/lwp.s: New.
* opcodes/i386-dis.c (OP_LWPCB_E): New.
(OP_LWP_E): New.
(OP_LWP_I): New.
(USE_XOP_8F_TABLE): New.
(XOP_8F_TABLE): New.
(REG_XOP_LWPCB): New.
(REG_XOP_LWP): New.
(XOP_09): New.
(XOP_0A): New.
(reg_table): Redirect REG_8F to XOP_8F_TABLE.
Add entries for REG_XOP_LWPCB and REG_XOP_LWP.
(xop_table): New.
(get_valid_dis386): Handle USE_XOP_8F_TABLE.
Use the offsets VEX_0F, VEX_0F38, and VEX_0F3A instead of their values
to access to the vex_table.
(OP_LWPCB_E): New.
(OP_LWP_E): New.
(OP_LWP_I): New.
* opcodes/i386-gen.c (cpu_flag_init): Add CPU_LWP_FLAGS, CpuLWP.
(cpu_flags): Add CpuLWP.
(opcode_modifiers): Add VexLWP, XOP09, and XOP0A.
* opcodes/i386-opc.h (CpuLWP): New.
(i386_cpu_flags): Add bit cpulwp.
(VexLWP): New.
(XOP09): New.
(XOP0A): New.
(i386_opcode_modifier): Add vexlwp, xop09, and xop0a.
* opcodes/i386-opc.tbl (llwpcb): Added.
(lwpval): Added.
(lwpins): Added.
Index: gas/config/tc-i386.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-i386.c,v
retrieving revision 1.402
diff -u -d -d -u -p -r1.402 tc-i386.c
--- gas/config/tc-i386.c 29 Oct 2009 22:22:58 -0000 1.402
+++ gas/config/tc-i386.c 5 Nov 2009 22:44:36 -0000
@@ -641,6 +641,8 @@ static const arch_entry cpu_arch[] =
CPU_FMA_FLAGS },
{ ".fma4", PROCESSOR_UNKNOWN,
CPU_FMA4_FLAGS },
+ { ".lwp", PROCESSOR_UNKNOWN,
+ CPU_LWP_FLAGS },
{ ".movbe", PROCESSOR_UNKNOWN,
CPU_MOVBE_FLAGS },
{ ".ept", PROCESSOR_UNKNOWN,
@@ -2720,18 +2722,28 @@ build_vex_prefix (const insn_template *t
/* 3-byte VEX prefix. */
unsigned int m, w;
+ i.vex.length = 3;
+ i.vex.bytes[0] = 0xc4;
+
if (i.tm.opcode_modifier.vex0f)
m = 0x1;
else if (i.tm.opcode_modifier.vex0f38)
m = 0x2;
else if (i.tm.opcode_modifier.vex0f3a)
m = 0x3;
+ else if (i.tm.opcode_modifier.xop09)
+ {
+ m = 0x9;
+ i.vex.bytes[0] = 0x8f;
+ }
+ else if (i.tm.opcode_modifier.xop0a)
+ {
+ m = 0xa;
+ i.vex.bytes[0] = 0x8f;
+ }
else
abort ();
- i.vex.length = 3;
- i.vex.bytes[0] = 0xc4;
-
/* The high 3 bits of the second VEX byte are 1's compliment
of RXB bits from REX. */
i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
@@ -4936,7 +4948,8 @@ build_modrm_byte (void)
a instruction with VEX prefix and 3 sources. */
if (i.mem_operands == 0
&& ((i.reg_operands == 2
- && !i.tm.opcode_modifier.vexndd)
+ && !i.tm.opcode_modifier.vexndd
+ && !i.tm.opcode_modifier.vexlwp)
|| (i.reg_operands == 3
&& i.tm.opcode_modifier.vexnds)
|| (i.reg_operands == 4 && vex_3_sources)))
@@ -5252,11 +5265,22 @@ build_modrm_byte (void)
else
mem = ~0;
+ if (i.tm.opcode_modifier.vexlwp)
+ {
+ i.vex.register_specifier = i.op[2].regs;
+ if (!i.mem_operands)
+ {
+ i.rm.mode = 3;
+ i.rm.regmem = i.op[1].regs->reg_num;
+ if ((i.op[1].regs->reg_flags & RegRex) != 0)
+ i.rex |= REX_B;
+ }
+ }
/* Fill in i.rm.reg or i.rm.regmem field with register operand
(if any) based on i.tm.extension_opcode. Again, we must be
careful to make sure that segment/control/debug/test/MMX
registers are coded into the i.rm.reg field. */
- if (i.reg_operands)
+ else if (i.reg_operands)
{
unsigned int op;
unsigned int vex_reg = ~0;
@@ -5316,6 +5340,7 @@ build_modrm_byte (void)
&& !operand_type_equal (&i.tm.operand_types[vex_reg],
®ymm))
abort ();
+
i.vex.register_specifier = i.op[vex_reg].regs;
}
@@ -8019,7 +8044,7 @@ md_show_usage (stream)
ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
- svme, abm, padlock, fma4\n"));
+ svme, abm, padlock, fma4, lwp\n"));
fprintf (stream, _("\
-mtune=CPU optimize for CPU, CPU is one of:\n\
i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
Index: gas/doc/c-i386.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-i386.texi,v
retrieving revision 1.41
diff -u -d -d -u -p -r1.41 c-i386.texi
--- gas/doc/c-i386.texi 20 Oct 2009 22:18:18 -0000 1.41
+++ gas/doc/c-i386.texi 5 Nov 2009 22:44:36 -0000
@@ -32,6 +32,7 @@ extending the Intel architecture to 64-b
* i386-Jumps:: Handling of Jump Instructions
* i386-Float:: Floating Point
* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
+* i386-LWP:: AMD's Lightweight Profiling Instructions
* i386-16bit:: Writing 16-bit Code
* i386-Arch:: Specifying an x86 CPU architecture
* i386-Bugs:: AT&T Syntax bugs
@@ -799,6 +800,25 @@ as the floating point stack.
See Intel and AMD documentation, keeping in mind that the operand order in
instructions is reversed from the Intel syntax.
+@node i386-LWP
+@section AMD's Lightweight Profiling Instructions
+
+@cindex LWP, i386
+@cindex LWP, x86-64
+
+@code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
+instruction set, available on AMD's Family 15h (Orochi) processors.
+
+LWP enables applications to collect and manage performance data, and
+react to performance events. The collection of performance data
+requires no context switches. LWP runs in the context of a thread and
+so several counters can be used independently across multiple threads.
+LWP can be used in both 64-bit and legacy 32-bit modes.
+
+For detailed information on the LWP instruction set, see the
+@cite{AMD Lightweight Profiling Specification} available at
+@uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
+
@node i386-16bit
@section Writing 16-bit Code
Index: gas/testsuite/gas/i386/i386.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/i386/i386.exp,v
retrieving revision 1.122
diff -u -d -d -u -p -r1.122 i386.exp
--- gas/testsuite/gas/i386/i386.exp 24 Sep 2009 14:36:48 -0000 1.122
+++ gas/testsuite/gas/i386/i386.exp 5 Nov 2009 22:44:36 -0000
@@ -156,6 +156,7 @@ if [expr ([istarget "i*86-*-*"] || [ist
run_dump_test "fma"
run_dump_test "fma-intel"
run_dump_test "fma4"
+ run_dump_test "lwp"
# These tests require support for 8 and 16 bit relocs,
# so we only run them for ELF and COFF targets.
@@ -322,6 +323,7 @@ if [expr ([istarget "i*86-*-*"] || [ista
run_dump_test "x86-64-fma"
run_dump_test "x86-64-fma-intel"
run_dump_test "x86-64-fma4"
+ run_dump_test "x86-64-lwp"
if { ![istarget "*-*-aix*"]
&& ![istarget "*-*-beos*"]
Index: gas/testsuite/gas/i386/lwp.d
===================================================================
RCS file: gas/testsuite/gas/i386/lwp.d
diff -N gas/testsuite/gas/i386/lwp.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/i386/lwp.d 5 Nov 2009 22:44:36 -0000
@@ -0,0 +1,137 @@
+#objdump: -dw
+#name: x86-64 LWP
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 8f e9 78 12 c0[ ]+llwpcb %ax
+[ ]*[a-f0-9]+: 8f e9 78 12 c1[ ]+llwpcb %cx
+[ ]*[a-f0-9]+: 8f e9 78 12 c2[ ]+llwpcb %dx
+[ ]*[a-f0-9]+: 8f e9 78 12 c3[ ]+llwpcb %bx
+[ ]*[a-f0-9]+: 8f e9 78 12 c4[ ]+llwpcb %sp
+[ ]*[a-f0-9]+: 8f e9 78 12 c5[ ]+llwpcb %bp
+[ ]*[a-f0-9]+: 8f e9 78 12 c6[ ]+llwpcb %si
+[ ]*[a-f0-9]+: 8f e9 78 12 c7[ ]+llwpcb %di
+[ ]*[a-f0-9]+: 8f e9 7c 12 c0[ ]+llwpcb %eax
+[ ]*[a-f0-9]+: 8f e9 7c 12 c1[ ]+llwpcb %ecx
+[ ]*[a-f0-9]+: 8f e9 7c 12 c2[ ]+llwpcb %edx
+[ ]*[a-f0-9]+: 8f e9 7c 12 c3[ ]+llwpcb %ebx
+[ ]*[a-f0-9]+: 8f e9 7c 12 c4[ ]+llwpcb %esp
+[ ]*[a-f0-9]+: 8f e9 7c 12 c5[ ]+llwpcb %ebp
+[ ]*[a-f0-9]+: 8f e9 7c 12 c6[ ]+llwpcb %esi
+[ ]*[a-f0-9]+: 8f e9 7c 12 c7[ ]+llwpcb %edi
+[ ]*[a-f0-9]+: 8f e9 7c 12 cf[ ]+slwpcb %edi
+[ ]*[a-f0-9]+: 8f e9 7c 12 ce[ ]+slwpcb %esi
+[ ]*[a-f0-9]+: 8f e9 7c 12 cd[ ]+slwpcb %ebp
+[ ]*[a-f0-9]+: 8f e9 7c 12 cc[ ]+slwpcb %esp
+[ ]*[a-f0-9]+: 8f e9 7c 12 cb[ ]+slwpcb %ebx
+[ ]*[a-f0-9]+: 8f e9 7c 12 ca[ ]+slwpcb %edx
+[ ]*[a-f0-9]+: 8f e9 7c 12 c9[ ]+slwpcb %ecx
+[ ]*[a-f0-9]+: 8f e9 7c 12 c8[ ]+slwpcb %eax
+[ ]*[a-f0-9]+: 8f e9 78 12 cf[ ]+slwpcb %di
+[ ]*[a-f0-9]+: 8f e9 78 12 ce[ ]+slwpcb %si
+[ ]*[a-f0-9]+: 8f e9 78 12 cd[ ]+slwpcb %bp
+[ ]*[a-f0-9]+: 8f e9 78 12 cc[ ]+slwpcb %sp
+[ ]*[a-f0-9]+: 8f e9 78 12 cb[ ]+slwpcb %bx
+[ ]*[a-f0-9]+: 8f e9 78 12 ca[ ]+slwpcb %dx
+[ ]*[a-f0-9]+: 8f e9 78 12 c9[ ]+slwpcb %cx
+[ ]*[a-f0-9]+: 8f e9 78 12 c8[ ]+slwpcb %ax
+[ ]*[a-f0-9]+: 8f ea 78 12 c0 34 12[ ]+lwpins \$0x1234,%eax,%ax
+[ ]*[a-f0-9]+: 8f ea 70 12 c1 34 12[ ]+lwpins \$0x1234,%ecx,%cx
+[ ]*[a-f0-9]+: 8f ea 68 12 c2 34 12[ ]+lwpins \$0x1234,%edx,%dx
+[ ]*[a-f0-9]+: 8f ea 60 12 c3 34 12[ ]+lwpins \$0x1234,%ebx,%bx
+[ ]*[a-f0-9]+: 8f ea 58 12 c4 34 12[ ]+lwpins \$0x1234,%esp,%sp
+[ ]*[a-f0-9]+: 8f ea 50 12 c5 34 12[ ]+lwpins \$0x1234,%ebp,%bp
+[ ]*[a-f0-9]+: 8f ea 48 12 c6 34 12[ ]+lwpins \$0x1234,%esi,%si
+[ ]*[a-f0-9]+: 8f ea 40 12 c7 34 12[ ]+lwpins \$0x1234,%edi,%di
+[ ]*[a-f0-9]+: 8f ea 7c 12 c7 78 56 34 12[ ]+lwpins \$0x12345678,%edi,%eax
+[ ]*[a-f0-9]+: 8f ea 74 12 c6 78 56 34 12[ ]+lwpins \$0x12345678,%esi,%ecx
+[ ]*[a-f0-9]+: 8f ea 6c 12 c5 78 56 34 12[ ]+lwpins \$0x12345678,%ebp,%edx
+[ ]*[a-f0-9]+: 8f ea 64 12 c4 78 56 34 12[ ]+lwpins \$0x12345678,%esp,%ebx
+[ ]*[a-f0-9]+: 8f ea 5c 12 c3 78 56 34 12[ ]+lwpins \$0x12345678,%ebx,%esp
+[ ]*[a-f0-9]+: 8f ea 54 12 c2 78 56 34 12[ ]+lwpins \$0x12345678,%edx,%ebp
+[ ]*[a-f0-9]+: 8f ea 4c 12 c1 78 56 34 12[ ]+lwpins \$0x12345678,%ecx,%esi
+[ ]*[a-f0-9]+: 8f ea 44 12 c0 78 56 34 12[ ]+lwpins \$0x12345678,%eax,%edi
+[ ]*[a-f0-9]+: 8f ea 78 12 c8 34 12[ ]+lwpval \$0x1234,%eax,%ax
+[ ]*[a-f0-9]+: 8f ea 70 12 c9 34 12[ ]+lwpval \$0x1234,%ecx,%cx
+[ ]*[a-f0-9]+: 8f ea 68 12 ca 34 12[ ]+lwpval \$0x1234,%edx,%dx
+[ ]*[a-f0-9]+: 8f ea 60 12 cb 34 12[ ]+lwpval \$0x1234,%ebx,%bx
+[ ]*[a-f0-9]+: 8f ea 58 12 cc 34 12[ ]+lwpval \$0x1234,%esp,%sp
+[ ]*[a-f0-9]+: 8f ea 50 12 cd 34 12[ ]+lwpval \$0x1234,%ebp,%bp
+[ ]*[a-f0-9]+: 8f ea 48 12 ce 34 12[ ]+lwpval \$0x1234,%esi,%si
+[ ]*[a-f0-9]+: 8f ea 40 12 cf 34 12[ ]+lwpval \$0x1234,%edi,%di
+[ ]*[a-f0-9]+: 8f ea 7c 12 cf 78 56 34 12[ ]+lwpval \$0x12345678,%edi,%eax
+[ ]*[a-f0-9]+: 8f ea 74 12 ce 78 56 34 12[ ]+lwpval \$0x12345678,%esi,%ecx
+[ ]*[a-f0-9]+: 8f ea 6c 12 cd 78 56 34 12[ ]+lwpval \$0x12345678,%ebp,%edx
+[ ]*[a-f0-9]+: 8f ea 64 12 cc 78 56 34 12[ ]+lwpval \$0x12345678,%esp,%ebx
+[ ]*[a-f0-9]+: 8f ea 5c 12 cb 78 56 34 12[ ]+lwpval \$0x12345678,%ebx,%esp
+[ ]*[a-f0-9]+: 8f ea 54 12 ca 78 56 34 12[ ]+lwpval \$0x12345678,%edx,%ebp
+[ ]*[a-f0-9]+: 8f ea 4c 12 c9 78 56 34 12[ ]+lwpval \$0x12345678,%ecx,%esi
+[ ]*[a-f0-9]+: 8f ea 44 12 c8 78 56 34 12[ ]+lwpval \$0x12345678,%eax,%edi
+[ ]*[a-f0-9]+: 8f ea 78 12 00 34 12[ ]+lwpins \$0x1234,\(%eax\),%ax
+[ ]*[a-f0-9]+: 8f ea 70 12 01 34 12[ ]+lwpins \$0x1234,\(%ecx\),%cx
+[ ]*[a-f0-9]+: 8f ea 68 12 02 34 12[ ]+lwpins \$0x1234,\(%edx\),%dx
+[ ]*[a-f0-9]+: 8f ea 60 12 03 34 12[ ]+lwpins \$0x1234,\(%ebx\),%bx
+[ ]*[a-f0-9]+: 8f ea 58 12 04 24 34 12[ ]+lwpins \$0x1234,\(%esp\),%sp
+[ ]*[a-f0-9]+: 8f ea 50 12 45 00 34 12[ ]+lwpins \$0x1234,0x0\(%ebp\),%bp
+[ ]*[a-f0-9]+: 8f ea 48 12 06 34 12[ ]+lwpins \$0x1234,\(%esi\),%si
+[ ]*[a-f0-9]+: 8f ea 40 12 07 34 12[ ]+lwpins \$0x1234,\(%edi\),%di
+[ ]*[a-f0-9]+: 8f ea 7c 12 07 78 56 34 12[ ]+lwpins \$0x12345678,\(%edi\),%eax
+[ ]*[a-f0-9]+: 8f ea 74 12 06 78 56 34 12[ ]+lwpins \$0x12345678,\(%esi\),%ecx
+[ ]*[a-f0-9]+: 8f ea 6c 12 45 00 78 56 34 12[ ]+lwpins \$0x12345678,0x0\(%ebp\),%edx
+[ ]*[a-f0-9]+: 8f ea 64 12 04 24 78 56 34 12[ ]+lwpins \$0x12345678,\(%esp\),%ebx
+[ ]*[a-f0-9]+: 8f ea 5c 12 03 78 56 34 12[ ]+lwpins \$0x12345678,\(%ebx\),%esp
+[ ]*[a-f0-9]+: 8f ea 54 12 02 78 56 34 12[ ]+lwpins \$0x12345678,\(%edx\),%ebp
+[ ]*[a-f0-9]+: 8f ea 4c 12 01 78 56 34 12[ ]+lwpins \$0x12345678,\(%ecx\),%esi
+[ ]*[a-f0-9]+: 8f ea 44 12 00 78 56 34 12[ ]+lwpins \$0x12345678,\(%eax\),%edi
+[ ]*[a-f0-9]+: 8f ea 78 12 08 34 12[ ]+lwpval \$0x1234,\(%eax\),%ax
+[ ]*[a-f0-9]+: 8f ea 70 12 09 34 12[ ]+lwpval \$0x1234,\(%ecx\),%cx
+[ ]*[a-f0-9]+: 8f ea 68 12 0a 34 12[ ]+lwpval \$0x1234,\(%edx\),%dx
+[ ]*[a-f0-9]+: 8f ea 60 12 0b 34 12[ ]+lwpval \$0x1234,\(%ebx\),%bx
+[ ]*[a-f0-9]+: 8f ea 58 12 0c 24 34 12[ ]+lwpval \$0x1234,\(%esp\),%sp
+[ ]*[a-f0-9]+: 8f ea 50 12 4d 00 34 12[ ]+lwpval \$0x1234,0x0\(%ebp\),%bp
+[ ]*[a-f0-9]+: 8f ea 48 12 0e 34 12[ ]+lwpval \$0x1234,\(%esi\),%si
+[ ]*[a-f0-9]+: 8f ea 40 12 0f 34 12[ ]+lwpval \$0x1234,\(%edi\),%di
+[ ]*[a-f0-9]+: 8f ea 7c 12 0f 78 56 34 12[ ]+lwpval \$0x12345678,\(%edi\),%eax
+[ ]*[a-f0-9]+: 8f ea 74 12 0e 78 56 34 12[ ]+lwpval \$0x12345678,\(%esi\),%ecx
+[ ]*[a-f0-9]+: 8f ea 6c 12 4d 00 78 56 34 12[ ]+lwpval \$0x12345678,0x0\(%ebp\),%edx
+[ ]*[a-f0-9]+: 8f ea 64 12 0c 24 78 56 34 12[ ]+lwpval \$0x12345678,\(%esp\),%ebx
+[ ]*[a-f0-9]+: 8f ea 5c 12 0b 78 56 34 12[ ]+lwpval \$0x12345678,\(%ebx\),%esp
+[ ]*[a-f0-9]+: 8f ea 54 12 0a 78 56 34 12[ ]+lwpval \$0x12345678,\(%edx\),%ebp
+[ ]*[a-f0-9]+: 8f ea 4c 12 09 78 56 34 12[ ]+lwpval \$0x12345678,\(%ecx\),%esi
+[ ]*[a-f0-9]+: 8f ea 44 12 08 78 56 34 12[ ]+lwpval \$0x12345678,\(%eax\),%edi
+[ ]*[a-f0-9]+: 8f ea 78 12 80 fe ca 00 00 34 12[ ]+lwpins \$0x1234,0xcafe\(%eax\),%ax
+[ ]*[a-f0-9]+: 8f ea 70 12 81 fe ca 00 00 34 12[ ]+lwpins \$0x1234,0xcafe\(%ecx\),%cx
+[ ]*[a-f0-9]+: 8f ea 68 12 82 fe ca 00 00 34 12[ ]+lwpins \$0x1234,0xcafe\(%edx\),%dx
+[ ]*[a-f0-9]+: 8f ea 60 12 83 fe ca 00 00 34 12[ ]+lwpins \$0x1234,0xcafe\(%ebx\),%bx
+[ ]*[a-f0-9]+: 8f ea 58 12 84 24 fe ca 00 00 34 12[ ]+lwpins \$0x1234,0xcafe\(%esp\),%sp
+[ ]*[a-f0-9]+: 8f ea 50 12 85 fe ca 00 00 34 12[ ]+lwpins \$0x1234,0xcafe\(%ebp\),%bp
+[ ]*[a-f0-9]+: 8f ea 48 12 86 fe ca 00 00 34 12[ ]+lwpins \$0x1234,0xcafe\(%esi\),%si
+[ ]*[a-f0-9]+: 8f ea 40 12 87 fe ca 00 00 34 12[ ]+lwpins \$0x1234,0xcafe\(%edi\),%di
+[ ]*[a-f0-9]+: 8f ea 7c 12 87 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%edi\),%eax
+[ ]*[a-f0-9]+: 8f ea 74 12 86 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%esi\),%ecx
+[ ]*[a-f0-9]+: 8f ea 6c 12 85 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%ebp\),%edx
+[ ]*[a-f0-9]+: 8f ea 64 12 84 24 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%esp\),%ebx
+[ ]*[a-f0-9]+: 8f ea 5c 12 83 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%ebx\),%esp
+[ ]*[a-f0-9]+: 8f ea 54 12 82 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%edx\),%ebp
+[ ]*[a-f0-9]+: 8f ea 4c 12 81 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%ecx\),%esi
+[ ]*[a-f0-9]+: 8f ea 44 12 80 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%eax\),%edi
+[ ]*[a-f0-9]+: 8f ea 78 12 88 fe ca 00 00 34 12[ ]+lwpval \$0x1234,0xcafe\(%eax\),%ax
+[ ]*[a-f0-9]+: 8f ea 70 12 89 fe ca 00 00 34 12[ ]+lwpval \$0x1234,0xcafe\(%ecx\),%cx
+[ ]*[a-f0-9]+: 8f ea 68 12 8a fe ca 00 00 34 12[ ]+lwpval \$0x1234,0xcafe\(%edx\),%dx
+[ ]*[a-f0-9]+: 8f ea 60 12 8b fe ca 00 00 34 12[ ]+lwpval \$0x1234,0xcafe\(%ebx\),%bx
+[ ]*[a-f0-9]+: 8f ea 58 12 8c 24 fe ca 00 00 34 12[ ]+lwpval \$0x1234,0xcafe\(%esp\),%sp
+[ ]*[a-f0-9]+: 8f ea 50 12 8d fe ca 00 00 34 12[ ]+lwpval \$0x1234,0xcafe\(%ebp\),%bp
+[ ]*[a-f0-9]+: 8f ea 48 12 8e fe ca 00 00 34 12[ ]+lwpval \$0x1234,0xcafe\(%esi\),%si
+[ ]*[a-f0-9]+: 8f ea 40 12 8f fe ca 00 00 34 12[ ]+lwpval \$0x1234,0xcafe\(%edi\),%di
+[ ]*[a-f0-9]+: 8f ea 7c 12 8f fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%edi\),%eax
+[ ]*[a-f0-9]+: 8f ea 74 12 8e fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%esi\),%ecx
+[ ]*[a-f0-9]+: 8f ea 6c 12 8d fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%ebp\),%edx
+[ ]*[a-f0-9]+: 8f ea 64 12 8c 24 fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%esp\),%ebx
+[ ]*[a-f0-9]+: 8f ea 5c 12 8b fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%ebx\),%esp
+[ ]*[a-f0-9]+: 8f ea 54 12 8a fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%edx\),%ebp
+[ ]*[a-f0-9]+: 8f ea 4c 12 89 fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%ecx\),%esi
+[ ]*[a-f0-9]+: 8f ea 44 12 88 fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%eax\),%edi
+#pass
Index: gas/testsuite/gas/i386/lwp.s
===================================================================
RCS file: gas/testsuite/gas/i386/lwp.s
diff -N gas/testsuite/gas/i386/lwp.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/i386/lwp.s 5 Nov 2009 22:44:36 -0000
@@ -0,0 +1,141 @@
+# Check 64bit LWP instructions
+
+ .allow_index_reg
+ .text
+_start:
+
+ llwpcb %ax
+ llwpcb %cx
+ llwpcb %dx
+ llwpcb %bx
+ llwpcb %sp
+ llwpcb %bp
+ llwpcb %si
+ llwpcb %di
+ llwpcb %eax
+ llwpcb %ecx
+ llwpcb %edx
+ llwpcb %ebx
+ llwpcb %esp
+ llwpcb %ebp
+ llwpcb %esi
+ llwpcb %edi
+
+ slwpcb %edi
+ slwpcb %esi
+ slwpcb %ebp
+ slwpcb %esp
+ slwpcb %ebx
+ slwpcb %edx
+ slwpcb %ecx
+ slwpcb %eax
+ slwpcb %di
+ slwpcb %si
+ slwpcb %bp
+ slwpcb %sp
+ slwpcb %bx
+ slwpcb %dx
+ slwpcb %cx
+ slwpcb %ax
+
+ lwpins $0x1234, %eax, %ax
+ lwpins $0x1234, %ecx, %cx
+ lwpins $0x1234, %edx, %dx
+ lwpins $0x1234, %ebx, %bx
+ lwpins $0x1234, %esp, %sp
+ lwpins $0x1234, %ebp, %bp
+ lwpins $0x1234, %esi, %si
+ lwpins $0x1234, %edi, %di
+ lwpins $0x12345678, %edi, %eax
+ lwpins $0x12345678, %esi, %ecx
+ lwpins $0x12345678, %ebp, %edx
+ lwpins $0x12345678, %esp, %ebx
+ lwpins $0x12345678, %ebx, %esp
+ lwpins $0x12345678, %edx, %ebp
+ lwpins $0x12345678, %ecx, %esi
+ lwpins $0x12345678, %eax, %edi
+
+ lwpval $0x1234, %eax, %ax
+ lwpval $0x1234, %ecx, %cx
+ lwpval $0x1234, %edx, %dx
+ lwpval $0x1234, %ebx, %bx
+ lwpval $0x1234, %esp, %sp
+ lwpval $0x1234, %ebp, %bp
+ lwpval $0x1234, %esi, %si
+ lwpval $0x1234, %edi, %di
+ lwpval $0x12345678, %edi, %eax
+ lwpval $0x12345678, %esi, %ecx
+ lwpval $0x12345678, %ebp, %edx
+ lwpval $0x12345678, %esp, %ebx
+ lwpval $0x12345678, %ebx, %esp
+ lwpval $0x12345678, %edx, %ebp
+ lwpval $0x12345678, %ecx, %esi
+ lwpval $0x12345678, %eax, %edi
+
+ lwpins $0x1234, (%eax), %ax
+ lwpins $0x1234, (%ecx), %cx
+ lwpins $0x1234, (%edx), %dx
+ lwpins $0x1234, (%ebx), %bx
+ lwpins $0x1234, (%esp), %sp
+ lwpins $0x1234, (%ebp), %bp
+ lwpins $0x1234, (%esi), %si
+ lwpins $0x1234, (%edi), %di
+ lwpins $0x12345678, (%edi), %eax
+ lwpins $0x12345678, (%esi), %ecx
+ lwpins $0x12345678, (%ebp), %edx
+ lwpins $0x12345678, (%esp), %ebx
+ lwpins $0x12345678, (%ebx), %esp
+ lwpins $0x12345678, (%edx), %ebp
+ lwpins $0x12345678, (%ecx), %esi
+ lwpins $0x12345678, (%eax), %edi
+
+ lwpval $0x1234, (%eax), %ax
+ lwpval $0x1234, (%ecx), %cx
+ lwpval $0x1234, (%edx), %dx
+ lwpval $0x1234, (%ebx), %bx
+ lwpval $0x1234, (%esp), %sp
+ lwpval $0x1234, (%ebp), %bp
+ lwpval $0x1234, (%esi), %si
+ lwpval $0x1234, (%edi), %di
+ lwpval $0x12345678, (%edi), %eax
+ lwpval $0x12345678, (%esi), %ecx
+ lwpval $0x12345678, (%ebp), %edx
+ lwpval $0x12345678, (%esp), %ebx
+ lwpval $0x12345678, (%ebx), %esp
+ lwpval $0x12345678, (%edx), %ebp
+ lwpval $0x12345678, (%ecx), %esi
+ lwpval $0x12345678, (%eax), %edi
+
+ lwpins $0x1234, 0xcafe(%eax), %ax
+ lwpins $0x1234, 0xcafe(%ecx), %cx
+ lwpins $0x1234, 0xcafe(%edx), %dx
+ lwpins $0x1234, 0xcafe(%ebx), %bx
+ lwpins $0x1234, 0xcafe(%esp), %sp
+ lwpins $0x1234, 0xcafe(%ebp), %bp
+ lwpins $0x1234, 0xcafe(%esi), %si
+ lwpins $0x1234, 0xcafe(%edi), %di
+ lwpins $0x12345678, 0xcafe(%edi), %eax
+ lwpins $0x12345678, 0xcafe(%esi), %ecx
+ lwpins $0x12345678, 0xcafe(%ebp), %edx
+ lwpins $0x12345678, 0xcafe(%esp), %ebx
+ lwpins $0x12345678, 0xcafe(%ebx), %esp
+ lwpins $0x12345678, 0xcafe(%edx), %ebp
+ lwpins $0x12345678, 0xcafe(%ecx), %esi
+ lwpins $0x12345678, 0xcafe(%eax), %edi
+
+ lwpval $0x1234, 0xcafe(%eax), %ax
+ lwpval $0x1234, 0xcafe(%ecx), %cx
+ lwpval $0x1234, 0xcafe(%edx), %dx
+ lwpval $0x1234, 0xcafe(%ebx), %bx
+ lwpval $0x1234, 0xcafe(%esp), %sp
+ lwpval $0x1234, 0xcafe(%ebp), %bp
+ lwpval $0x1234, 0xcafe(%esi), %si
+ lwpval $0x1234, 0xcafe(%edi), %di
+ lwpval $0x12345678, 0xcafe(%edi), %eax
+ lwpval $0x12345678, 0xcafe(%esi), %ecx
+ lwpval $0x12345678, 0xcafe(%ebp), %edx
+ lwpval $0x12345678, 0xcafe(%esp), %ebx
+ lwpval $0x12345678, 0xcafe(%ebx), %esp
+ lwpval $0x12345678, 0xcafe(%edx), %ebp
+ lwpval $0x12345678, 0xcafe(%ecx), %esi
+ lwpval $0x12345678, 0xcafe(%eax), %edi
Index: gas/testsuite/gas/i386/x86-64-lwp.d
===================================================================
RCS file: gas/testsuite/gas/i386/x86-64-lwp.d
diff -N gas/testsuite/gas/i386/x86-64-lwp.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/i386/x86-64-lwp.d 5 Nov 2009 22:44:36 -0000
@@ -0,0 +1,201 @@
+#objdump: -dw
+#name: x86-64 LWP
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 8f e9 78 12 c0[ ]+llwpcb %ax
+[ ]*[a-f0-9]+: 8f e9 78 12 c1[ ]+llwpcb %cx
+[ ]*[a-f0-9]+: 8f e9 78 12 c2[ ]+llwpcb %dx
+[ ]*[a-f0-9]+: 8f e9 78 12 c3[ ]+llwpcb %bx
+[ ]*[a-f0-9]+: 8f e9 78 12 c4[ ]+llwpcb %sp
+[ ]*[a-f0-9]+: 8f e9 78 12 c5[ ]+llwpcb %bp
+[ ]*[a-f0-9]+: 8f e9 78 12 c6[ ]+llwpcb %si
+[ ]*[a-f0-9]+: 8f e9 78 12 c7[ ]+llwpcb %di
+[ ]*[a-f0-9]+: 8f e9 7c 12 c0[ ]+llwpcb %eax
+[ ]*[a-f0-9]+: 8f e9 7c 12 c1[ ]+llwpcb %ecx
+[ ]*[a-f0-9]+: 8f e9 7c 12 c2[ ]+llwpcb %edx
+[ ]*[a-f0-9]+: 8f e9 7c 12 c3[ ]+llwpcb %ebx
+[ ]*[a-f0-9]+: 8f e9 7c 12 c4[ ]+llwpcb %esp
+[ ]*[a-f0-9]+: 8f e9 7c 12 c5[ ]+llwpcb %ebp
+[ ]*[a-f0-9]+: 8f e9 7c 12 c6[ ]+llwpcb %esi
+[ ]*[a-f0-9]+: 8f e9 7c 12 c7[ ]+llwpcb %edi
+[ ]*[a-f0-9]+: 8f e9 f8 12 c0[ ]+llwpcb %rax
+[ ]*[a-f0-9]+: 8f e9 f8 12 c1[ ]+llwpcb %rcx
+[ ]*[a-f0-9]+: 8f e9 f8 12 c2[ ]+llwpcb %rdx
+[ ]*[a-f0-9]+: 8f e9 f8 12 c3[ ]+llwpcb %rbx
+[ ]*[a-f0-9]+: 8f e9 f8 12 c4[ ]+llwpcb %rsp
+[ ]*[a-f0-9]+: 8f e9 f8 12 c5[ ]+llwpcb %rbp
+[ ]*[a-f0-9]+: 8f e9 f8 12 c6[ ]+llwpcb %rsi
+[ ]*[a-f0-9]+: 8f e9 f8 12 c7[ ]+llwpcb %rdi
+[ ]*[a-f0-9]+: 8f e9 f8 12 cf[ ]+slwpcb %rdi
+[ ]*[a-f0-9]+: 8f e9 f8 12 ce[ ]+slwpcb %rsi
+[ ]*[a-f0-9]+: 8f e9 f8 12 cd[ ]+slwpcb %rbp
+[ ]*[a-f0-9]+: 8f e9 f8 12 cc[ ]+slwpcb %rsp
+[ ]*[a-f0-9]+: 8f e9 f8 12 cb[ ]+slwpcb %rbx
+[ ]*[a-f0-9]+: 8f e9 f8 12 ca[ ]+slwpcb %rdx
+[ ]*[a-f0-9]+: 8f e9 f8 12 c9[ ]+slwpcb %rcx
+[ ]*[a-f0-9]+: 8f e9 f8 12 c8[ ]+slwpcb %rax
+[ ]*[a-f0-9]+: 8f e9 7c 12 cf[ ]+slwpcb %edi
+[ ]*[a-f0-9]+: 8f e9 7c 12 ce[ ]+slwpcb %esi
+[ ]*[a-f0-9]+: 8f e9 7c 12 cd[ ]+slwpcb %ebp
+[ ]*[a-f0-9]+: 8f e9 7c 12 cc[ ]+slwpcb %esp
+[ ]*[a-f0-9]+: 8f e9 7c 12 cb[ ]+slwpcb %ebx
+[ ]*[a-f0-9]+: 8f e9 7c 12 ca[ ]+slwpcb %edx
+[ ]*[a-f0-9]+: 8f e9 7c 12 c9[ ]+slwpcb %ecx
+[ ]*[a-f0-9]+: 8f e9 7c 12 c8[ ]+slwpcb %eax
+[ ]*[a-f0-9]+: 8f e9 78 12 cf[ ]+slwpcb %di
+[ ]*[a-f0-9]+: 8f e9 78 12 ce[ ]+slwpcb %si
+[ ]*[a-f0-9]+: 8f e9 78 12 cd[ ]+slwpcb %bp
+[ ]*[a-f0-9]+: 8f e9 78 12 cc[ ]+slwpcb %sp
+[ ]*[a-f0-9]+: 8f e9 78 12 cb[ ]+slwpcb %bx
+[ ]*[a-f0-9]+: 8f e9 78 12 ca[ ]+slwpcb %dx
+[ ]*[a-f0-9]+: 8f e9 78 12 c9[ ]+slwpcb %cx
+[ ]*[a-f0-9]+: 8f e9 78 12 c8[ ]+slwpcb %ax
+[ ]*[a-f0-9]+: 8f ea 78 12 c0 34 12[ ]+lwpins \$0x1234,%eax,%ax
+[ ]*[a-f0-9]+: 8f ea 70 12 c1 34 12[ ]+lwpins \$0x1234,%ecx,%cx
+[ ]*[a-f0-9]+: 8f ea 68 12 c2 34 12[ ]+lwpins \$0x1234,%edx,%dx
+[ ]*[a-f0-9]+: 8f ea 60 12 c3 34 12[ ]+lwpins \$0x1234,%ebx,%bx
+[ ]*[a-f0-9]+: 8f ea 58 12 c4 34 12[ ]+lwpins \$0x1234,%esp,%sp
+[ ]*[a-f0-9]+: 8f ea 50 12 c5 34 12[ ]+lwpins \$0x1234,%ebp,%bp
+[ ]*[a-f0-9]+: 8f ea 48 12 c6 34 12[ ]+lwpins \$0x1234,%esi,%si
+[ ]*[a-f0-9]+: 8f ea 40 12 c7 34 12[ ]+lwpins \$0x1234,%edi,%di
+[ ]*[a-f0-9]+: 8f ea 7c 12 c7 78 56 34 12[ ]+lwpins \$0x12345678,%edi,%eax
+[ ]*[a-f0-9]+: 8f ea 74 12 c6 78 56 34 12[ ]+lwpins \$0x12345678,%esi,%ecx
+[ ]*[a-f0-9]+: 8f ea 6c 12 c5 78 56 34 12[ ]+lwpins \$0x12345678,%ebp,%edx
+[ ]*[a-f0-9]+: 8f ea 64 12 c4 78 56 34 12[ ]+lwpins \$0x12345678,%esp,%ebx
+[ ]*[a-f0-9]+: 8f ea 5c 12 c3 78 56 34 12[ ]+lwpins \$0x12345678,%ebx,%esp
+[ ]*[a-f0-9]+: 8f ea 54 12 c2 78 56 34 12[ ]+lwpins \$0x12345678,%edx,%ebp
+[ ]*[a-f0-9]+: 8f ea 4c 12 c1 78 56 34 12[ ]+lwpins \$0x12345678,%ecx,%esi
+[ ]*[a-f0-9]+: 8f ea 44 12 c0 78 56 34 12[ ]+lwpins \$0x12345678,%eax,%edi
+[ ]*[a-f0-9]+: 8f ea f8 12 c0 78 56 34 12[ ]+lwpins \$0x12345678,%eax,%rax
+[ ]*[a-f0-9]+: 8f ea f0 12 c1 78 56 34 12[ ]+lwpins \$0x12345678,%ecx,%rcx
+[ ]*[a-f0-9]+: 8f ea e8 12 c2 78 56 34 12[ ]+lwpins \$0x12345678,%edx,%rdx
+[ ]*[a-f0-9]+: 8f ea e0 12 c3 78 56 34 12[ ]+lwpins \$0x12345678,%ebx,%rbx
+[ ]*[a-f0-9]+: 8f ea d8 12 c4 78 56 34 12[ ]+lwpins \$0x12345678,%esp,%rsp
+[ ]*[a-f0-9]+: 8f ea d0 12 c5 78 56 34 12[ ]+lwpins \$0x12345678,%ebp,%rbp
+[ ]*[a-f0-9]+: 8f ea c8 12 c6 78 56 34 12[ ]+lwpins \$0x12345678,%esi,%rsi
+[ ]*[a-f0-9]+: 8f ea c0 12 c7 78 56 34 12[ ]+lwpins \$0x12345678,%edi,%rdi
+[ ]*[a-f0-9]+: 8f ea 78 12 c8 34 12[ ]+lwpval \$0x1234,%eax,%ax
+[ ]*[a-f0-9]+: 8f ea 70 12 c9 34 12[ ]+lwpval \$0x1234,%ecx,%cx
+[ ]*[a-f0-9]+: 8f ea 68 12 ca 34 12[ ]+lwpval \$0x1234,%edx,%dx
+[ ]*[a-f0-9]+: 8f ea 60 12 cb 34 12[ ]+lwpval \$0x1234,%ebx,%bx
+[ ]*[a-f0-9]+: 8f ea 58 12 cc 34 12[ ]+lwpval \$0x1234,%esp,%sp
+[ ]*[a-f0-9]+: 8f ea 50 12 cd 34 12[ ]+lwpval \$0x1234,%ebp,%bp
+[ ]*[a-f0-9]+: 8f ea 48 12 ce 34 12[ ]+lwpval \$0x1234,%esi,%si
+[ ]*[a-f0-9]+: 8f ea 40 12 cf 34 12[ ]+lwpval \$0x1234,%edi,%di
+[ ]*[a-f0-9]+: 8f ea 7c 12 cf 78 56 34 12[ ]+lwpval \$0x12345678,%edi,%eax
+[ ]*[a-f0-9]+: 8f ea 74 12 ce 78 56 34 12[ ]+lwpval \$0x12345678,%esi,%ecx
+[ ]*[a-f0-9]+: 8f ea 6c 12 cd 78 56 34 12[ ]+lwpval \$0x12345678,%ebp,%edx
+[ ]*[a-f0-9]+: 8f ea 64 12 cc 78 56 34 12[ ]+lwpval \$0x12345678,%esp,%ebx
+[ ]*[a-f0-9]+: 8f ea 5c 12 cb 78 56 34 12[ ]+lwpval \$0x12345678,%ebx,%esp
+[ ]*[a-f0-9]+: 8f ea 54 12 ca 78 56 34 12[ ]+lwpval \$0x12345678,%edx,%ebp
+[ ]*[a-f0-9]+: 8f ea 4c 12 c9 78 56 34 12[ ]+lwpval \$0x12345678,%ecx,%esi
+[ ]*[a-f0-9]+: 8f ea 44 12 c8 78 56 34 12[ ]+lwpval \$0x12345678,%eax,%edi
+[ ]*[a-f0-9]+: 8f ea f8 12 c8 78 56 34 12[ ]+lwpval \$0x12345678,%eax,%rax
+[ ]*[a-f0-9]+: 8f ea f0 12 c9 78 56 34 12[ ]+lwpval \$0x12345678,%ecx,%rcx
+[ ]*[a-f0-9]+: 8f ea e8 12 ca 78 56 34 12[ ]+lwpval \$0x12345678,%edx,%rdx
+[ ]*[a-f0-9]+: 8f ea e0 12 cb 78 56 34 12[ ]+lwpval \$0x12345678,%ebx,%rbx
+[ ]*[a-f0-9]+: 8f ea d8 12 cc 78 56 34 12[ ]+lwpval \$0x12345678,%esp,%rsp
+[ ]*[a-f0-9]+: 8f ea d0 12 cd 78 56 34 12[ ]+lwpval \$0x12345678,%ebp,%rbp
+[ ]*[a-f0-9]+: 8f ea c8 12 ce 78 56 34 12[ ]+lwpval \$0x12345678,%esi,%rsi
+[ ]*[a-f0-9]+: 8f ea c0 12 cf 78 56 34 12[ ]+lwpval \$0x12345678,%edi,%rdi
+[ ]*[a-f0-9]+: 67 8f ea 78 12 00 34 12[ ]+addr32 lwpins \$0x1234,\(%eax\),%ax
+[ ]*[a-f0-9]+: 67 8f ea 70 12 01 34 12[ ]+addr32 lwpins \$0x1234,\(%ecx\),%cx
+[ ]*[a-f0-9]+: 67 8f ea 68 12 02 34 12[ ]+addr32 lwpins \$0x1234,\(%edx\),%dx
+[ ]*[a-f0-9]+: 67 8f ea 60 12 03 34 12[ ]+addr32 lwpins \$0x1234,\(%ebx\),%bx
+[ ]*[a-f0-9]+: 67 8f ea 58 12 04 24 34 12[ ]+addr32 lwpins \$0x1234,\(%esp\),%sp
+[ ]*[a-f0-9]+: 67 8f ea 50 12 45 00 34 12[ ]+addr32 lwpins \$0x1234,0x0\(%ebp\),%bp
+[ ]*[a-f0-9]+: 67 8f ea 48 12 06 34 12[ ]+addr32 lwpins \$0x1234,\(%esi\),%si
+[ ]*[a-f0-9]+: 67 8f ea 40 12 07 34 12[ ]+addr32 lwpins \$0x1234,\(%edi\),%di
+[ ]*[a-f0-9]+: 67 8f ea 7c 12 07 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%edi\),%eax
+[ ]*[a-f0-9]+: 67 8f ea 74 12 06 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%esi\),%ecx
+[ ]*[a-f0-9]+: 67 8f ea 6c 12 45 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0x0\(%ebp\),%edx
+[ ]*[a-f0-9]+: 67 8f ea 64 12 04 24 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%esp\),%ebx
+[ ]*[a-f0-9]+: 67 8f ea 5c 12 03 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%ebx\),%esp
+[ ]*[a-f0-9]+: 67 8f ea 54 12 02 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%edx\),%ebp
+[ ]*[a-f0-9]+: 67 8f ea 4c 12 01 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%ecx\),%esi
+[ ]*[a-f0-9]+: 67 8f ea 44 12 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%eax\),%edi
+[ ]*[a-f0-9]+: 67 8f ea f8 12 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%eax\),%rax
+[ ]*[a-f0-9]+: 67 8f ea f0 12 01 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%ecx\),%rcx
+[ ]*[a-f0-9]+: 67 8f ea e8 12 02 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%edx\),%rdx
+[ ]*[a-f0-9]+: 67 8f ea e0 12 03 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%ebx\),%rbx
+[ ]*[a-f0-9]+: 67 8f ea d8 12 04 24 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%esp\),%rsp
+[ ]*[a-f0-9]+: 67 8f ea d0 12 45 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0x0\(%ebp\),%rbp
+[ ]*[a-f0-9]+: 67 8f ea c8 12 06 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%esi\),%rsi
+[ ]*[a-f0-9]+: 67 8f ea c0 12 07 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%edi\),%rdi
+[ ]*[a-f0-9]+: 67 8f ea 78 12 08 34 12[ ]+addr32 lwpval \$0x1234,\(%eax\),%ax
+[ ]*[a-f0-9]+: 67 8f ea 70 12 09 34 12[ ]+addr32 lwpval \$0x1234,\(%ecx\),%cx
+[ ]*[a-f0-9]+: 67 8f ea 68 12 0a 34 12[ ]+addr32 lwpval \$0x1234,\(%edx\),%dx
+[ ]*[a-f0-9]+: 67 8f ea 60 12 0b 34 12[ ]+addr32 lwpval \$0x1234,\(%ebx\),%bx
+[ ]*[a-f0-9]+: 67 8f ea 58 12 0c 24 34 12[ ]+addr32 lwpval \$0x1234,\(%esp\),%sp
+[ ]*[a-f0-9]+: 67 8f ea 50 12 4d 00 34 12[ ]+addr32 lwpval \$0x1234,0x0\(%ebp\),%bp
+[ ]*[a-f0-9]+: 67 8f ea 48 12 0e 34 12[ ]+addr32 lwpval \$0x1234,\(%esi\),%si
+[ ]*[a-f0-9]+: 67 8f ea 40 12 0f 34 12[ ]+addr32 lwpval \$0x1234,\(%edi\),%di
+[ ]*[a-f0-9]+: 67 8f ea 7c 12 0f 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%edi\),%eax
+[ ]*[a-f0-9]+: 67 8f ea 74 12 0e 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%esi\),%ecx
+[ ]*[a-f0-9]+: 67 8f ea 6c 12 4d 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0x0\(%ebp\),%edx
+[ ]*[a-f0-9]+: 67 8f ea 64 12 0c 24 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%esp\),%ebx
+[ ]*[a-f0-9]+: 67 8f ea 5c 12 0b 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%ebx\),%esp
+[ ]*[a-f0-9]+: 67 8f ea 54 12 0a 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%edx\),%ebp
+[ ]*[a-f0-9]+: 67 8f ea 4c 12 09 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%ecx\),%esi
+[ ]*[a-f0-9]+: 67 8f ea 44 12 08 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%eax\),%edi
+[ ]*[a-f0-9]+: 67 8f ea f8 12 08 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%eax\),%rax
+[ ]*[a-f0-9]+: 67 8f ea f0 12 09 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%ecx\),%rcx
+[ ]*[a-f0-9]+: 67 8f ea e8 12 0a 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%edx\),%rdx
+[ ]*[a-f0-9]+: 67 8f ea e0 12 0b 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%ebx\),%rbx
+[ ]*[a-f0-9]+: 67 8f ea d8 12 0c 24 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%esp\),%rsp
+[ ]*[a-f0-9]+: 67 8f ea d0 12 4d 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0x0\(%ebp\),%rbp
+[ ]*[a-f0-9]+: 67 8f ea c8 12 0e 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%esi\),%rsi
+[ ]*[a-f0-9]+: 67 8f ea c0 12 0f 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%edi\),%rdi
+[ ]*[a-f0-9]+: 67 8f ea 78 12 80 fe ca 00 00 34 12[ ]+addr32 lwpins \$0x1234,0xcafe\(%eax\),%ax
+[ ]*[a-f0-9]+: 67 8f ea 70 12 81 fe ca 00 00 34 12[ ]+addr32 lwpins \$0x1234,0xcafe\(%ecx\),%cx
+[ ]*[a-f0-9]+: 67 8f ea 68 12 82 fe ca 00 00 34 12[ ]+addr32 lwpins \$0x1234,0xcafe\(%edx\),%dx
+[ ]*[a-f0-9]+: 67 8f ea 60 12 83 fe ca 00 00 34 12[ ]+addr32 lwpins \$0x1234,0xcafe\(%ebx\),%bx
+[ ]*[a-f0-9]+: 67 8f ea 58 12 84 24 fe ca 00 00 34 12[ ]+addr32 lwpins \$0x1234,0xcafe\(%esp\),%sp
+[ ]*[a-f0-9]+: 67 8f ea 50 12 85 fe ca 00 00 34 12[ ]+addr32 lwpins \$0x1234,0xcafe\(%ebp\),%bp
+[ ]*[a-f0-9]+: 67 8f ea 48 12 86 fe ca 00 00 34 12[ ]+addr32 lwpins \$0x1234,0xcafe\(%esi\),%si
+[ ]*[a-f0-9]+: 67 8f ea 40 12 87 fe ca 00 00 34 12[ ]+addr32 lwpins \$0x1234,0xcafe\(%edi\),%di
+[ ]*[a-f0-9]+: 67 8f ea 7c 12 87 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%edi\),%eax
+[ ]*[a-f0-9]+: 67 8f ea 74 12 86 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%esi\),%ecx
+[ ]*[a-f0-9]+: 67 8f ea 6c 12 85 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%ebp\),%edx
+[ ]*[a-f0-9]+: 67 8f ea 64 12 84 24 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%esp\),%ebx
+[ ]*[a-f0-9]+: 67 8f ea 5c 12 83 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%ebx\),%esp
+[ ]*[a-f0-9]+: 67 8f ea 54 12 82 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%edx\),%ebp
+[ ]*[a-f0-9]+: 67 8f ea 4c 12 81 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%ecx\),%esi
+[ ]*[a-f0-9]+: 67 8f ea 44 12 80 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%eax\),%edi
+[ ]*[a-f0-9]+: 67 8f ea f8 12 80 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%eax\),%rax
+[ ]*[a-f0-9]+: 67 8f ea f0 12 81 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%ecx\),%rcx
+[ ]*[a-f0-9]+: 67 8f ea e8 12 82 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%edx\),%rdx
+[ ]*[a-f0-9]+: 67 8f ea e0 12 83 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%ebx\),%rbx
+[ ]*[a-f0-9]+: 67 8f ea d8 12 84 24 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%esp\),%rsp
+[ ]*[a-f0-9]+: 67 8f ea d0 12 85 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%ebp\),%rbp
+[ ]*[a-f0-9]+: 67 8f ea c8 12 86 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%esi\),%rsi
+[ ]*[a-f0-9]+: 67 8f ea c0 12 87 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%edi\),%rdi
+[ ]*[a-f0-9]+: 67 8f ea 78 12 88 fe ca 00 00 34 12[ ]+addr32 lwpval \$0x1234,0xcafe\(%eax\),%ax
+[ ]*[a-f0-9]+: 67 8f ea 70 12 89 fe ca 00 00 34 12[ ]+addr32 lwpval \$0x1234,0xcafe\(%ecx\),%cx
+[ ]*[a-f0-9]+: 67 8f ea 68 12 8a fe ca 00 00 34 12[ ]+addr32 lwpval \$0x1234,0xcafe\(%edx\),%dx
+[ ]*[a-f0-9]+: 67 8f ea 60 12 8b fe ca 00 00 34 12[ ]+addr32 lwpval \$0x1234,0xcafe\(%ebx\),%bx
+[ ]*[a-f0-9]+: 67 8f ea 58 12 8c 24 fe ca 00 00 34 12[ ]+addr32 lwpval \$0x1234,0xcafe\(%esp\),%sp
+[ ]*[a-f0-9]+: 67 8f ea 50 12 8d fe ca 00 00 34 12[ ]+addr32 lwpval \$0x1234,0xcafe\(%ebp\),%bp
+[ ]*[a-f0-9]+: 67 8f ea 48 12 8e fe ca 00 00 34 12[ ]+addr32 lwpval \$0x1234,0xcafe\(%esi\),%si
+[ ]*[a-f0-9]+: 67 8f ea 40 12 8f fe ca 00 00 34 12[ ]+addr32 lwpval \$0x1234,0xcafe\(%edi\),%di
+[ ]*[a-f0-9]+: 67 8f ea 7c 12 8f fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%edi\),%eax
+[ ]*[a-f0-9]+: 67 8f ea 74 12 8e fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%esi\),%ecx
+[ ]*[a-f0-9]+: 67 8f ea 6c 12 8d fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%ebp\),%edx
+[ ]*[a-f0-9]+: 67 8f ea 64 12 8c 24 fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%esp\),%ebx
+[ ]*[a-f0-9]+: 67 8f ea 5c 12 8b fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%ebx\),%esp
+[ ]*[a-f0-9]+: 67 8f ea 54 12 8a fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%edx\),%ebp
+[ ]*[a-f0-9]+: 67 8f ea 4c 12 89 fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%ecx\),%esi
+[ ]*[a-f0-9]+: 67 8f ea 44 12 88 fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%eax\),%edi
+[ ]*[a-f0-9]+: 67 8f ea f8 12 88 fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%eax\),%rax
+[ ]*[a-f0-9]+: 67 8f ea f0 12 89 fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%ecx\),%rcx
+[ ]*[a-f0-9]+: 67 8f ea e8 12 8a fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%edx\),%rdx
+[ ]*[a-f0-9]+: 67 8f ea e0 12 8b fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%ebx\),%rbx
+[ ]*[a-f0-9]+: 67 8f ea d8 12 8c 24 fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%esp\),%rsp
+[ ]*[a-f0-9]+: 67 8f ea d0 12 8d fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%ebp\),%rbp
+[ ]*[a-f0-9]+: 67 8f ea c8 12 8e fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%esi\),%rsi
+[ ]*[a-f0-9]+: 67 8f ea c0 12 8f fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%edi\),%rdi
+#pass
Index: gas/testsuite/gas/i386/x86-64-lwp.s
===================================================================
RCS file: gas/testsuite/gas/i386/x86-64-lwp.s
diff -N gas/testsuite/gas/i386/x86-64-lwp.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/i386/x86-64-lwp.s 5 Nov 2009 22:44:36 -0000
@@ -0,0 +1,205 @@
+# Check 64bit LWP instructions
+
+ .allow_index_reg
+ .text
+_start:
+
+ llwpcb %ax
+ llwpcb %cx
+ llwpcb %dx
+ llwpcb %bx
+ llwpcb %sp
+ llwpcb %bp
+ llwpcb %si
+ llwpcb %di
+ llwpcb %eax
+ llwpcb %ecx
+ llwpcb %edx
+ llwpcb %ebx
+ llwpcb %esp
+ llwpcb %ebp
+ llwpcb %esi
+ llwpcb %edi
+ llwpcb %rax
+ llwpcb %rcx
+ llwpcb %rdx
+ llwpcb %rbx
+ llwpcb %rsp
+ llwpcb %rbp
+ llwpcb %rsi
+ llwpcb %rdi
+
+ slwpcb %rdi
+ slwpcb %rsi
+ slwpcb %rbp
+ slwpcb %rsp
+ slwpcb %rbx
+ slwpcb %rdx
+ slwpcb %rcx
+ slwpcb %rax
+ slwpcb %edi
+ slwpcb %esi
+ slwpcb %ebp
+ slwpcb %esp
+ slwpcb %ebx
+ slwpcb %edx
+ slwpcb %ecx
+ slwpcb %eax
+ slwpcb %di
+ slwpcb %si
+ slwpcb %bp
+ slwpcb %sp
+ slwpcb %bx
+ slwpcb %dx
+ slwpcb %cx
+ slwpcb %ax
+
+ lwpins $0x1234, %eax, %ax
+ lwpins $0x1234, %ecx, %cx
+ lwpins $0x1234, %edx, %dx
+ lwpins $0x1234, %ebx, %bx
+ lwpins $0x1234, %esp, %sp
+ lwpins $0x1234, %ebp, %bp
+ lwpins $0x1234, %esi, %si
+ lwpins $0x1234, %edi, %di
+ lwpins $0x12345678, %edi, %eax
+ lwpins $0x12345678, %esi, %ecx
+ lwpins $0x12345678, %ebp, %edx
+ lwpins $0x12345678, %esp, %ebx
+ lwpins $0x12345678, %ebx, %esp
+ lwpins $0x12345678, %edx, %ebp
+ lwpins $0x12345678, %ecx, %esi
+ lwpins $0x12345678, %eax, %edi
+ lwpins $0x12345678, %eax, %rax
+ lwpins $0x12345678, %ecx, %rcx
+ lwpins $0x12345678, %edx, %rdx
+ lwpins $0x12345678, %ebx, %rbx
+ lwpins $0x12345678, %esp, %rsp
+ lwpins $0x12345678, %ebp, %rbp
+ lwpins $0x12345678, %esi, %rsi
+ lwpins $0x12345678, %edi, %rdi
+
+ lwpval $0x1234, %eax, %ax
+ lwpval $0x1234, %ecx, %cx
+ lwpval $0x1234, %edx, %dx
+ lwpval $0x1234, %ebx, %bx
+ lwpval $0x1234, %esp, %sp
+ lwpval $0x1234, %ebp, %bp
+ lwpval $0x1234, %esi, %si
+ lwpval $0x1234, %edi, %di
+ lwpval $0x12345678, %edi, %eax
+ lwpval $0x12345678, %esi, %ecx
+ lwpval $0x12345678, %ebp, %edx
+ lwpval $0x12345678, %esp, %ebx
+ lwpval $0x12345678, %ebx, %esp
+ lwpval $0x12345678, %edx, %ebp
+ lwpval $0x12345678, %ecx, %esi
+ lwpval $0x12345678, %eax, %edi
+ lwpval $0x12345678, %eax, %rax
+ lwpval $0x12345678, %ecx, %rcx
+ lwpval $0x12345678, %edx, %rdx
+ lwpval $0x12345678, %ebx, %rbx
+ lwpval $0x12345678, %esp, %rsp
+ lwpval $0x12345678, %ebp, %rbp
+ lwpval $0x12345678, %esi, %rsi
+ lwpval $0x12345678, %edi, %rdi
+
+ lwpins $0x1234, (%eax), %ax
+ lwpins $0x1234, (%ecx), %cx
+ lwpins $0x1234, (%edx), %dx
+ lwpins $0x1234, (%ebx), %bx
+ lwpins $0x1234, (%esp), %sp
+ lwpins $0x1234, (%ebp), %bp
+ lwpins $0x1234, (%esi), %si
+ lwpins $0x1234, (%edi), %di
+ lwpins $0x12345678, (%edi), %eax
+ lwpins $0x12345678, (%esi), %ecx
+ lwpins $0x12345678, (%ebp), %edx
+ lwpins $0x12345678, (%esp), %ebx
+ lwpins $0x12345678, (%ebx), %esp
+ lwpins $0x12345678, (%edx), %ebp
+ lwpins $0x12345678, (%ecx), %esi
+ lwpins $0x12345678, (%eax), %edi
+ lwpins $0x12345678, (%eax), %rax
+ lwpins $0x12345678, (%ecx), %rcx
+ lwpins $0x12345678, (%edx), %rdx
+ lwpins $0x12345678, (%ebx), %rbx
+ lwpins $0x12345678, (%esp), %rsp
+ lwpins $0x12345678, (%ebp), %rbp
+ lwpins $0x12345678, (%esi), %rsi
+ lwpins $0x12345678, (%edi), %rdi
+
+ lwpval $0x1234, (%eax), %ax
+ lwpval $0x1234, (%ecx), %cx
+ lwpval $0x1234, (%edx), %dx
+ lwpval $0x1234, (%ebx), %bx
+ lwpval $0x1234, (%esp), %sp
+ lwpval $0x1234, (%ebp), %bp
+ lwpval $0x1234, (%esi), %si
+ lwpval $0x1234, (%edi), %di
+ lwpval $0x12345678, (%edi), %eax
+ lwpval $0x12345678, (%esi), %ecx
+ lwpval $0x12345678, (%ebp), %edx
+ lwpval $0x12345678, (%esp), %ebx
+ lwpval $0x12345678, (%ebx), %esp
+ lwpval $0x12345678, (%edx), %ebp
+ lwpval $0x12345678, (%ecx), %esi
+ lwpval $0x12345678, (%eax), %edi
+ lwpval $0x12345678, (%eax), %rax
+ lwpval $0x12345678, (%ecx), %rcx
+ lwpval $0x12345678, (%edx), %rdx
+ lwpval $0x12345678, (%ebx), %rbx
+ lwpval $0x12345678, (%esp), %rsp
+ lwpval $0x12345678, (%ebp), %rbp
+ lwpval $0x12345678, (%esi), %rsi
+ lwpval $0x12345678, (%edi), %rdi
+
+ lwpins $0x1234, 0xcafe(%eax), %ax
+ lwpins $0x1234, 0xcafe(%ecx), %cx
+ lwpins $0x1234, 0xcafe(%edx), %dx
+ lwpins $0x1234, 0xcafe(%ebx), %bx
+ lwpins $0x1234, 0xcafe(%esp), %sp
+ lwpins $0x1234, 0xcafe(%ebp), %bp
+ lwpins $0x1234, 0xcafe(%esi), %si
+ lwpins $0x1234, 0xcafe(%edi), %di
+ lwpins $0x12345678, 0xcafe(%edi), %eax
+ lwpins $0x12345678, 0xcafe(%esi), %ecx
+ lwpins $0x12345678, 0xcafe(%ebp), %edx
+ lwpins $0x12345678, 0xcafe(%esp), %ebx
+ lwpins $0x12345678, 0xcafe(%ebx), %esp
+ lwpins $0x12345678, 0xcafe(%edx), %ebp
+ lwpins $0x12345678, 0xcafe(%ecx), %esi
+ lwpins $0x12345678, 0xcafe(%eax), %edi
+ lwpins $0x12345678, 0xcafe(%eax), %rax
+ lwpins $0x12345678, 0xcafe(%ecx), %rcx
+ lwpins $0x12345678, 0xcafe(%edx), %rdx
+ lwpins $0x12345678, 0xcafe(%ebx), %rbx
+ lwpins $0x12345678, 0xcafe(%esp), %rsp
+ lwpins $0x12345678, 0xcafe(%ebp), %rbp
+ lwpins $0x12345678, 0xcafe(%esi), %rsi
+ lwpins $0x12345678, 0xcafe(%edi), %rdi
+
+ lwpval $0x1234, 0xcafe(%eax), %ax
+ lwpval $0x1234, 0xcafe(%ecx), %cx
+ lwpval $0x1234, 0xcafe(%edx), %dx
+ lwpval $0x1234, 0xcafe(%ebx), %bx
+ lwpval $0x1234, 0xcafe(%esp), %sp
+ lwpval $0x1234, 0xcafe(%ebp), %bp
+ lwpval $0x1234, 0xcafe(%esi), %si
+ lwpval $0x1234, 0xcafe(%edi), %di
+ lwpval $0x12345678, 0xcafe(%edi), %eax
+ lwpval $0x12345678, 0xcafe(%esi), %ecx
+ lwpval $0x12345678, 0xcafe(%ebp), %edx
+ lwpval $0x12345678, 0xcafe(%esp), %ebx
+ lwpval $0x12345678, 0xcafe(%ebx), %esp
+ lwpval $0x12345678, 0xcafe(%edx), %ebp
+ lwpval $0x12345678, 0xcafe(%ecx), %esi
+ lwpval $0x12345678, 0xcafe(%eax), %edi
+ lwpval $0x12345678, 0xcafe(%eax), %rax
+ lwpval $0x12345678, 0xcafe(%ecx), %rcx
+ lwpval $0x12345678, 0xcafe(%edx), %rdx
+ lwpval $0x12345678, 0xcafe(%ebx), %rbx
+ lwpval $0x12345678, 0xcafe(%esp), %rsp
+ lwpval $0x12345678, 0xcafe(%ebp), %rbp
+ lwpval $0x12345678, 0xcafe(%esi), %rsi
+ lwpval $0x12345678, 0xcafe(%edi), %rdi
Index: opcodes/i386-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/i386-dis.c,v
retrieving revision 1.206
diff -u -d -d -u -p -r1.206 i386-dis.c
--- opcodes/i386-dis.c 29 Oct 2009 22:22:59 -0000 1.206
+++ opcodes/i386-dis.c 5 Nov 2009 22:44:36 -0000
@@ -114,6 +114,9 @@ static void REP_Fixup (int, int);
static void CMPXCHG8B_Fixup (int, int);
static void XMM_Fixup (int, int);
static void CRC32_Fixup (int, int);
+static void OP_LWPCB_E (int, int);
+static void OP_LWP_E (int, int);
+static void OP_LWP_I (int, int);
static void MOVBE_Fixup (int, int);
@@ -514,6 +517,7 @@ enum
USE_PREFIX_TABLE,
USE_X86_64_TABLE,
USE_3BYTE_TABLE,
+ USE_XOP_8F_TABLE,
USE_VEX_C4_TABLE,
USE_VEX_C5_TABLE,
USE_VEX_LEN_TABLE
@@ -528,6 +532,7 @@ enum
#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
+#define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
#define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
#define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
#define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
@@ -565,7 +570,9 @@ enum
REG_VEX_71,
REG_VEX_72,
REG_VEX_73,
- REG_VEX_AE
+ REG_VEX_AE,
+ REG_XOP_LWPCB,
+ REG_XOP_LWP
};
enum
@@ -1070,6 +1077,12 @@ enum
enum
{
+ XOP_09 = 0,
+ XOP_0A
+};
+
+enum
+{
VEX_0F = 0,
VEX_0F38,
VEX_0F3A
@@ -2123,7 +2136,7 @@ static const struct dis386 reg_table[][8
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "(bad)", { XX } },
+ { XOP_8F_TABLE (XOP_09) },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
},
@@ -2435,6 +2448,28 @@ static const struct dis386 reg_table[][8
{ "(bad)", { XX } },
{ "(bad)", { XX } },
},
+ /* REG_XOP_LWPCB */
+ {
+ { "llwpcb", { { OP_LWPCB_E, 0 } } },
+ { "slwpcb", { { OP_LWPCB_E, 0 } } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ },
+ /* REG_XOP_LWP */
+ {
+ { "lwpins", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
+ { "lwpval", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ },
};
static const struct dis386 prefix_table[][4] = {
@@ -6343,6 +6378,590 @@ static const struct dis386 three_byte_ta
},
};
+static const struct dis386 xop_table[][256] = {
+ /* XOP_09 */
+ {
+ /* 00 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 08 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 10 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { REG_TABLE (REG_XOP_LWPCB) },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 18 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 20 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 28 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 30 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 38 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 40 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 48 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 50 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 58 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 60 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 68 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 70 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 78 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 80 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 88 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 90 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 98 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* a0 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* a8 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* b0 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* b8 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* c0 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* c8 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* d0 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* d8 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* e0 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* e8 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* f0 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* f8 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ },
+ /* XOP_0A */
+ {
+ /* 00 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 08 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 10 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { REG_TABLE (REG_XOP_LWP) },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 18 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 20 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 28 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 30 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 38 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 40 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 48 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 50 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 58 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 60 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 68 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 70 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 78 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 80 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 88 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 90 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* 98 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* a0 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* a8 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* b0 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* b8 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* c0 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* c8 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* d0 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* d8 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* e0 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* e8 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* f0 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ /* f8 */
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ },
+};
static const struct dis386 vex_table[][256] = {
/* VEX_0F */
@@ -9315,6 +9934,65 @@ get_valid_dis386 (const struct dis386 *d
dp = &vex_len_table[dp->op[1].bytemode][index];
break;
+ case USE_XOP_8F_TABLE:
+ FETCH_DATA (info, codep + 3);
+ /* All bits in the REX prefix are ignored. */
+ rex_ignored = rex;
+ rex = ~(*codep >> 5) & 0x7;
+
+ /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
+ switch ((*codep & 0x1f))
+ {
+ default:
+ BadOp ();
+ case 0x9:
+ vex_table_index = XOP_09;
+ break;
+ case 0xa:
+ vex_table_index = XOP_0A;
+ break;
+ }
+ codep++;
+ vex.w = *codep & 0x80;
+ if (vex.w && address_mode == mode_64bit)
+ rex |= REX_W;
+
+ vex.register_specifier = (~(*codep >> 3)) & 0xf;
+ if (address_mode != mode_64bit
+ && vex.register_specifier > 0x7)
+ BadOp ();
+
+ vex.length = (*codep & 0x4) ? 256 : 128;
+ switch ((*codep & 0x3))
+ {
+ case 0:
+ vex.prefix = 0;
+ break;
+ case 1:
+ vex.prefix = DATA_PREFIX_OPCODE;
+ break;
+ case 2:
+ vex.prefix = REPE_PREFIX_OPCODE;
+ break;
+ case 3:
+ vex.prefix = REPNE_PREFIX_OPCODE;
+ break;
+ }
+ need_vex = 1;
+ need_vex_reg = 1;
+ codep++;
+ index = *codep++;
+ dp = &xop_table[vex_table_index][index];
+ /* There is no MODRM byte for VEX [82|77]. */
+ if (index != 0x77 && index != 0x82)
+ {
+ FETCH_DATA (info, codep + 1);
+ modrm.mod = (*codep >> 6) & 3;
+ modrm.reg = (*codep >> 3) & 7;
+ modrm.rm = *codep & 7;
+ }
+ break;
+
case USE_VEX_C4_TABLE:
FETCH_DATA (info, codep + 3);
/* All bits in the REX prefix are ignored. */
@@ -9325,13 +10003,13 @@ get_valid_dis386 (const struct dis386 *d
default:
BadOp ();
case 0x1:
- vex_table_index = 0;
+ vex_table_index = VEX_0F;
break;
case 0x2:
- vex_table_index = 1;
+ vex_table_index = VEX_0F38;
break;
case 0x3:
- vex_table_index = 2;
+ vex_table_index = VEX_0F3A;
break;
}
codep++;
@@ -12956,3 +13634,53 @@ MOVBE_Fixup (int bytemode, int sizeflag)
skip:
OP_M (bytemode, sizeflag);
}
+
+static void
+OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+ int reg;
+ const char **names;
+
+ /* Skip mod/rm byte. */
+ MODRM_CHECK;
+ codep++;
+
+ if (vex.w)
+ names = names64;
+ else if (vex.length == 256)
+ names = names32;
+ else
+ names = names16;
+
+ reg = modrm.rm;
+ USED_REX (REX_B);
+ if (rex & REX_B)
+ reg += 8;
+
+ oappend (names[reg]);
+}
+
+static void
+OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+ const char **names;
+
+ if (vex.w)
+ names = names64;
+ else if (vex.length == 256)
+ names = names32;
+ else
+ names = names16;
+
+ oappend (names[vex.register_specifier]);
+}
+
+static void
+OP_LWP_I (int bytemode ATTRIBUTE_UNUSED, int sizeflag)
+{
+ if (vex.w || vex.length == 256)
+ OP_I (q_mode, sizeflag);
+ else
+ OP_I (w_mode, sizeflag);
+}
+
Index: opcodes/i386-gen.c
===================================================================
RCS file: /cvs/src/src/opcodes/i386-gen.c,v
retrieving revision 1.53
diff -u -d -d -u -p -r1.53 i386-gen.c
--- opcodes/i386-gen.c 24 Sep 2009 16:37:09 -0000 1.53
+++ opcodes/i386-gen.c 5 Nov 2009 22:44:36 -0000
@@ -128,6 +128,8 @@ static initializer cpu_flag_init[] =
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA" },
{ "CPU_FMA4_FLAGS",
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA4" },
+ { "CPU_LWP_FLAGS",
+ "CpuLWP" },
{ "CPU_MOVBE_FLAGS",
"CpuMovbe" },
{ "CPU_RDTSCP_FLAGS",
@@ -295,7 +297,8 @@ static bitfield cpu_flags[] =
BITFIELD (CpuAES),
BITFIELD (CpuPCLMUL),
BITFIELD (CpuFMA),
- BITFIELD (CpuFMA4),
+ BITFIELD (CpuFMA4),
+ BITFIELD (CpuLWP),
BITFIELD (CpuLM),
BITFIELD (CpuMovbe),
BITFIELD (CpuEPT),
@@ -349,11 +352,14 @@ static bitfield opcode_modifiers[] =
BITFIELD (Vex),
BITFIELD (VexNDS),
BITFIELD (VexNDD),
+ BITFIELD (VexLWP),
BITFIELD (VexW0),
BITFIELD (VexW1),
BITFIELD (Vex0F),
BITFIELD (Vex0F38),
BITFIELD (Vex0F3A),
+ BITFIELD (XOP09),
+ BITFIELD (XOP0A),
BITFIELD (Vex3Sources),
BITFIELD (VexImmExt),
BITFIELD (SSE2AVX),
Index: opcodes/i386-opc.h
===================================================================
RCS file: /cvs/src/src/opcodes/i386-opc.h,v
retrieving revision 1.56
diff -u -d -d -u -p -r1.56 i386-opc.h
--- opcodes/i386-opc.h 16 Oct 2009 15:50:52 -0000 1.56
+++ opcodes/i386-opc.h 5 Nov 2009 22:44:36 -0000
@@ -102,6 +102,8 @@ enum
CpuFMA,
/* FMA4 support required */
CpuFMA4,
+ /* LWP support required */
+ CpuLWP,
/* MOVBE Instuction support required */
CpuMovbe,
/* EPT Instructions required */
@@ -168,6 +170,7 @@ typedef union i386_cpu_flags
unsigned int cpupclmul:1;
unsigned int cpufma:1;
unsigned int cpufma4:1;
+ unsigned int cpulwp:1;
unsigned int cpumovbe:1;
unsigned int cpuept:1;
unsigned int cpurdtscp:1;
@@ -273,6 +276,9 @@ enum
VexNDS,
/* insn has VEX NDD. Register destination is encoded in Vex prefix. */
VexNDD,
+ /* insn has VEX NDD. Register destination is encoded in Vex prefix
+ and one of the operands can access a memory location. */
+ VexLWP,
/* insn has VEX W0. */
VexW0,
/* insn has VEX W1. */
@@ -283,6 +289,10 @@ enum
Vex0F38,
/* insn has VEX 0x0F3A opcode prefix. */
Vex0F3A,
+ /* insn has XOP 0x09 opcode prefix. */
+ XOP09,
+ /* insn has XOP 0x0A opcode prefix. */
+ XOP0A,
/* insn has VEX prefix with 3 soures. */
Vex3Sources,
/* instruction has VEX 8 bit imm */
@@ -345,11 +355,14 @@ typedef struct i386_opcode_modifier
unsigned int vex:2;
unsigned int vexnds:1;
unsigned int vexndd:1;
+ unsigned int vexlwp:1;
unsigned int vexw0:1;
unsigned int vexw1:1;
unsigned int vex0f:1;
unsigned int vex0f38:1;
unsigned int vex0f3a:1;
+ unsigned int xop09:1;
+ unsigned int xop0a:1;
unsigned int vex3sources:1;
unsigned int veximmext:1;
unsigned int sse2avx:1;
Index: opcodes/i386-opc.tbl
===================================================================
RCS file: /cvs/src/src/opcodes/i386-opc.tbl,v
retrieving revision 1.66
diff -u -d -d -u -p -r1.66 i386-opc.tbl
--- opcodes/i386-opc.tbl 2 Oct 2009 19:03:40 -0000 1.66
+++ opcodes/i386-opc.tbl 5 Nov 2009 22:44:36 -0000
@@ -2548,6 +2548,21 @@ vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4,
vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
+// LWP instructions
+
+llwpcb, 1, 0x12, 0x0, 1, CpuLWP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Reg16 }
+llwpcb, 1, 0x12, 0x0, 1, CpuLWP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Reg32 }
+llwpcb, 1, 0x12, 0x0, 1, CpuLWP, Modrm|XOP09|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|Vex, { Reg64 }
+slwpcb, 1, 0x12, 0x1, 1, CpuLWP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Reg16 }
+slwpcb, 1, 0x12, 0x1, 1, CpuLWP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Reg32 }
+slwpcb, 1, 0x12, 0x1, 1, CpuLWP, Modrm|XOP09|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|Vex, { Reg64 }
+lwpval, 3, 0x12, 0x1, 1, CpuLWP, Modrm|XOP0A|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexLWP|Vex, { Imm16, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg16 }
+lwpval, 3, 0x12, 0x1, 1, CpuLWP, Modrm|XOP0A|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexLWP|Vex=2, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+lwpval, 3, 0x12, 0x1, 1, CpuLWP, Modrm|XOP0A|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexLWP|NoRex64|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|XOP0A|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexLWP|Vex, { Imm16, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg16 }
+lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|XOP0A|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexLWP|Vex=2, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|XOP0A|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexLWP|NoRex64|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+
// AMD 3DNow! instructions.
prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }