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Re: [PATCH] Add XOP support for upcoming AMD Orochi processor
Hi,
I was asked to remove for now the support for the CVT16 instructions
from binutils, and the attached patch does this.
2009-11-18 Sebastian Pop <sebastian.pop@amd.com>
gas/
* config/tc-i386.c (cpu_arch): Remove cvt16.
(md_show_usage): Same.
* doc/c-i386.texi: Same.
gas/testsuite/
* gas/i386/cvt16.d: Removed.
* gas/i386/cvt16.s: Removed.
* gas/i386/x86-64-cvt16.d: Removed.
* gas/i386/x86-64-cvt16.s: Removed.
* gas/i386/i386.exp: Remove cvt16 and x86-64-cvt16 tests.
opcodes/
* i386-dis.c (VEX_LEN_XOP_08_A0): Removed.
(VEX_LEN_XOP_08_A1): Removed.
(xop_table): Remove entries for VEX_LEN_XOP_08_A0 and
VEX_LEN_XOP_08_A1.
(vex_len_table): Same.
* i386-gen.c (CPU_CVT16_FLAGS): Removed.
(cpu_flags): Remove field for CpuCVT16.
* i386-opc.h (CpuCVT16): Removed.
(i386_cpu_flags): Remove bitfield cpucvt16.
(i386-opc.tbl): Remove CVT16 instructions.
Tested on x86-64-linux with make -k check.
Ok to commit?
Thanks,
Sebastian Pop
--
AMD / Open Source Compiler Engineering / GNU Tools
2009-11-18 Sebastian Pop <sebastian.pop@amd.com>
gas/
* config/tc-i386.c (cpu_arch): Remove cvt16.
(md_show_usage): Same.
* doc/c-i386.texi: Same.
gas/testsuite/
* gas/i386/cvt16.d: Removed.
* gas/i386/cvt16.s: Removed.
* gas/i386/x86-64-cvt16.d: Removed.
* gas/i386/x86-64-cvt16.s: Removed.
* gas/i386/i386.exp: Remove cvt16 and x86-64-cvt16 tests.
opcodes/
* i386-dis.c (VEX_LEN_XOP_08_A0): Removed.
(VEX_LEN_XOP_08_A1): Removed.
(xop_table): Remove entries for VEX_LEN_XOP_08_A0 and
VEX_LEN_XOP_08_A1.
(vex_len_table): Same.
* i386-gen.c (CPU_CVT16_FLAGS): Removed.
(cpu_flags): Remove field for CpuCVT16.
* i386-opc.h (CpuCVT16): Removed.
(i386_cpu_flags): Remove bitfield cpucvt16.
(i386-opc.tbl): Remove CVT16 instructions.
Index: gas/config/tc-i386.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-i386.c,v
retrieving revision 1.408
diff -u -d -d -u -p -r1.408 tc-i386.c
--- gas/config/tc-i386.c 18 Nov 2009 04:04:16 -0000 1.408
+++ gas/config/tc-i386.c 18 Nov 2009 19:55:10 -0000
@@ -644,8 +644,6 @@ static const arch_entry cpu_arch[] =
CPU_FMA4_FLAGS },
{ ".xop", PROCESSOR_UNKNOWN,
CPU_XOP_FLAGS },
- { ".cvt16", PROCESSOR_UNKNOWN,
- CPU_CVT16_FLAGS },
{ ".lwp", PROCESSOR_UNKNOWN,
CPU_LWP_FLAGS },
{ ".movbe", PROCESSOR_UNKNOWN,
@@ -8127,7 +8125,7 @@ md_show_usage (stream)
ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
- svme, abm, padlock, fma4, xop, cvt16, lwp\n"));
+ svme, abm, padlock, fma4, xop, lwp\n"));
fprintf (stream, _("\
-mtune=CPU optimize for CPU, CPU is one of:\n\
i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
Index: gas/doc/c-i386.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-i386.texi,v
retrieving revision 1.44
diff -u -d -d -u -p -r1.44 c-i386.texi
--- gas/doc/c-i386.texi 18 Nov 2009 04:04:16 -0000 1.44
+++ gas/doc/c-i386.texi 18 Nov 2009 19:55:10 -0000
@@ -144,7 +144,6 @@ accept various extension mnemonics. For
@code{lwp},
@code{fma4},
@code{xop},
-@code{cvt16},
@code{syscall},
@code{rdtscp},
@code{3dnow},
@@ -925,7 +924,7 @@ supported on the CPU specified. The cho
@item @samp{.ept} @tab @samp{.clflush}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
-@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cvt16}
+@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop}
@item @samp{.padlock}
@end multitable
Index: gas/testsuite/gas/i386/cvt16.d
===================================================================
RCS file: gas/testsuite/gas/i386/cvt16.d
diff -N gas/testsuite/gas/i386/cvt16.d
--- gas/testsuite/gas/i386/cvt16.d 18 Nov 2009 04:04:17 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,73 +0,0 @@
-#objdump: -dw
-#name: i386 CVT16
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+: 8f e8 78 a0 ff 00[ ]+vcvtph2ps \$0x0,%xmm7,%xmm7
-[ ]*[a-f0-9]+: 8f e8 78 a0 3b 00[ ]+vcvtph2ps \$0x0,\(%ebx\),%xmm7
-[ ]*[a-f0-9]+: 8f e8 78 a0 e8 00[ ]+vcvtph2ps \$0x0,%xmm0,%xmm5
-[ ]*[a-f0-9]+: 8f e8 78 a0 c5 ff[ ]+vcvtph2ps \$0xff,%xmm5,%xmm0
-[ ]*[a-f0-9]+: 8f e8 78 a0 c0 03[ ]+vcvtph2ps \$0x3,%xmm0,%xmm0
-[ ]*[a-f0-9]+: 8f e8 78 a0 c7 03[ ]+vcvtph2ps \$0x3,%xmm7,%xmm0
-[ ]*[a-f0-9]+: 8f e8 78 a0 ed 00[ ]+vcvtph2ps \$0x0,%xmm5,%xmm5
-[ ]*[a-f0-9]+: 8f e8 78 a0 f8 00[ ]+vcvtph2ps \$0x0,%xmm0,%xmm7
-[ ]*[a-f0-9]+: 8f e8 78 a0 00 03[ ]+vcvtph2ps \$0x3,\(%eax\),%xmm0
-[ ]*[a-f0-9]+: 8f e8 78 a0 03 ff[ ]+vcvtph2ps \$0xff,\(%ebx\),%xmm0
-[ ]*[a-f0-9]+: 8f e8 78 a0 38 00[ ]+vcvtph2ps \$0x0,\(%eax\),%xmm7
-[ ]*[a-f0-9]+: 8f e8 78 a0 ff ff[ ]+vcvtph2ps \$0xff,%xmm7,%xmm7
-[ ]*[a-f0-9]+: 8f e8 78 a0 ed ff[ ]+vcvtph2ps \$0xff,%xmm5,%xmm5
-[ ]*[a-f0-9]+: 8f e8 78 a0 2b ff[ ]+vcvtph2ps \$0xff,\(%ebx\),%xmm5
-[ ]*[a-f0-9]+: 8f e8 78 a0 c7 ff[ ]+vcvtph2ps \$0xff,%xmm7,%xmm0
-[ ]*[a-f0-9]+: 8f e8 78 a0 38 03[ ]+vcvtph2ps \$0x3,\(%eax\),%xmm7
-[ ]*[a-f0-9]+: 8f e8 7c a0 ff 00[ ]+vcvtph2ps \$0x0,%xmm7,%ymm7
-[ ]*[a-f0-9]+: 8f e8 7c a0 3b 00[ ]+vcvtph2ps \$0x0,\(%ebx\),%ymm7
-[ ]*[a-f0-9]+: 8f e8 7c a0 e8 00[ ]+vcvtph2ps \$0x0,%xmm0,%ymm5
-[ ]*[a-f0-9]+: 8f e8 7c a0 c5 ff[ ]+vcvtph2ps \$0xff,%xmm5,%ymm0
-[ ]*[a-f0-9]+: 8f e8 7c a0 c0 03[ ]+vcvtph2ps \$0x3,%xmm0,%ymm0
-[ ]*[a-f0-9]+: 8f e8 7c a0 c7 03[ ]+vcvtph2ps \$0x3,%xmm7,%ymm0
-[ ]*[a-f0-9]+: 8f e8 7c a0 ed 00[ ]+vcvtph2ps \$0x0,%xmm5,%ymm5
-[ ]*[a-f0-9]+: 8f e8 7c a0 f8 00[ ]+vcvtph2ps \$0x0,%xmm0,%ymm7
-[ ]*[a-f0-9]+: 8f e8 7c a0 00 03[ ]+vcvtph2ps \$0x3,\(%eax\),%ymm0
-[ ]*[a-f0-9]+: 8f e8 7c a0 03 ff[ ]+vcvtph2ps \$0xff,\(%ebx\),%ymm0
-[ ]*[a-f0-9]+: 8f e8 7c a0 38 00[ ]+vcvtph2ps \$0x0,\(%eax\),%ymm7
-[ ]*[a-f0-9]+: 8f e8 7c a0 ff ff[ ]+vcvtph2ps \$0xff,%xmm7,%ymm7
-[ ]*[a-f0-9]+: 8f e8 7c a0 ed ff[ ]+vcvtph2ps \$0xff,%xmm5,%ymm5
-[ ]*[a-f0-9]+: 8f e8 7c a0 2b ff[ ]+vcvtph2ps \$0xff,\(%ebx\),%ymm5
-[ ]*[a-f0-9]+: 8f e8 7c a0 c7 ff[ ]+vcvtph2ps \$0xff,%xmm7,%ymm0
-[ ]*[a-f0-9]+: 8f e8 7c a0 38 03[ ]+vcvtph2ps \$0x3,\(%eax\),%ymm7
-[ ]*[a-f0-9]+: 8f e8 78 a1 2b 00[ ]+vcvtps2ph \$0x0,%xmm5,\(%ebx\)
-[ ]*[a-f0-9]+: 8f e8 78 a1 3e 00[ ]+vcvtps2ph \$0x0,%xmm7,\(%esi\)
-[ ]*[a-f0-9]+: 8f e8 78 a1 00 00[ ]+vcvtps2ph \$0x0,%xmm0,\(%eax\)
-[ ]*[a-f0-9]+: 8f e8 78 a1 ea ff[ ]+vcvtps2ph \$0xff,%xmm5,%xmm2
-[ ]*[a-f0-9]+: 8f e8 78 a1 c2 03[ ]+vcvtps2ph \$0x3,%xmm0,%xmm2
-[ ]*[a-f0-9]+: 8f e8 78 a1 ea 03[ ]+vcvtps2ph \$0x3,%xmm5,%xmm2
-[ ]*[a-f0-9]+: 8f e8 78 a1 c7 00[ ]+vcvtps2ph \$0x0,%xmm0,%xmm7
-[ ]*[a-f0-9]+: 8f e8 78 a1 06 00[ ]+vcvtps2ph \$0x0,%xmm0,\(%esi\)
-[ ]*[a-f0-9]+: 8f e8 78 a1 f8 ff[ ]+vcvtps2ph \$0xff,%xmm7,%xmm0
-[ ]*[a-f0-9]+: 8f e8 78 a1 3b 00[ ]+vcvtps2ph \$0x0,%xmm7,\(%ebx\)
-[ ]*[a-f0-9]+: 8f e8 78 a1 2b ff[ ]+vcvtps2ph \$0xff,%xmm5,\(%ebx\)
-[ ]*[a-f0-9]+: 8f e8 78 a1 00 ff[ ]+vcvtps2ph \$0xff,%xmm0,\(%eax\)
-[ ]*[a-f0-9]+: 8f e8 78 a1 38 ff[ ]+vcvtps2ph \$0xff,%xmm7,\(%eax\)
-[ ]*[a-f0-9]+: 8f e8 78 a1 3b 03[ ]+vcvtps2ph \$0x3,%xmm7,\(%ebx\)
-[ ]*[a-f0-9]+: 8f e8 78 a1 28 03[ ]+vcvtps2ph \$0x3,%xmm5,\(%eax\)
-[ ]*[a-f0-9]+: 8f e8 78 a1 ef ff[ ]+vcvtps2ph \$0xff,%xmm5,%xmm7
-[ ]*[a-f0-9]+: 8f e8 7c a1 2b 00[ ]+vcvtps2ph \$0x0,%ymm5,\(%ebx\)
-[ ]*[a-f0-9]+: 8f e8 7c a1 3e 00[ ]+vcvtps2ph \$0x0,%ymm7,\(%esi\)
-[ ]*[a-f0-9]+: 8f e8 7c a1 00 00[ ]+vcvtps2ph \$0x0,%ymm0,\(%eax\)
-[ ]*[a-f0-9]+: 8f e8 7c a1 ea ff[ ]+vcvtps2ph \$0xff,%ymm5,%xmm2
-[ ]*[a-f0-9]+: 8f e8 7c a1 c2 03[ ]+vcvtps2ph \$0x3,%ymm0,%xmm2
-[ ]*[a-f0-9]+: 8f e8 7c a1 ea 03[ ]+vcvtps2ph \$0x3,%ymm5,%xmm2
-[ ]*[a-f0-9]+: 8f e8 7c a1 c7 00[ ]+vcvtps2ph \$0x0,%ymm0,%xmm7
-[ ]*[a-f0-9]+: 8f e8 7c a1 06 00[ ]+vcvtps2ph \$0x0,%ymm0,\(%esi\)
-[ ]*[a-f0-9]+: 8f e8 7c a1 f8 ff[ ]+vcvtps2ph \$0xff,%ymm7,%xmm0
-[ ]*[a-f0-9]+: 8f e8 7c a1 3b 00[ ]+vcvtps2ph \$0x0,%ymm7,\(%ebx\)
-[ ]*[a-f0-9]+: 8f e8 7c a1 2b ff[ ]+vcvtps2ph \$0xff,%ymm5,\(%ebx\)
-[ ]*[a-f0-9]+: 8f e8 7c a1 00 ff[ ]+vcvtps2ph \$0xff,%ymm0,\(%eax\)
-[ ]*[a-f0-9]+: 8f e8 7c a1 38 ff[ ]+vcvtps2ph \$0xff,%ymm7,\(%eax\)
-[ ]*[a-f0-9]+: 8f e8 7c a1 3b 03[ ]+vcvtps2ph \$0x3,%ymm7,\(%ebx\)
-[ ]*[a-f0-9]+: 8f e8 7c a1 28 03[ ]+vcvtps2ph \$0x3,%ymm5,\(%eax\)
-[ ]*[a-f0-9]+: 8f e8 7c a1 ef ff[ ]+vcvtps2ph \$0xff,%ymm5,%xmm7
-#pass
Index: gas/testsuite/gas/i386/cvt16.s
===================================================================
RCS file: gas/testsuite/gas/i386/cvt16.s
diff -N gas/testsuite/gas/i386/cvt16.s
--- gas/testsuite/gas/i386/cvt16.s 18 Nov 2009 04:04:17 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,74 +0,0 @@
-# Check CVT16 instructions (maxcombos=16, maxops=3, archbits=32, seed=1)
-
- .allow_index_reg
- .text
-_start:
-
-# Tests for op VCVTPH2PS imm8, xmm2/mem64, xmm1 (at&t syntax)
- VCVTPH2PS $0x0,%xmm7,%xmm7
- VCVTPH2PS $0x0,(%ebx),%xmm7
- VCVTPH2PS $0x0,%xmm0,%xmm5
- VCVTPH2PS $0xFF,%xmm5,%xmm0
- VCVTPH2PS $0x3,%xmm0,%xmm0
- VCVTPH2PS $0x3,%xmm7,%xmm0
- VCVTPH2PS $0x0,%xmm5,%xmm5
- VCVTPH2PS $0x0,%xmm0,%xmm7
- VCVTPH2PS $0x3,(%eax),%xmm0
- VCVTPH2PS $0xFF,(%ebx),%xmm0
- VCVTPH2PS $0x0,(%eax),%xmm7
- VCVTPH2PS $0xFF,%xmm7,%xmm7
- VCVTPH2PS $0xFF,%xmm5,%xmm5
- VCVTPH2PS $0xFF,(%ebx),%xmm5
- VCVTPH2PS $0xFF,%xmm7,%xmm0
- VCVTPH2PS $0x3,(%eax),%xmm7
-# Tests for op VCVTPH2PS imm8, xmm2/mem128, ymm1 (at&t syntax)
- VCVTPH2PS $0x0,%xmm7,%ymm7
- VCVTPH2PS $0x0,(%ebx),%ymm7
- VCVTPH2PS $0x0,%xmm0,%ymm5
- VCVTPH2PS $0xFF,%xmm5,%ymm0
- VCVTPH2PS $0x3,%xmm0,%ymm0
- VCVTPH2PS $0x3,%xmm7,%ymm0
- VCVTPH2PS $0x0,%xmm5,%ymm5
- VCVTPH2PS $0x0,%xmm0,%ymm7
- VCVTPH2PS $0x3,(%eax),%ymm0
- VCVTPH2PS $0xFF,(%ebx),%ymm0
- VCVTPH2PS $0x0,(%eax),%ymm7
- VCVTPH2PS $0xFF,%xmm7,%ymm7
- VCVTPH2PS $0xFF,%xmm5,%ymm5
- VCVTPH2PS $0xFF,(%ebx),%ymm5
- VCVTPH2PS $0xFF,%xmm7,%ymm0
- VCVTPH2PS $0x3,(%eax),%ymm7
-# Tests for op VCVTPS2PH imm8, xmm2, xmm1/mem64 (at&t syntax)
- VCVTPS2PH $0x0,%xmm5,(%ebx)
- VCVTPS2PH $0x0,%xmm7,(%esi)
- VCVTPS2PH $0x0,%xmm0,(%eax)
- VCVTPS2PH $0xFF,%xmm5,%xmm2
- VCVTPS2PH $0x3,%xmm0,%xmm2
- VCVTPS2PH $0x3,%xmm5,%xmm2
- VCVTPS2PH $0x0,%xmm0,%xmm7
- VCVTPS2PH $0x0,%xmm0,(%esi)
- VCVTPS2PH $0xFF,%xmm7,%xmm0
- VCVTPS2PH $0x0,%xmm7,(%ebx)
- VCVTPS2PH $0xFF,%xmm5,(%ebx)
- VCVTPS2PH $0xFF,%xmm0,(%eax)
- VCVTPS2PH $0xFF,%xmm7,(%eax)
- VCVTPS2PH $0x3,%xmm7,(%ebx)
- VCVTPS2PH $0x3,%xmm5,(%eax)
- VCVTPS2PH $0xFF,%xmm5,%xmm7
-# Tests for op VCVTPS2PH imm8, ymm2, xmm1/mem128 (at&t syntax)
- VCVTPS2PH $0x0,%ymm5,(%ebx)
- VCVTPS2PH $0x0,%ymm7,(%esi)
- VCVTPS2PH $0x0,%ymm0,(%eax)
- VCVTPS2PH $0xFF,%ymm5,%xmm2
- VCVTPS2PH $0x3,%ymm0,%xmm2
- VCVTPS2PH $0x3,%ymm5,%xmm2
- VCVTPS2PH $0x0,%ymm0,%xmm7
- VCVTPS2PH $0x0,%ymm0,(%esi)
- VCVTPS2PH $0xFF,%ymm7,%xmm0
- VCVTPS2PH $0x0,%ymm7,(%ebx)
- VCVTPS2PH $0xFF,%ymm5,(%ebx)
- VCVTPS2PH $0xFF,%ymm0,(%eax)
- VCVTPS2PH $0xFF,%ymm7,(%eax)
- VCVTPS2PH $0x3,%ymm7,(%ebx)
- VCVTPS2PH $0x3,%ymm5,(%eax)
- VCVTPS2PH $0xFF,%ymm5,%xmm7
Index: gas/testsuite/gas/i386/i386.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/i386/i386.exp,v
retrieving revision 1.128
diff -u -d -d -u -p -r1.128 i386.exp
--- gas/testsuite/gas/i386/i386.exp 18 Nov 2009 04:04:17 -0000 1.128
+++ gas/testsuite/gas/i386/i386.exp 18 Nov 2009 19:55:12 -0000
@@ -163,7 +163,6 @@ if [expr ([istarget "i*86-*-*"] || [ist
run_dump_test "fma4"
run_dump_test "lwp"
run_dump_test "xop"
- run_dump_test "cvt16"
# These tests require support for 8 and 16 bit relocs,
# so we only run them for ELF and COFF targets.
@@ -339,7 +338,6 @@ if [expr ([istarget "i*86-*-*"] || [ista
run_dump_test "x86-64-fma4"
run_dump_test "x86-64-lwp"
run_dump_test "x86-64-xop"
- run_dump_test "x86-64-cvt16"
if { ![istarget "*-*-aix*"]
&& ![istarget "*-*-beos*"]
Index: gas/testsuite/gas/i386/x86-64-cvt16.d
===================================================================
RCS file: gas/testsuite/gas/i386/x86-64-cvt16.d
diff -N gas/testsuite/gas/i386/x86-64-cvt16.d
--- gas/testsuite/gas/i386/x86-64-cvt16.d 18 Nov 2009 04:04:17 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,73 +0,0 @@
-#objdump: -dw
-#name: x86-64 CVT16
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+: 8f 48 78 a0 ff 00[ ]+vcvtph2ps \$0x0,%xmm15,%xmm15
-[ ]*[a-f0-9]+: 8f 68 78 a0 3e 00[ ]+vcvtph2ps \$0x0,\(%rsi\),%xmm15
-[ ]*[a-f0-9]+: 8f 68 78 a0 d8 00[ ]+vcvtph2ps \$0x0,%xmm0,%xmm11
-[ ]*[a-f0-9]+: 8f c8 78 a0 c7 ff[ ]+vcvtph2ps \$0xff,%xmm15,%xmm0
-[ ]*[a-f0-9]+: 8f e8 78 a0 c0 03[ ]+vcvtph2ps \$0x3,%xmm0,%xmm0
-[ ]*[a-f0-9]+: 8f c8 78 a0 c7 03[ ]+vcvtph2ps \$0x3,%xmm15,%xmm0
-[ ]*[a-f0-9]+: 8f 48 78 a0 db 00[ ]+vcvtph2ps \$0x0,%xmm11,%xmm11
-[ ]*[a-f0-9]+: 8f 68 78 a0 f8 00[ ]+vcvtph2ps \$0x0,%xmm0,%xmm15
-[ ]*[a-f0-9]+: 8f e8 78 a0 01 03[ ]+vcvtph2ps \$0x3,\(%rcx\),%xmm0
-[ ]*[a-f0-9]+: 8f e8 78 a0 06 ff[ ]+vcvtph2ps \$0xff,\(%rsi\),%xmm0
-[ ]*[a-f0-9]+: 8f 68 78 a0 3f 00[ ]+vcvtph2ps \$0x0,\(%rdi\),%xmm15
-[ ]*[a-f0-9]+: 8f 48 78 a0 ff ff[ ]+vcvtph2ps \$0xff,%xmm15,%xmm15
-[ ]*[a-f0-9]+: 8f 48 78 a0 db ff[ ]+vcvtph2ps \$0xff,%xmm11,%xmm11
-[ ]*[a-f0-9]+: 8f 68 78 a0 1e ff[ ]+vcvtph2ps \$0xff,\(%rsi\),%xmm11
-[ ]*[a-f0-9]+: 8f 68 78 a0 3f 03[ ]+vcvtph2ps \$0x3,\(%rdi\),%xmm15
-[ ]*[a-f0-9]+: 8f 48 78 a0 df 03[ ]+vcvtph2ps \$0x3,%xmm15,%xmm11
-[ ]*[a-f0-9]+: 8f 48 7c a0 ff 00[ ]+vcvtph2ps \$0x0,%xmm15,%ymm15
-[ ]*[a-f0-9]+: 8f 68 7c a0 3e 00[ ]+vcvtph2ps \$0x0,\(%rsi\),%ymm15
-[ ]*[a-f0-9]+: 8f 68 7c a0 d8 00[ ]+vcvtph2ps \$0x0,%xmm0,%ymm11
-[ ]*[a-f0-9]+: 8f c8 7c a0 c7 ff[ ]+vcvtph2ps \$0xff,%xmm15,%ymm0
-[ ]*[a-f0-9]+: 8f e8 7c a0 c0 03[ ]+vcvtph2ps \$0x3,%xmm0,%ymm0
-[ ]*[a-f0-9]+: 8f c8 7c a0 c7 03[ ]+vcvtph2ps \$0x3,%xmm15,%ymm0
-[ ]*[a-f0-9]+: 8f 48 7c a0 db 00[ ]+vcvtph2ps \$0x0,%xmm11,%ymm11
-[ ]*[a-f0-9]+: 8f 68 7c a0 f8 00[ ]+vcvtph2ps \$0x0,%xmm0,%ymm15
-[ ]*[a-f0-9]+: 8f e8 7c a0 01 03[ ]+vcvtph2ps \$0x3,\(%rcx\),%ymm0
-[ ]*[a-f0-9]+: 8f e8 7c a0 06 ff[ ]+vcvtph2ps \$0xff,\(%rsi\),%ymm0
-[ ]*[a-f0-9]+: 8f 68 7c a0 3f 00[ ]+vcvtph2ps \$0x0,\(%rdi\),%ymm15
-[ ]*[a-f0-9]+: 8f 48 7c a0 ff ff[ ]+vcvtph2ps \$0xff,%xmm15,%ymm15
-[ ]*[a-f0-9]+: 8f 48 7c a0 db ff[ ]+vcvtph2ps \$0xff,%xmm11,%ymm11
-[ ]*[a-f0-9]+: 8f 68 7c a0 1e ff[ ]+vcvtph2ps \$0xff,\(%rsi\),%ymm11
-[ ]*[a-f0-9]+: 8f 68 7c a0 3f 03[ ]+vcvtph2ps \$0x3,\(%rdi\),%ymm15
-[ ]*[a-f0-9]+: 8f 48 7c a0 df 03[ ]+vcvtph2ps \$0x3,%xmm15,%ymm11
-[ ]*[a-f0-9]+: 8f 68 78 a1 18 00[ ]+vcvtps2ph \$0x0,%xmm11,\(%rax\)
-[ ]*[a-f0-9]+: 8f 68 78 a1 3f 00[ ]+vcvtps2ph \$0x0,%xmm15,\(%rdi\)
-[ ]*[a-f0-9]+: 8f c8 78 a1 04 24 00[ ]+vcvtps2ph \$0x0,%xmm0,\(%r12\)
-[ ]*[a-f0-9]+: 8f 48 78 a1 df ff[ ]+vcvtps2ph \$0xff,%xmm11,%xmm15
-[ ]*[a-f0-9]+: 8f c8 78 a1 c7 03[ ]+vcvtps2ph \$0x3,%xmm0,%xmm15
-[ ]*[a-f0-9]+: 8f 48 78 a1 df 03[ ]+vcvtps2ph \$0x3,%xmm11,%xmm15
-[ ]*[a-f0-9]+: 8f e8 78 a1 c4 00[ ]+vcvtps2ph \$0x0,%xmm0,%xmm4
-[ ]*[a-f0-9]+: 8f e8 78 a1 07 00[ ]+vcvtps2ph \$0x0,%xmm0,\(%rdi\)
-[ ]*[a-f0-9]+: 8f 68 78 a1 f8 ff[ ]+vcvtps2ph \$0xff,%xmm15,%xmm0
-[ ]*[a-f0-9]+: 8f 68 78 a1 38 00[ ]+vcvtps2ph \$0x0,%xmm15,\(%rax\)
-[ ]*[a-f0-9]+: 8f 68 78 a1 18 ff[ ]+vcvtps2ph \$0xff,%xmm11,\(%rax\)
-[ ]*[a-f0-9]+: 8f c8 78 a1 04 24 ff[ ]+vcvtps2ph \$0xff,%xmm0,\(%r12\)
-[ ]*[a-f0-9]+: 8f 48 78 a1 3c 24 ff[ ]+vcvtps2ph \$0xff,%xmm15,\(%r12\)
-[ ]*[a-f0-9]+: 8f 68 78 a1 38 03[ ]+vcvtps2ph \$0x3,%xmm15,\(%rax\)
-[ ]*[a-f0-9]+: 8f 48 78 a1 1c 24 03[ ]+vcvtps2ph \$0x3,%xmm11,\(%r12\)
-[ ]*[a-f0-9]+: 8f 68 78 a1 dc ff[ ]+vcvtps2ph \$0xff,%xmm11,%xmm4
-[ ]*[a-f0-9]+: 8f 68 7c a1 18 00[ ]+vcvtps2ph \$0x0,%ymm11,\(%rax\)
-[ ]*[a-f0-9]+: 8f 68 7c a1 3f 00[ ]+vcvtps2ph \$0x0,%ymm15,\(%rdi\)
-[ ]*[a-f0-9]+: 8f c8 7c a1 04 24 00[ ]+vcvtps2ph \$0x0,%ymm0,\(%r12\)
-[ ]*[a-f0-9]+: 8f 48 7c a1 df ff[ ]+vcvtps2ph \$0xff,%ymm11,%xmm15
-[ ]*[a-f0-9]+: 8f c8 7c a1 c7 03[ ]+vcvtps2ph \$0x3,%ymm0,%xmm15
-[ ]*[a-f0-9]+: 8f 48 7c a1 df 03[ ]+vcvtps2ph \$0x3,%ymm11,%xmm15
-[ ]*[a-f0-9]+: 8f e8 7c a1 c4 00[ ]+vcvtps2ph \$0x0,%ymm0,%xmm4
-[ ]*[a-f0-9]+: 8f e8 7c a1 07 00[ ]+vcvtps2ph \$0x0,%ymm0,\(%rdi\)
-[ ]*[a-f0-9]+: 8f 68 7c a1 f8 ff[ ]+vcvtps2ph \$0xff,%ymm15,%xmm0
-[ ]*[a-f0-9]+: 8f 68 7c a1 38 00[ ]+vcvtps2ph \$0x0,%ymm15,\(%rax\)
-[ ]*[a-f0-9]+: 8f 68 7c a1 18 ff[ ]+vcvtps2ph \$0xff,%ymm11,\(%rax\)
-[ ]*[a-f0-9]+: 8f c8 7c a1 04 24 ff[ ]+vcvtps2ph \$0xff,%ymm0,\(%r12\)
-[ ]*[a-f0-9]+: 8f 48 7c a1 3c 24 ff[ ]+vcvtps2ph \$0xff,%ymm15,\(%r12\)
-[ ]*[a-f0-9]+: 8f 68 7c a1 38 03[ ]+vcvtps2ph \$0x3,%ymm15,\(%rax\)
-[ ]*[a-f0-9]+: 8f 48 7c a1 1c 24 03[ ]+vcvtps2ph \$0x3,%ymm11,\(%r12\)
-[ ]*[a-f0-9]+: 8f 68 7c a1 dc ff[ ]+vcvtps2ph \$0xff,%ymm11,%xmm4
-#pass
Index: gas/testsuite/gas/i386/x86-64-cvt16.s
===================================================================
RCS file: gas/testsuite/gas/i386/x86-64-cvt16.s
diff -N gas/testsuite/gas/i386/x86-64-cvt16.s
--- gas/testsuite/gas/i386/x86-64-cvt16.s 18 Nov 2009 04:04:17 -0000 1.1
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,74 +0,0 @@
-# Check CVT16 instructions (maxcombos=16, maxops=3, archbits=64, seed=1)
-
- .allow_index_reg
- .text
-_start:
-
-# Tests for op VCVTPH2PS imm8, xmm2/mem64, xmm1 (at&t syntax)
- VCVTPH2PS $0x0,%xmm15,%xmm15
- VCVTPH2PS $0x0,(%rsi),%xmm15
- VCVTPH2PS $0x0,%xmm0,%xmm11
- VCVTPH2PS $0xFF,%xmm15,%xmm0
- VCVTPH2PS $0x3,%xmm0,%xmm0
- VCVTPH2PS $0x3,%xmm15,%xmm0
- VCVTPH2PS $0x0,%xmm11,%xmm11
- VCVTPH2PS $0x0,%xmm0,%xmm15
- VCVTPH2PS $0x3,(%rcx),%xmm0
- VCVTPH2PS $0xFF,(%rsi),%xmm0
- VCVTPH2PS $0x0,(%rdi),%xmm15
- VCVTPH2PS $0xFF,%xmm15,%xmm15
- VCVTPH2PS $0xFF,%xmm11,%xmm11
- VCVTPH2PS $0xFF,(%rsi),%xmm11
- VCVTPH2PS $0x3,(%rdi),%xmm15
- VCVTPH2PS $0x3,%xmm15,%xmm11
-# Tests for op VCVTPH2PS imm8, xmm2/mem128, ymm1 (at&t syntax)
- VCVTPH2PS $0x0,%xmm15,%ymm15
- VCVTPH2PS $0x0,(%rsi),%ymm15
- VCVTPH2PS $0x0,%xmm0,%ymm11
- VCVTPH2PS $0xFF,%xmm15,%ymm0
- VCVTPH2PS $0x3,%xmm0,%ymm0
- VCVTPH2PS $0x3,%xmm15,%ymm0
- VCVTPH2PS $0x0,%xmm11,%ymm11
- VCVTPH2PS $0x0,%xmm0,%ymm15
- VCVTPH2PS $0x3,(%rcx),%ymm0
- VCVTPH2PS $0xFF,(%rsi),%ymm0
- VCVTPH2PS $0x0,(%rdi),%ymm15
- VCVTPH2PS $0xFF,%xmm15,%ymm15
- VCVTPH2PS $0xFF,%xmm11,%ymm11
- VCVTPH2PS $0xFF,(%rsi),%ymm11
- VCVTPH2PS $0x3,(%rdi),%ymm15
- VCVTPH2PS $0x3,%xmm15,%ymm11
-# Tests for op VCVTPS2PH imm8, xmm2, xmm1/mem64 (at&t syntax)
- VCVTPS2PH $0x0,%xmm11,(%rax)
- VCVTPS2PH $0x0,%xmm15,(%rdi)
- VCVTPS2PH $0x0,%xmm0,(%r12)
- VCVTPS2PH $0xFF,%xmm11,%xmm15
- VCVTPS2PH $0x3,%xmm0,%xmm15
- VCVTPS2PH $0x3,%xmm11,%xmm15
- VCVTPS2PH $0x0,%xmm0,%xmm4
- VCVTPS2PH $0x0,%xmm0,(%rdi)
- VCVTPS2PH $0xFF,%xmm15,%xmm0
- VCVTPS2PH $0x0,%xmm15,(%rax)
- VCVTPS2PH $0xFF,%xmm11,(%rax)
- VCVTPS2PH $0xFF,%xmm0,(%r12)
- VCVTPS2PH $0xFF,%xmm15,(%r12)
- VCVTPS2PH $0x3,%xmm15,(%rax)
- VCVTPS2PH $0x3,%xmm11,(%r12)
- VCVTPS2PH $0xFF,%xmm11,%xmm4
-# Tests for op VCVTPS2PH imm8, ymm2, xmm1/mem128 (at&t syntax)
- VCVTPS2PH $0x0,%ymm11,(%rax)
- VCVTPS2PH $0x0,%ymm15,(%rdi)
- VCVTPS2PH $0x0,%ymm0,(%r12)
- VCVTPS2PH $0xFF,%ymm11,%xmm15
- VCVTPS2PH $0x3,%ymm0,%xmm15
- VCVTPS2PH $0x3,%ymm11,%xmm15
- VCVTPS2PH $0x0,%ymm0,%xmm4
- VCVTPS2PH $0x0,%ymm0,(%rdi)
- VCVTPS2PH $0xFF,%ymm15,%xmm0
- VCVTPS2PH $0x0,%ymm15,(%rax)
- VCVTPS2PH $0xFF,%ymm11,(%rax)
- VCVTPS2PH $0xFF,%ymm0,(%r12)
- VCVTPS2PH $0xFF,%ymm15,(%r12)
- VCVTPS2PH $0x3,%ymm15,(%rax)
- VCVTPS2PH $0x3,%ymm11,(%r12)
- VCVTPS2PH $0xFF,%ymm11,%xmm4
Index: opcodes/i386-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/i386-dis.c,v
retrieving revision 1.213
diff -u -d -d -u -p -r1.213 i386-dis.c
--- opcodes/i386-dis.c 18 Nov 2009 04:04:17 -0000 1.213
+++ opcodes/i386-dis.c 18 Nov 2009 19:55:15 -0000
@@ -1293,8 +1293,6 @@ enum
VEX_LEN_3A7E_P_2,
VEX_LEN_3A7F_P_2,
VEX_LEN_3ADF_P_2,
- VEX_LEN_XOP_08_A0,
- VEX_LEN_XOP_08_A1,
VEX_LEN_XOP_09_80,
VEX_LEN_XOP_09_81
};
@@ -6573,8 +6571,8 @@ static const struct dis386 xop_table[][2
{ "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
{ "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
/* a0 */
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_A0) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_A1) },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
{ "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
{ "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
{ "(bad)", { XX } },
@@ -9353,16 +9351,6 @@ static const struct dis386 vex_len_table
{ "vaeskeygenassist", { XM, EXx, Ib } },
{ "(bad)", { XX } },
},
- /* VEX_LEN_XOP_08_A0 */
- {
- { "vcvtph2ps", { XM, EXq, Ib } },
- { "vcvtph2ps", { XM, EXxmm, Ib } },
- },
- /* VEX_LEN_XOP_08_A1 */
- {
- { "vcvtps2ph", { EXq, XM, Ib } },
- { "vcvtps2ph", { EXxmm, XM, Ib } },
- },
/* VEX_LEN_XOP_09_80 */
{
{ "vfrczps", { XM, EXxmm } },
Index: opcodes/i386-gen.c
===================================================================
RCS file: /cvs/src/src/opcodes/i386-gen.c,v
retrieving revision 1.56
diff -u -d -d -u -p -r1.56 i386-gen.c
--- opcodes/i386-gen.c 18 Nov 2009 04:04:17 -0000 1.56
+++ opcodes/i386-gen.c 18 Nov 2009 19:55:15 -0000
@@ -129,9 +129,7 @@ static initializer cpu_flag_init[] =
{ "CPU_FMA4_FLAGS",
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA4" },
{ "CPU_XOP_FLAGS",
- "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuABM|CpuAVX|CpuFMA4|CpuXOP|CpuCVT16" },
- { "CPU_CVT16_FLAGS",
- "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuABM|CpuAVX|CpuFMA4|CpuXOP|CpuCVT16" },
+ "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuABM|CpuAVX|CpuFMA4|CpuXOP" },
{ "CPU_LWP_FLAGS",
"CpuLWP" },
{ "CPU_MOVBE_FLAGS",
@@ -303,7 +301,6 @@ static bitfield cpu_flags[] =
BITFIELD (CpuFMA),
BITFIELD (CpuFMA4),
BITFIELD (CpuXOP),
- BITFIELD (CpuCVT16),
BITFIELD (CpuLWP),
BITFIELD (CpuLM),
BITFIELD (CpuMovbe),
Index: opcodes/i386-opc.h
===================================================================
RCS file: /cvs/src/src/opcodes/i386-opc.h,v
retrieving revision 1.59
diff -u -d -d -u -p -r1.59 i386-opc.h
--- opcodes/i386-opc.h 18 Nov 2009 04:04:17 -0000 1.59
+++ opcodes/i386-opc.h 18 Nov 2009 19:55:15 -0000
@@ -104,8 +104,6 @@ enum
CpuFMA4,
/* XOP support required */
CpuXOP,
- /* CVT16 support required */
- CpuCVT16,
/* LWP support required */
CpuLWP,
/* MOVBE Instuction support required */
@@ -175,7 +173,6 @@ typedef union i386_cpu_flags
unsigned int cpufma:1;
unsigned int cpufma4:1;
unsigned int cpuxop:1;
- unsigned int cpucvt16:1;
unsigned int cpulwp:1;
unsigned int cpumovbe:1;
unsigned int cpuept:1;
Index: opcodes/i386-opc.tbl
===================================================================
RCS file: /cvs/src/src/opcodes/i386-opc.tbl,v
retrieving revision 1.70
diff -u -d -d -u -p -r1.70 i386-opc.tbl
--- opcodes/i386-opc.tbl 18 Nov 2009 04:04:17 -0000 1.70
+++ opcodes/i386-opc.tbl 18 Nov 2009 19:55:15 -0000
@@ -2548,13 +2548,6 @@ vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4,
vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
-// CVT16 instructions
-
-vcvtph2ps, 3, 0xa0, None, 1, CpuCVT16, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Qword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
-vcvtph2ps, 3, 0xa0, None, 1, CpuCVT16, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM }
-vcvtps2ph, 3, 0xa1, None, 1, CpuCVT16, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, RegXMM, Qword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex }
-vcvtps2ph, 3, 0xa1, None, 1, CpuCVT16, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Imm8, RegYMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex }
-
// XOP instructions
vfrczpd, 2, 0x81, None, 1, CpuXOP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }