This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
Microblaze wshadow fix.
- From: Nick Clifton <nickc at redhat dot com>
- To: binutils at sourceware dot org
- Date: Mon, 14 Dec 2009 09:49:34 +0000
- Subject: Microblaze wshadow fix.
Hi Guys,
I have just found another shadowed variable that I missed with my
original patch. This time in the microblaze port. Fixed with the
attached patch.
Cheers
Nick
gas/ChangeLog
2009-12-14 Nick Clifton <nickc@redhat.com>
* config/tc-microblaze.c (md_assemble): Rename 'imm' to 'immed' in
order to avoid shadowing global variable of the same name.
Index: gas/config/tc-microblaze.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-microblaze.c,v
retrieving revision 1.3
diff -c -3 -p -r1.3 tc-microblaze.c
*** gas/config/tc-microblaze.c 29 Aug 2009 22:10:59 -0000 1.3
--- gas/config/tc-microblaze.c 14 Dec 2009 09:47:38 -0000
*************** md_assemble (char * str)
*** 801,807 ****
unsigned reg2;
unsigned reg3;
unsigned isize;
! unsigned int imm, temp;
expressionS exp;
char name[20];
--- 801,807 ----
unsigned reg2;
unsigned reg3;
unsigned isize;
! unsigned int immed, temp;
expressionS exp;
char name[20];
*************** md_assemble (char * str)
*** 943,954 ****
exp.X_add_symbol,
exp.X_add_number,
opc);
! imm = 0;
}
else
{
output = frag_more (isize);
! imm = exp.X_add_number;
}
if (streq (name, "lmi") || streq (name, "smi"))
--- 943,954 ----
exp.X_add_symbol,
exp.X_add_number,
opc);
! immed = 0;
}
else
{
output = frag_more (isize);
! immed = exp.X_add_number;
}
if (streq (name, "lmi") || streq (name, "smi"))
*************** md_assemble (char * str)
*** 971,977 ****
inst = opcode->bit_sequence;
inst |= (reg1 << RD_LOW) & RD_MASK;
inst |= (reg2 << RA_LOW) & RA_MASK;
! inst |= (imm << IMM_LOW) & IMM_MASK;
for (i = 0; i < count - 1; i++)
{
--- 971,977 ----
inst = opcode->bit_sequence;
inst |= (reg1 << RD_LOW) & RD_MASK;
inst |= (reg2 << RA_LOW) & RA_MASK;
! inst |= (immed << IMM_LOW) & IMM_MASK;
for (i = 0; i < count - 1; i++)
{
*************** md_assemble (char * str)
*** 980,996 ****
output[2] = INST_BYTE2 (inst);
output[3] = INST_BYTE3 (inst);
output = frag_more (isize);
! imm = imm + 4;
reg1++;
inst = opcode->bit_sequence;
inst |= (reg1 << RD_LOW) & RD_MASK;
inst |= (reg2 << RA_LOW) & RA_MASK;
! inst |= (imm << IMM_LOW) & IMM_MASK;
}
}
else
{
! temp = imm & 0xFFFF8000;
if ((temp != 0) && (temp != 0xFFFF8000))
{
/* Needs an immediate inst. */
--- 980,996 ----
output[2] = INST_BYTE2 (inst);
output[3] = INST_BYTE3 (inst);
output = frag_more (isize);
! immed = immed + 4;
reg1++;
inst = opcode->bit_sequence;
inst |= (reg1 << RD_LOW) & RD_MASK;
inst |= (reg2 << RA_LOW) & RA_MASK;
! inst |= (immed << IMM_LOW) & IMM_MASK;
}
}
else
{
! temp = immed & 0xFFFF8000;
if ((temp != 0) && (temp != 0xFFFF8000))
{
/* Needs an immediate inst. */
*************** md_assemble (char * str)
*** 1002,1008 ****
}
inst1 = opcode1->bit_sequence;
! inst1 |= ((imm & 0xFFFF0000) >> 16) & IMM_MASK;
output[0] = INST_BYTE0 (inst1);
output[1] = INST_BYTE1 (inst1);
output[2] = INST_BYTE2 (inst1);
--- 1002,1008 ----
}
inst1 = opcode1->bit_sequence;
! inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
output[0] = INST_BYTE0 (inst1);
output[1] = INST_BYTE1 (inst1);
output[2] = INST_BYTE2 (inst1);
*************** md_assemble (char * str)
*** 1011,1017 ****
}
inst |= (reg1 << RD_LOW) & RD_MASK;
inst |= (reg2 << RA_LOW) & RA_MASK;
! inst |= (imm << IMM_LOW) & IMM_MASK;
}
break;
--- 1011,1017 ----
}
inst |= (reg1 << RD_LOW) & RD_MASK;
inst |= (reg2 << RA_LOW) & RA_MASK;
! inst |= (immed << IMM_LOW) & IMM_MASK;
}
break;
*************** md_assemble (char * str)
*** 1046,1062 ****
else
{
output = frag_more (isize);
! imm = exp.X_add_number;
}
! if (imm != (imm % 32))
{
as_warn (_("Shift value > 32. using <value %% 32>"));
! imm = imm % 32;
}
inst |= (reg1 << RD_LOW) & RD_MASK;
inst |= (reg2 << RA_LOW) & RA_MASK;
! inst |= (imm << IMM_LOW) & IMM5_MASK;
break;
case INST_TYPE_R1_R2:
--- 1046,1062 ----
else
{
output = frag_more (isize);
! immed = exp.X_add_number;
}
! if (immed != (immed % 32))
{
as_warn (_("Shift value > 32. using <value %% 32>"));
! immed = immed % 32;
}
inst |= (reg1 << RD_LOW) & RD_MASK;
inst |= (reg2 << RA_LOW) & RA_MASK;
! inst |= (immed << IMM_LOW) & IMM5_MASK;
break;
case INST_TYPE_R1_R2:
*************** md_assemble (char * str)
*** 1122,1132 ****
reg1 = 0;
}
if (strcmp (op_end, ""))
! op_end = parse_reg (op_end + 1, &imm); /* Get rfslN. */
else
{
as_fatal (_("Error in statement syntax"));
! imm = 0;
}
/* Check for spl registers. */
--- 1122,1132 ----
reg1 = 0;
}
if (strcmp (op_end, ""))
! op_end = parse_reg (op_end + 1, &immed); /* Get rfslN. */
else
{
as_fatal (_("Error in statement syntax"));
! immed = 0;
}
/* Check for spl registers. */
*************** md_assemble (char * str)
*** 1134,1140 ****
as_fatal (_("Cannot use special register with this instruction"));
inst |= (reg1 << RD_LOW) & RD_MASK;
! inst |= (imm << IMM_LOW) & RFSL_MASK;
output = frag_more (isize);
break;
--- 1134,1140 ----
as_fatal (_("Cannot use special register with this instruction"));
inst |= (reg1 << RD_LOW) & RD_MASK;
! inst |= (immed << IMM_LOW) & RFSL_MASK;
output = frag_more (isize);
break;
*************** md_assemble (char * str)
*** 1161,1170 ****
else
{
output = frag_more (isize);
! imm = exp.X_add_number;
}
inst |= (reg1 << RD_LOW) & RD_MASK;
! inst |= (imm << IMM_LOW) & IMM15_MASK;
break;
case INST_TYPE_R1_RFSL:
--- 1161,1170 ----
else
{
output = frag_more (isize);
! immed = exp.X_add_number;
}
inst |= (reg1 << RD_LOW) & RD_MASK;
! inst |= (immed << IMM_LOW) & IMM15_MASK;
break;
case INST_TYPE_R1_RFSL:
*************** md_assemble (char * str)
*** 1176,1186 ****
reg1 = 0;
}
if (strcmp (op_end, ""))
! op_end = parse_reg (op_end + 1, &imm); /* Get rfslN. */
else
{
as_fatal (_("Error in statement syntax"));
! imm = 0;
}
/* Check for spl registers. */
--- 1176,1186 ----
reg1 = 0;
}
if (strcmp (op_end, ""))
! op_end = parse_reg (op_end + 1, &immed); /* Get rfslN. */
else
{
as_fatal (_("Error in statement syntax"));
! immed = 0;
}
/* Check for spl registers. */
*************** md_assemble (char * str)
*** 1188,1209 ****
as_fatal (_("Cannot use special register with this instruction"));
inst |= (reg1 << RA_LOW) & RA_MASK;
! inst |= (imm << IMM_LOW) & RFSL_MASK;
output = frag_more (isize);
break;
case INST_TYPE_RFSL:
if (strcmp (op_end, ""))
! op_end = parse_reg (op_end + 1, &imm); /* Get rfslN. */
else
{
as_fatal (_("Error in statement syntax"));
! imm = 0;
}
/* Check for spl registers. */
if (check_spl_reg (®1))
as_fatal (_("Cannot use special register with this instruction"));
! inst |= (imm << IMM_LOW) & RFSL_MASK;
output = frag_more (isize);
break;
--- 1188,1209 ----
as_fatal (_("Cannot use special register with this instruction"));
inst |= (reg1 << RA_LOW) & RA_MASK;
! inst |= (immed << IMM_LOW) & RFSL_MASK;
output = frag_more (isize);
break;
case INST_TYPE_RFSL:
if (strcmp (op_end, ""))
! op_end = parse_reg (op_end + 1, &immed); /* Get rfslN. */
else
{
as_fatal (_("Error in statement syntax"));
! immed = 0;
}
/* Check for spl registers. */
if (check_spl_reg (®1))
as_fatal (_("Cannot use special register with this instruction"));
! inst |= (immed << IMM_LOW) & RFSL_MASK;
output = frag_more (isize);
break;
*************** md_assemble (char * str)
*** 1259,1293 ****
}
if (reg2 == REG_MSR)
! imm = opcode->immval_mask | REG_MSR_MASK;
else if (reg2 == REG_PC)
! imm = opcode->immval_mask | REG_PC_MASK;
else if (reg2 == REG_EAR)
! imm = opcode->immval_mask | REG_EAR_MASK;
else if (reg2 == REG_ESR)
! imm = opcode->immval_mask | REG_ESR_MASK;
else if (reg2 == REG_FSR)
! imm = opcode->immval_mask | REG_FSR_MASK;
else if (reg2 == REG_BTR)
! imm = opcode->immval_mask | REG_BTR_MASK;
else if (reg2 == REG_EDR)
! imm = opcode->immval_mask | REG_EDR_MASK;
else if (reg2 == REG_PID)
! imm = opcode->immval_mask | REG_PID_MASK;
else if (reg2 == REG_ZPR)
! imm = opcode->immval_mask | REG_ZPR_MASK;
else if (reg2 == REG_TLBX)
! imm = opcode->immval_mask | REG_TLBX_MASK;
else if (reg2 == REG_TLBLO)
! imm = opcode->immval_mask | REG_TLBLO_MASK;
else if (reg2 == REG_TLBHI)
! imm = opcode->immval_mask | REG_TLBHI_MASK;
else if (reg2 >= (REG_PVR+MIN_PVR_REGNUM) && reg2 <= (REG_PVR+MAX_PVR_REGNUM))
! imm = opcode->immval_mask | REG_PVR_MASK | reg2;
else
as_fatal (_("invalid value for special purpose register"));
inst |= (reg1 << RD_LOW) & RD_MASK;
! inst |= (imm << IMM_LOW) & IMM_MASK;
output = frag_more (isize);
break;
--- 1259,1293 ----
}
if (reg2 == REG_MSR)
! immed = opcode->immval_mask | REG_MSR_MASK;
else if (reg2 == REG_PC)
! immed = opcode->immval_mask | REG_PC_MASK;
else if (reg2 == REG_EAR)
! immed = opcode->immval_mask | REG_EAR_MASK;
else if (reg2 == REG_ESR)
! immed = opcode->immval_mask | REG_ESR_MASK;
else if (reg2 == REG_FSR)
! immed = opcode->immval_mask | REG_FSR_MASK;
else if (reg2 == REG_BTR)
! immed = opcode->immval_mask | REG_BTR_MASK;
else if (reg2 == REG_EDR)
! immed = opcode->immval_mask | REG_EDR_MASK;
else if (reg2 == REG_PID)
! immed = opcode->immval_mask | REG_PID_MASK;
else if (reg2 == REG_ZPR)
! immed = opcode->immval_mask | REG_ZPR_MASK;
else if (reg2 == REG_TLBX)
! immed = opcode->immval_mask | REG_TLBX_MASK;
else if (reg2 == REG_TLBLO)
! immed = opcode->immval_mask | REG_TLBLO_MASK;
else if (reg2 == REG_TLBHI)
! immed = opcode->immval_mask | REG_TLBHI_MASK;
else if (reg2 >= (REG_PVR+MIN_PVR_REGNUM) && reg2 <= (REG_PVR+MAX_PVR_REGNUM))
! immed = opcode->immval_mask | REG_PVR_MASK | reg2;
else
as_fatal (_("invalid value for special purpose register"));
inst |= (reg1 << RD_LOW) & RD_MASK;
! inst |= (immed << IMM_LOW) & IMM_MASK;
output = frag_more (isize);
break;
*************** md_assemble (char * str)
*** 1308,1342 ****
}
if (reg1 == REG_MSR)
! imm = opcode->immval_mask | REG_MSR_MASK;
else if (reg1 == REG_PC)
! imm = opcode->immval_mask | REG_PC_MASK;
else if (reg1 == REG_EAR)
! imm = opcode->immval_mask | REG_EAR_MASK;
else if (reg1 == REG_ESR)
! imm = opcode->immval_mask | REG_ESR_MASK;
else if (reg1 == REG_FSR)
! imm = opcode->immval_mask | REG_FSR_MASK;
else if (reg1 == REG_BTR)
! imm = opcode->immval_mask | REG_BTR_MASK;
else if (reg1 == REG_EDR)
! imm = opcode->immval_mask | REG_EDR_MASK;
else if (reg1 == REG_PID)
! imm = opcode->immval_mask | REG_PID_MASK;
else if (reg1 == REG_ZPR)
! imm = opcode->immval_mask | REG_ZPR_MASK;
else if (reg1 == REG_TLBX)
! imm = opcode->immval_mask | REG_TLBX_MASK;
else if (reg1 == REG_TLBLO)
! imm = opcode->immval_mask | REG_TLBLO_MASK;
else if (reg1 == REG_TLBHI)
! imm = opcode->immval_mask | REG_TLBHI_MASK;
else if (reg1 == REG_TLBSX)
! imm = opcode->immval_mask | REG_TLBSX_MASK;
else
as_fatal (_("invalid value for special purpose register"));
inst |= (reg2 << RA_LOW) & RA_MASK;
! inst |= (imm << IMM_LOW) & IMM_MASK;
output = frag_more (isize);
break;
--- 1308,1342 ----
}
if (reg1 == REG_MSR)
! immed = opcode->immval_mask | REG_MSR_MASK;
else if (reg1 == REG_PC)
! immed = opcode->immval_mask | REG_PC_MASK;
else if (reg1 == REG_EAR)
! immed = opcode->immval_mask | REG_EAR_MASK;
else if (reg1 == REG_ESR)
! immed = opcode->immval_mask | REG_ESR_MASK;
else if (reg1 == REG_FSR)
! immed = opcode->immval_mask | REG_FSR_MASK;
else if (reg1 == REG_BTR)
! immed = opcode->immval_mask | REG_BTR_MASK;
else if (reg1 == REG_EDR)
! immed = opcode->immval_mask | REG_EDR_MASK;
else if (reg1 == REG_PID)
! immed = opcode->immval_mask | REG_PID_MASK;
else if (reg1 == REG_ZPR)
! immed = opcode->immval_mask | REG_ZPR_MASK;
else if (reg1 == REG_TLBX)
! immed = opcode->immval_mask | REG_TLBX_MASK;
else if (reg1 == REG_TLBLO)
! immed = opcode->immval_mask | REG_TLBLO_MASK;
else if (reg1 == REG_TLBHI)
! immed = opcode->immval_mask | REG_TLBHI_MASK;
else if (reg1 == REG_TLBSX)
! immed = opcode->immval_mask | REG_TLBSX_MASK;
else
as_fatal (_("invalid value for special purpose register"));
inst |= (reg2 << RA_LOW) & RA_MASK;
! inst |= (immed << IMM_LOW) & IMM_MASK;
output = frag_more (isize);
break;
*************** md_assemble (char * str)
*** 1432,1446 ****
exp.X_add_symbol,
exp.X_add_number,
opc);
! imm = 0;
}
else
{
output = frag_more (isize);
! imm = exp.X_add_number;
}
! temp = imm & 0xFFFF8000;
if ((temp != 0) && (temp != 0xFFFF8000))
{
/* Needs an immediate inst. */
--- 1432,1446 ----
exp.X_add_symbol,
exp.X_add_number,
opc);
! immed = 0;
}
else
{
output = frag_more (isize);
! immed = exp.X_add_number;
}
! temp = immed & 0xFFFF8000;
if ((temp != 0) && (temp != 0xFFFF8000))
{
/* Needs an immediate inst. */
*************** md_assemble (char * str)
*** 1452,1458 ****
}
inst1 = opcode1->bit_sequence;
! inst1 |= ((imm & 0xFFFF0000) >> 16) & IMM_MASK;
output[0] = INST_BYTE0 (inst1);
output[1] = INST_BYTE1 (inst1);
output[2] = INST_BYTE2 (inst1);
--- 1452,1458 ----
}
inst1 = opcode1->bit_sequence;
! inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
output[0] = INST_BYTE0 (inst1);
output[1] = INST_BYTE1 (inst1);
output[2] = INST_BYTE2 (inst1);
*************** md_assemble (char * str)
*** 1461,1467 ****
}
inst |= (reg1 << RA_LOW) & RA_MASK;
! inst |= (imm << IMM_LOW) & IMM_MASK;
break;
case INST_TYPE_RD_IMM:
--- 1461,1467 ----
}
inst |= (reg1 << RA_LOW) & RA_MASK;
! inst |= (immed << IMM_LOW) & IMM_MASK;
break;
case INST_TYPE_RD_IMM:
*************** md_assemble (char * str)
*** 1499,1513 ****
exp.X_add_symbol,
exp.X_add_number,
opc);
! imm = 0;
}
else
{
output = frag_more (isize);
! imm = exp.X_add_number;
}
! temp = imm & 0xFFFF8000;
if ((temp != 0) && (temp != 0xFFFF8000))
{
/* Needs an immediate inst. */
--- 1499,1513 ----
exp.X_add_symbol,
exp.X_add_number,
opc);
! immed = 0;
}
else
{
output = frag_more (isize);
! immed = exp.X_add_number;
}
! temp = immed & 0xFFFF8000;
if ((temp != 0) && (temp != 0xFFFF8000))
{
/* Needs an immediate inst. */
*************** md_assemble (char * str)
*** 1519,1525 ****
}
inst1 = opcode1->bit_sequence;
! inst1 |= ((imm & 0xFFFF0000) >> 16) & IMM_MASK;
output[0] = INST_BYTE0 (inst1);
output[1] = INST_BYTE1 (inst1);
output[2] = INST_BYTE2 (inst1);
--- 1519,1525 ----
}
inst1 = opcode1->bit_sequence;
! inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
output[0] = INST_BYTE0 (inst1);
output[1] = INST_BYTE1 (inst1);
output[2] = INST_BYTE2 (inst1);
*************** md_assemble (char * str)
*** 1528,1534 ****
}
inst |= (reg1 << RD_LOW) & RD_MASK;
! inst |= (imm << IMM_LOW) & IMM_MASK;
break;
case INST_TYPE_R2:
--- 1528,1534 ----
}
inst |= (reg1 << RD_LOW) & RD_MASK;
! inst |= (immed << IMM_LOW) & IMM_MASK;
break;
case INST_TYPE_R2:
*************** md_assemble (char * str)
*** 1572,1587 ****
exp.X_add_symbol,
exp.X_add_number,
opc);
! imm = 0;
}
else
{
output = frag_more (isize);
! imm = exp.X_add_number;
}
! temp = imm & 0xFFFF8000;
if ((temp != 0) && (temp != 0xFFFF8000))
{
/* Needs an immediate inst. */
--- 1572,1587 ----
exp.X_add_symbol,
exp.X_add_number,
opc);
! immed = 0;
}
else
{
output = frag_more (isize);
! immed = exp.X_add_number;
}
! temp = immed & 0xFFFF8000;
if ((temp != 0) && (temp != 0xFFFF8000))
{
/* Needs an immediate inst. */
*************** md_assemble (char * str)
*** 1593,1606 ****
}
inst1 = opcode1->bit_sequence;
! inst1 |= ((imm & 0xFFFF0000) >> 16) & IMM_MASK;
output[0] = INST_BYTE0 (inst1);
output[1] = INST_BYTE1 (inst1);
output[2] = INST_BYTE2 (inst1);
output[3] = INST_BYTE3 (inst1);
output = frag_more (isize);
}
! inst |= (imm << IMM_LOW) & IMM_MASK;
break;
case INST_TYPE_NONE:
--- 1593,1606 ----
}
inst1 = opcode1->bit_sequence;
! inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
output[0] = INST_BYTE0 (inst1);
output[1] = INST_BYTE1 (inst1);
output[2] = INST_BYTE2 (inst1);
output[3] = INST_BYTE3 (inst1);
output = frag_more (isize);
}
! inst |= (immed << IMM_LOW) & IMM_MASK;
break;
case INST_TYPE_NONE: