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[PATCH, ARM] Fix Cortex-A8 erratum veneer alignment
- From: Julian Brown <julian at codesourcery dot com>
- To: binutils at sourceware dot org
- Date: Wed, 18 Aug 2010 16:21:44 +0100
- Subject: [PATCH, ARM] Fix Cortex-A8 erratum veneer alignment
Hi,
This patch fixes an alignment issue which means that (under quite rare
circumstances) the veneers used for erratum workarounds in the linker
can be placed at insufficiently-aligned locations, causing predictable
chaos. This is a refinement to the fix mentioned in point (2) of the
message:
http://sourceware.org/ml/binutils/2009-08/msg00041.html
In short, the one Cortex-A8 erratum workaround which uses ARM-mode code
will now be aligned to a four-byte boundary, whereas before it may have
landed only on a two-byte boundary.
Also the enumeration value arm_stub_a8_veneer_lwm (which would
otherwise have been orphaned by this patch) is used in preference to
arm_stub_a8_veneer_b_cond elsewhere: this leads to no change in
functionality, but is somewhat more meaningful in that context. I can
apply that change separately if desired.
OK to apply? Tested with cross to ARM Linux. The new test case passes
with the main (non-testsuite) part of the patch, and fails without it.
Julian
ChangeLog
bfd/
* elf32-arm.c (arm_stub_required_alignment): New.
(arm_build_one_stub): Use above to partition stubs.
(make_branch_to_a8_stub): Use arm_stub_a8_veneer_lwm not
arm_stub_a8_veneer_b_cond.
ld/testsuite/
* ld-arm/arm-elf.exp (armelftests): Add cortex-a8-fix-blx-bcond.s.
* ld-arm/cortex-a8-fix-blx-bcond.s: New.
* ld-arm/cortex-a8-fix-blx-bcond.d: New.
? bfd/elf32-arm.c-partially-fixed
Index: bfd/elf32-arm.c
===================================================================
RCS file: /cvs/src/src/bfd/elf32-arm.c,v
retrieving revision 1.238
diff -c -p -r1.238 elf32-arm.c
*** bfd/elf32-arm.c 18 Aug 2010 12:24:05 -0000 1.238
--- bfd/elf32-arm.c 18 Aug 2010 14:47:05 -0000
*************** static bfd_reloc_status_type elf32_arm_f
*** 3475,3480 ****
--- 3475,3510 ----
Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
const char *, int, struct elf_link_hash_entry *, bfd_boolean *, char **);
+ static unsigned int
+ arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
+ {
+ switch (stub_type)
+ {
+ case arm_stub_a8_veneer_b_cond:
+ case arm_stub_a8_veneer_b:
+ case arm_stub_a8_veneer_bl:
+ return 2;
+
+ case arm_stub_long_branch_any_any:
+ case arm_stub_long_branch_v4t_arm_thumb:
+ case arm_stub_long_branch_thumb_only:
+ case arm_stub_long_branch_v4t_thumb_thumb:
+ case arm_stub_long_branch_v4t_thumb_arm:
+ case arm_stub_short_branch_v4t_thumb_arm:
+ case arm_stub_long_branch_any_arm_pic:
+ case arm_stub_long_branch_any_thumb_pic:
+ case arm_stub_long_branch_v4t_thumb_thumb_pic:
+ case arm_stub_long_branch_v4t_arm_thumb_pic:
+ case arm_stub_long_branch_v4t_thumb_arm_pic:
+ case arm_stub_long_branch_thumb_only_pic:
+ case arm_stub_a8_veneer_blx:
+ return 4;
+
+ default:
+ abort (); /* Should be unreachable. */
+ }
+ }
+
static bfd_boolean
arm_build_one_stub (struct bfd_hash_entry *gen_entry,
void * in_arg)
*************** arm_build_one_stub (struct bfd_hash_entr
*** 3506,3514 ****
stub_sec = stub_entry->stub_sec;
if ((globals->fix_cortex_a8 < 0)
! != (stub_entry->stub_type >= arm_stub_a8_veneer_lwm))
! /* We have to do the a8 fixes last, as they are less aligned than
! the other veneers. */
return TRUE;
/* Make a note of the offset within the stubs for this entry. */
--- 3536,3543 ----
stub_sec = stub_entry->stub_sec;
if ((globals->fix_cortex_a8 < 0)
! != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
! /* We have to do less-strictly-aligned fixes last. */
return TRUE;
/* Make a note of the offset within the stubs for this entry. */
*************** make_branch_to_a8_stub (struct bfd_hash_
*** 13356,13362 ****
data = (struct a8_branch_to_stub_data *) in_arg;
if (stub_entry->target_section != data->writing_section
! || stub_entry->stub_type < arm_stub_a8_veneer_b_cond)
return TRUE;
contents = data->contents;
--- 13385,13391 ----
data = (struct a8_branch_to_stub_data *) in_arg;
if (stub_entry->target_section != data->writing_section
! || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
return TRUE;
contents = data->contents;
Index: ld/testsuite/ld-arm/arm-elf.exp
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-arm/arm-elf.exp,v
retrieving revision 1.77
diff -c -p -r1.77 arm-elf.exp
*** ld/testsuite/ld-arm/arm-elf.exp 11 May 2010 17:36:28 -0000 1.77
--- ld/testsuite/ld-arm/arm-elf.exp 18 Aug 2010 14:47:05 -0000
*************** set armelftests {
*** 221,226 ****
--- 221,230 ----
"-EL -mcpu=cortex-a8" {cortex-a8-fix-hdr.s}
{{objdump -dr cortex-a8-fix-hdr.d}}
"cortex-a8-fix-hdr"}
+ {"Cortex-A8 erratum fix, blx.w and b<cond>.w together"
+ "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-blx-bcond.s}
+ {{objdump -dr cortex-a8-fix-blx-bcond.d}}
+ "cortex-a8-fix-blx-bcond"}
{"Unwinding and -gc-sections" "-gc-sections" "" {gc-unwind.s}
{{objdump -sj.data gc-unwind.d}}
"gc-unwind"}
Index: ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.d
===================================================================
RCS file: ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.d
diff -N ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.d
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.d 18 Aug 2010 14:47:05 -0000
***************
*** 0 ****
--- 1,1107 ----
+
+ .*: file format .*
+
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+ 9d4c: f3af 8000 nop\.w
+ 9d50: f3af 8000 nop\.w
+ 9d54: f3af 8000 nop\.w
+ 9d58: f3af 8000 nop\.w
+ 9d5c: f3af 8000 nop\.w
+ 9d60: f3af 8000 nop\.w
+ 9d64: f3af 8000 nop\.w
+ 9d68: f3af 8000 nop\.w
+ 9d6c: f3af 8000 nop\.w
+ 9d70: f3af 8000 nop\.w
+ 9d74: f3af 8000 nop\.w
+ 9d78: f3af 8000 nop\.w
+ 9d7c: f3af 8000 nop\.w
+ 9d80: f3af 8000 nop\.w
+ 9d84: f3af 8000 nop\.w
+ 9d88: f3af 8000 nop\.w
+ 9d8c: f3af 8000 nop\.w
+ 9d90: f3af 8000 nop\.w
+ 9d94: f3af 8000 nop\.w
+ 9d98: f3af 8000 nop\.w
+ 9d9c: f3af 8000 nop\.w
+ 9da0: f3af 8000 nop\.w
+ 9da4: f3af 8000 nop\.w
+ 9da8: f3af 8000 nop\.w
+ 9dac: f3af 8000 nop\.w
+ 9db0: f3af 8000 nop\.w
+ 9db4: f3af 8000 nop\.w
+ 9db8: f3af 8000 nop\.w
+ 9dbc: f3af 8000 nop\.w
+ 9dc0: f3af 8000 nop\.w
+ 9dc4: f3af 8000 nop\.w
+ 9dc8: f3af 8000 nop\.w
+ 9dcc: f3af 8000 nop\.w
+ 9dd0: f3af 8000 nop\.w
+ 9dd4: f3af 8000 nop\.w
+ 9dd8: f3af 8000 nop\.w
+ 9ddc: f3af 8000 nop\.w
+ 9de0: f3af 8000 nop\.w
+ 9de4: f3af 8000 nop\.w
+ 9de8: f3af 8000 nop\.w
+ 9dec: f3af 8000 nop\.w
+ 9df0: f3af 8000 nop\.w
+ 9df4: f3af 8000 nop\.w
+ 9df8: f3af 8000 nop\.w
+ 9dfc: f3af 8000 nop\.w
+ 9e00: f3af 8000 nop\.w
+ 9e04: f3af 8000 nop\.w
+ 9e08: f3af 8000 nop\.w
+ 9e0c: f3af 8000 nop\.w
+ 9e10: f3af 8000 nop\.w
+ 9e14: f3af 8000 nop\.w
+ 9e18: f3af 8000 nop\.w
+ 9e1c: f3af 8000 nop\.w
+ 9e20: f3af 8000 nop\.w
+ 9e24: f3af 8000 nop\.w
+ 9e28: f3af 8000 nop\.w
+ 9e2c: f3af 8000 nop\.w
+ 9e30: f3af 8000 nop\.w
+ 9e34: f3af 8000 nop\.w
+ 9e38: f3af 8000 nop\.w
+ 9e3c: f3af 8000 nop\.w
+ 9e40: f3af 8000 nop\.w
+ 9e44: f3af 8000 nop\.w
+ 9e48: f3af 8000 nop\.w
+ 9e4c: f3af 8000 nop\.w
+ 9e50: f3af 8000 nop\.w
+ 9e54: f3af 8000 nop\.w
+ 9e58: f3af 8000 nop\.w
+ 9e5c: f3af 8000 nop\.w
+ 9e60: f3af 8000 nop\.w
+ 9e64: f3af 8000 nop\.w
+ 9e68: f3af 8000 nop\.w
+ 9e6c: f3af 8000 nop\.w
+ 9e70: f3af 8000 nop\.w
+ 9e74: f3af 8000 nop\.w
+ 9e78: f3af 8000 nop\.w
+ 9e7c: f3af 8000 nop\.w
+ 9e80: f3af 8000 nop\.w
+ 9e84: f3af 8000 nop\.w
+ 9e88: f3af 8000 nop\.w
+ 9e8c: f3af 8000 nop\.w
+ 9e90: f3af 8000 nop\.w
+ 9e94: f3af 8000 nop\.w
+ 9e98: f3af 8000 nop\.w
+ 9e9c: f3af 8000 nop\.w
+ 9ea0: f3af 8000 nop\.w
+ 9ea4: f3af 8000 nop\.w
+ 9ea8: f3af 8000 nop\.w
+ 9eac: f3af 8000 nop\.w
+ 9eb0: f3af 8000 nop\.w
+ 9eb4: f3af 8000 nop\.w
+ 9eb8: f3af 8000 nop\.w
+ 9ebc: f3af 8000 nop\.w
+ 9ec0: f3af 8000 nop\.w
+ 9ec4: f3af 8000 nop\.w
+ 9ec8: f3af 8000 nop\.w
+ 9ecc: f3af 8000 nop\.w
+ 9ed0: f3af 8000 nop\.w
+ 9ed4: f3af 8000 nop\.w
+ 9ed8: f3af 8000 nop\.w
+ 9edc: f3af 8000 nop\.w
+ 9ee0: f3af 8000 nop\.w
+ 9ee4: f3af 8000 nop\.w
+ 9ee8: f3af 8000 nop\.w
+ 9eec: f3af 8000 nop\.w
+ 9ef0: f3af 8000 nop\.w
+ 9ef4: f3af 8000 nop\.w
+
+ 00009ef8 <arm_target>:
+ 9ef8: e0843005 add r3, r4, r5
+ 9efc: e12fff1e bx lr
+
+ 00009f00 <bl_insns>:
+ 9f00: bf00 nop
+ 9f02: eb01 0002 add\.w r0, r1, r2
+ 9f06: f7ff eff8 blx 9ef8 <arm_target>
+ 9f0a: eb01 0002 add\.w r0, r1, r2
+ 9f0e: f7ff eff4 blx 9ef8 <arm_target>
+ 9f12: eb01 0002 add\.w r0, r1, r2
+ 9f16: f7ff eff0 blx 9ef8 <arm_target>
+ 9f1a: eb01 0002 add\.w r0, r1, r2
+ 9f1e: f7ff efec blx 9ef8 <arm_target>
+ 9f22: eb01 0002 add\.w r0, r1, r2
+ 9f26: f7ff efe8 blx 9ef8 <arm_target>
+ 9f2a: eb01 0002 add\.w r0, r1, r2
+ 9f2e: f7ff efe4 blx 9ef8 <arm_target>
+ 9f32: eb01 0002 add\.w r0, r1, r2
+ 9f36: f7ff efe0 blx 9ef8 <arm_target>
+ 9f3a: eb01 0002 add\.w r0, r1, r2
+ 9f3e: f7ff efdc blx 9ef8 <arm_target>
+ 9f42: eb01 0002 add\.w r0, r1, r2
+ 9f46: f7ff efd8 blx 9ef8 <arm_target>
+ 9f4a: eb01 0002 add\.w r0, r1, r2
+ 9f4e: f7ff efd4 blx 9ef8 <arm_target>
+ 9f52: eb01 0002 add\.w r0, r1, r2
+ 9f56: f7ff efd0 blx 9ef8 <arm_target>
+ 9f5a: eb01 0002 add\.w r0, r1, r2
+ 9f5e: f7ff efcc blx 9ef8 <arm_target>
+ 9f62: eb01 0002 add\.w r0, r1, r2
+ 9f66: f7ff efc8 blx 9ef8 <arm_target>
+ 9f6a: eb01 0002 add\.w r0, r1, r2
+ 9f6e: f7ff efc4 blx 9ef8 <arm_target>
+ 9f72: eb01 0002 add\.w r0, r1, r2
+ 9f76: f7ff efc0 blx 9ef8 <arm_target>
+ 9f7a: eb01 0002 add\.w r0, r1, r2
+ 9f7e: f7ff efbc blx 9ef8 <arm_target>
+ 9f82: eb01 0002 add\.w r0, r1, r2
+ 9f86: f7ff efb8 blx 9ef8 <arm_target>
+ 9f8a: eb01 0002 add\.w r0, r1, r2
+ 9f8e: f7ff efb4 blx 9ef8 <arm_target>
+ 9f92: eb01 0002 add\.w r0, r1, r2
+ 9f96: f7ff efb0 blx 9ef8 <arm_target>
+ 9f9a: eb01 0002 add\.w r0, r1, r2
+ 9f9e: f7ff efac blx 9ef8 <arm_target>
+ 9fa2: eb01 0002 add\.w r0, r1, r2
+ 9fa6: f7ff efa8 blx 9ef8 <arm_target>
+ 9faa: eb01 0002 add\.w r0, r1, r2
+ 9fae: f7ff efa4 blx 9ef8 <arm_target>
+ 9fb2: eb01 0002 add\.w r0, r1, r2
+ 9fb6: f7ff efa0 blx 9ef8 <arm_target>
+ 9fba: eb01 0002 add\.w r0, r1, r2
+ 9fbe: f7ff ef9c blx 9ef8 <arm_target>
+ 9fc2: eb01 0002 add\.w r0, r1, r2
+ 9fc6: f7ff ef98 blx 9ef8 <arm_target>
+ 9fca: eb01 0002 add\.w r0, r1, r2
+ 9fce: f7ff ef94 blx 9ef8 <arm_target>
+ 9fd2: eb01 0002 add\.w r0, r1, r2
+ 9fd6: f7ff ef90 blx 9ef8 <arm_target>
+ 9fda: eb01 0002 add\.w r0, r1, r2
+ 9fde: f7ff ef8c blx 9ef8 <arm_target>
+ 9fe2: eb01 0002 add\.w r0, r1, r2
+ 9fe6: f7ff ef88 blx 9ef8 <arm_target>
+ 9fea: eb01 0002 add\.w r0, r1, r2
+ 9fee: f7ff ef84 blx 9ef8 <arm_target>
+ 9ff2: eb01 0002 add\.w r0, r1, r2
+ 9ff6: f7ff ef80 blx 9ef8 <arm_target>
+ 9ffa: eb01 0002 add\.w r0, r1, r2
+ 9ffe: f000 e804 blx a008 <bl_insns\+0x108>
+ a002: 4770 bx lr
+ a004: f3af 8000 nop\.w
+ a008: eaffffba b 9ef8 <arm_target>
+ a00c: d101 bne\.n a012 <bl_insns\+0x112>
+ a00e: f7fe bff8 b\.w 9002 <_start\+0x102>
+ a012: f7fe bfe6 b\.w 8fe2 <_start\+0xe2>
Index: ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.s
===================================================================
RCS file: ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.s
diff -N ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.s 18 Aug 2010 14:47:05 -0000
***************
*** 0 ****
--- 1,81 ----
+ .syntax unified
+ .cpu cortex-a8
+ .thumb
+ .text
+
+ @ expansion 32 bytes
+ .macro bw1
+ 1:
+ add.w r0, r1, r2
+ blx.w arm_target
+ add.w r0, r1, r2
+ blx.w arm_target
+ add.w r0, r1, r2
+ blx.w arm_target
+ add.w r0, r1, r2
+ blx.w arm_target
+ .endm
+
+ @ expansion 128 bytes
+ .macro bw2
+ bw1
+ bw1
+ bw1
+ bw1
+ .endm
+
+ @ expansion 32 bytes
+ .macro bw3
+ 1:
+ add.w r0, r1, r2
+ bne.w 1b
+ add.w r0, r1, r2
+ bne.w 1b
+ add.w r0, r1, r2
+ bne.w 1b
+ add.w r0, r1, r2
+ bne.w 1b
+ .endm
+
+ @ expansion 128 bytes
+ .macro bw4
+ bw3
+ bw3
+ bw3
+ bw3
+ .endm
+
+ .align 3
+ .global _start
+
+ .thumb
+ .thumb_func
+ .type _start, %function
+ _start:
+ nop
+
+ @ Trigger Cortex-A8 erratum workaround with b<cond> instructions.
+ bw4
+ bw4
+
+ nop
+
+ .rept 957
+ nop.w
+ .endr
+
+ .arm
+ arm_target:
+ add r3, r4, r5
+ bx lr
+
+ .thumb
+ bl_insns:
+
+ nop
+
+ @ ...and again with bl instructions.
+ bw2
+ bw2
+
+ bx lr