Re: [PATCH,ppc] prohibit string instructions on processors that don't support them

[Peter Bergner <bergner at vnet dot ibm dot com>]

On Wed, 2010-08-25 at 12:40 -0700, Nathan Froyd wrote:
> Processors in the E500 family (both the SPE and oddly-named e500mc*
> variety) do not support load/store string instructions.  This patch adds
> a PPC_OPCODE_STRING flag for marking these instructions so the assembler
> can give appropriate error messages when attempting to assemble such
> instructions.
> 
> I've attempted to add the PPC_OPCODE_STRING flag to only processors that
> support it; when in doubt, I have added it, on the grounds that doing so
> won't break anything.  I left the flag off the "efs" and "spe"
> pseudo-CPUs; I know of no embedded floating-point CPU that supports
> string instructions.

Wouldn't it be easier to just add the appropriate flags to the deprecated
field to disable the string ops for the cpus that don't want them
similar to how we disable lwsync for E500?

  {"lwsync",      XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},


Like so:

-{"lswx",	X(31,533),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, RB}},
+{"lswx",	X(31,533),	X_MASK,      PPCCOM,	E500|...,	{RT, RA0, RB}},

or 

-{"lswx",	X(31,533),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, RB}},
+{"lswx",	X(31,533),	X_MASK,      PPCCOM,	PPCNOSTR,	{RT, RA0, RB}},

where PPCNOSTR (or whatever macro name you want) is a new #define for the cpus
without the string ops.  One benefit is that is saves a bit in the ppc_cpu_t
opcodes mask which we'll need as we add support for new processors in the
future.



> Index: opcodes/sparc-dis.c
> ===================================================================
> RCS file: /cvs/src/src/opcodes/sparc-dis.c,v
> retrieving revision 1.17
> diff -u -u -r1.17 sparc-dis.c
> --- opcodes/sparc-dis.c	27 Jun 2010 04:07:55 -0000	1.17
> +++ opcodes/sparc-dis.c	25 Aug 2010 19:33:11 -0000
[snip]

I assume this was a cut/paste error?


Peter