This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
Re: TLS descriptors for ARM
- From: Nathan Sidwell <nathan at codesourcery dot com>
- To: Alexandre Oliva <aoliva at redhat dot com>
- Cc: binutils <binutils at sourceware dot org>, glommer at gmail dot com, Richard Earnshaw <rearnsha at arm dot com>
- Date: Thu, 06 Jan 2011 13:51:51 +0000
- Subject: Re: TLS descriptors for ARM
- References: <4D245C80.8040800@codesourcery.com> <or4o9m2lor.fsf@livre.localdomain>
On 01/06/11 13:42, Alexandre Oliva wrote:
On Jan 5, 2011, Nathan Sidwell<nathan@codesourcery.com> wrote:
It refers to R_ARM_TLS_DESCSEQ16 and R_ARM_TLS_DESCSEQ32, but no such
relocations are defined in the document. You may want to add a blurb
about that like you did to the e-mail.
oops, I see a proof-reading malfunction.
I suppose you meant to refer to R_ARM_THM_TLS_DESCSEQ too, although I
don't quite understand the rationale for the THM-specific relocations;
wouldn't non-THM relocations with odd addresses have worked?
I do not know.
The description of IE relaxation for TLS_CALLs gives me the impression
that a single instruction could be replaced with two. What am I
missing?
Are you referring to this bit:
ldr r0, .Lt0
.L1 add r0, pc
ldr r0, [r0]
...
.Lt0: .word foo(gottpoff) + (. - .L1 - 4)
for thumb.
you are correct, it relaxes the 32-bit call instruction to 2 16-bit thumb
instructions (there being no suitable 32bit thumb instruction available).
nathan
--
Nathan Sidwell :: http://www.codesourcery.com :: CodeSourcery