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fix blx disassembly
- From: Nathan Sidwell <nathan at codesourcery dot com>
- To: binutils <binutils at sourceware dot org>
- Date: Thu, 06 Jan 2011 14:33:08 +0000
- Subject: fix blx disassembly
I've committed this patch to correctly reject disassembly of blx instructions
that have the bottom bit set. Valid blx instructions must have the offset bit
zero clear, and real hardware will raise an exception if it is not.
We found a bug during the arm tls descriptor development that would have been
much more obvious had the disassembler shouted at me :)
nathan
--
Nathan Sidwell :: http://www.codesourcery.com :: CodeSourcery
2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
gas/testsuite/
* gas/arm/blx-bad.s: New.
* gas/arm/blx-bad.d: New.
opcodes/
* arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
Index: gas/testsuite/gas/arm/blx-bad.d
===================================================================
RCS file: gas/testsuite/gas/arm/blx-bad.d
diff -N gas/testsuite/gas/arm/blx-bad.d
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/blx-bad.d 6 Jan 2011 14:14:35 -0000
***************
*** 0 ****
--- 1,21 ----
+ #objdump: -drw --show-raw-insn
+ #name: BLX encoding
+
+ .*: file format .*arm.*
+
+
+ Disassembly of section .text:
+
+ 00000000 <ARM>:
+ 0: e1a00000 nop ; \(mov r0, r0\)
+
+ 00000004 <THUMB>:
+ 4: f7ff effc blx 0 <ARM>
+ 8: 46c0 nop ; \(mov r8, r8\)
+ a: f7ff effa blx 0 <ARM>
+ e: 46c0 nop ; \(mov r8, r8\)
+ 10: f7ff eff6 blx 0 <ARM>
+ 14: f7ff eff5 ; <UNDEFINED> instruction: 0xf7ffeff5
+ 18: 46c0 nop ; \(mov r8, r8\)
+ 1a: f7ff eff1 ; <UNDEFINED> instruction: 0xf7ffeff1
+ 1e: f7ff eff0 blx 0 <ARM>
Index: gas/testsuite/gas/arm/blx-bad.s
===================================================================
RCS file: gas/testsuite/gas/arm/blx-bad.s
diff -N gas/testsuite/gas/arm/blx-bad.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/blx-bad.s 6 Jan 2011 14:14:35 -0000
***************
*** 0 ****
--- 1,16 ----
+ .arm
+ .func ARM
+ ARM: nop
+
+ .thumb
+ .thumb_func
+ THUMB:
+ blx ARM
+ nop
+ blx ARM
+ nop
+ .inst 0xf7ffeff6
+ .inst 0xf7ffeff5
+ nop
+ .inst 0xf7ffeff1
+ .inst 0xf7ffeff0
Index: opcodes/arm-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/arm-dis.c,v
retrieving revision 1.135
diff -c -3 -p -r1.135 arm-dis.c
*** opcodes/arm-dis.c 27 Sep 2010 09:47:04 -0000 1.135
--- opcodes/arm-dis.c 6 Jan 2011 14:14:41 -0000
*************** static const struct opcode32 thumb32_opc
*** 1563,1569 ****
{ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
/* These have been 32-bit since the invention of Thumb. */
! {ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx%c\t%B%x"},
{ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
/* Fallback. */
--- 1563,1569 ----
{ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
/* These have been 32-bit since the invention of Thumb. */
! {ARM_EXT_V4T, 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
{ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
/* Fallback. */