Re: [PATCH] AMD bdver2 processors 1/2 - BMI

["H.J. Lu" <hjl dot tools at gmail dot com>]

On Thu, Jan 6, 2011 at 2:45 PM, Quentin Neill
<quentin.neill.gnu@gmail.com> wrote:
> On Thu, Jan 6, 2011 at 2:26 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>> On Thu, Jan 6, 2011 at 12:20 PM, Quentin Neill
>> <quentin.neill.gnu@gmail.com> wrote:
>>> On Wed, Jan 5, 2011 at 12:22 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>> On Wed, Jan 5, 2011 at 9:41 AM, Quentin Neill
>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>> On Wed, Jan 5, 2011 at 11:33 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>>> On Wed, Jan 5, 2011 at 8:45 AM, Quentin Neill
>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>> In i386-dis.c don't you need to order your REG_VEX enum and entry in
>>>>>>> the reg_table (move REG_VEX_0F38F3 above REG_VEX_0FAE):
>>>>>>> +++ b/opcodes/i386-dis.c
>>>>>>> @@ -598,8 +598,8 @@ enum
>>>>>>> ?REG_VEX_0F71,
>>>>>>> ?REG_VEX_0F72,
>>>>>>> ?REG_VEX_0F73,
>>>>>>> - ?REG_VEX_0FAE,
>>>>>>> ?REG_VEX_0F38F3,
>>>>>>> + ?REG_VEX_0FAE,
>>>>>>> ?REG_XOP_LWPCB,
>>>>>>> ?REG_XOP_LWP
>>>>>>> ?};
>>>>>>
>>>>>> I have
>>>>>>
>>>>>> ?REG_VEX_0F73,
>>>>>> ?REG_VEX_0FAE,
>>>>>> ?REG_VEX_0F38F3,
>>>>>> ?REG_XOP_LWPCB,
>>>>>> ?REG_XOP_LWP
>>>>>>
>>>>>> Please make sure your source is correct.
>>>>>>
>>>>>>
>>>>>> --
>>>>>> H.J.
>>>>>
>>>>> That was a small patch I proposed to move REG_VEX_0F38F3 above
>>>>> REG_VEX_0FAE to make them numerically sorted.
>>>>
>>>> That is wrong. ?VEX opcodes are sorted by
>>>>
>>>> VEX_0FXX
>>>> VEX_0F38XX
>>>> VEX_0F3AXX
>>>>
>>>>
>>>> --
>>>> H.J.
>>>>
>>>
>>> I also notice you did not implement ".bmi" cpu_arch entry in
>>> tc-i386.c, can you comment on that?
>>
>> You should submit a new BMI patch minus what I have
>> implemented for you.
>>
>>> Should I follow your lead concerning adding a ".tbm" directive?
>>
>> No.
>>
>>
>> --
>> H.J.
>>
>
> Patch adds BMI docs, .bmi arch directive and tests.
>
> Passes "make -k check RUNTESTFLAGS=i386.exp", okay to commit?
>

OK.

Thanks.


-- 
H.J.