Re: [PATCH] AMD bdver2 processors 1/2 - BMI

[Quentin Neill <quentin dot neill dot gnu at gmail dot com>]

On Fri, Jan 7, 2011 at 5:29 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Thu, Jan 6, 2011 at 2:49 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>> On Thu, Jan 6, 2011 at 2:45 PM, Quentin Neill
>> <quentin.neill.gnu@gmail.com> wrote:
>>> On Thu, Jan 6, 2011 at 2:26 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>> On Thu, Jan 6, 2011 at 12:20 PM, Quentin Neill
>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>> On Wed, Jan 5, 2011 at 12:22 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>>> On Wed, Jan 5, 2011 at 9:41 AM, Quentin Neill
>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>> On Wed, Jan 5, 2011 at 11:33 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>>>>> On Wed, Jan 5, 2011 at 8:45 AM, Quentin Neill
>>>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>>>> In i386-dis.c don't you need to order your REG_VEX enum and entry in
>>>>>>>>> the reg_table (move REG_VEX_0F38F3 above REG_VEX_0FAE):
>>>>>>>>> +++ b/opcodes/i386-dis.c
>>>>>>>>> @@ -598,8 +598,8 @@ enum
>>>>>>>>> ?REG_VEX_0F71,
>>>>>>>>> ?REG_VEX_0F72,
>>>>>>>>> ?REG_VEX_0F73,
>>>>>>>>> - ?REG_VEX_0FAE,
>>>>>>>>> ?REG_VEX_0F38F3,
>>>>>>>>> + ?REG_VEX_0FAE,
>>>>>>>>> ?REG_XOP_LWPCB,
>>>>>>>>> ?REG_XOP_LWP
>>>>>>>>> ?};
>>>>>>>>
>>>>>>>> I have
>>>>>>>>
>>>>>>>> ?REG_VEX_0F73,
>>>>>>>> ?REG_VEX_0FAE,
>>>>>>>> ?REG_VEX_0F38F3,
>>>>>>>> ?REG_XOP_LWPCB,
>>>>>>>> ?REG_XOP_LWP
>>>>>>>>
>>>>>>>> Please make sure your source is correct.
>>>>>>>>
>>>>>>>>
>>>>>>>> --
>>>>>>>> H.J.
>>>>>>>
>>>>>>> That was a small patch I proposed to move REG_VEX_0F38F3 above
>>>>>>> REG_VEX_0FAE to make them numerically sorted.
>>>>>>
>>>>>> That is wrong. ?VEX opcodes are sorted by
>>>>>>
>>>>>> VEX_0FXX
>>>>>> VEX_0F38XX
>>>>>> VEX_0F3AXX
>>>>>>
>>>>>>
>>>>>> --
>>>>>> H.J.
>>>>>>
>>>>>
>>>>> I also notice you did not implement ".bmi" cpu_arch entry in
>>>>> tc-i386.c, can you comment on that?
>>>>
>>>> You should submit a new BMI patch minus what I have
>>>> implemented for you.
>>>>
>>>>> Should I follow your lead concerning adding a ".tbm" directive?
>>>>
>>>> No.
>>>>
>>>>
>>>> --
>>>> H.J.
>>>>
>>>
>>> Patch adds BMI docs, .bmi arch directive and tests.
>>>
>>> Passes "make -k check RUNTESTFLAGS=i386.exp", okay to commit?
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>
> Could you please remove "-k" next time when you run tests?
> All x86 binutils tests should pass on Linux. ?I checked in this
> patch to fix the regression.
>
> --
> H.J.
> ----
> diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
> index 6f60a1a..67eee86 100644
> --- a/gas/testsuite/ChangeLog
> +++ b/gas/testsuite/ChangeLog
> @@ -1,3 +1,8 @@
> +2011-01-07 ?H.J. Lu ?<hongjiu.lu@intel.com>
> +
> + ? ? ? * gas/i386/ilp32/x86-64-arch-2.d: Add bmi flag and BMI instruction
> + ? ? ? pattern.
> +
> ?2011-01-07 ?Quentin Neill ?<quentin.neill@amd.com>
>
> ? ? ? ?* gas/i386/arch-10.s: Add a BMI instruction.
> diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-arch-2.d b/gas/testsuite/gas/i3
> 86/ilp32/x86-64-arch-2.d
> index 10c3565..779a95a 100644
> --- a/gas/testsuite/gas/i386/ilp32/x86-64-arch-2.d
> +++ b/gas/testsuite/gas/i386/ilp32/x86-64-arch-2.d
> @@ -1,5 +1,5 @@
> ?#source: ../x86-64-arch-2.s
> -#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflu
> sh+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
> +#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflu
> sh+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi
> ?#objdump: -dw
> ?#name: x86-64 (ILP32) arch 2
>
> @@ -37,4 +37,5 @@ Disassembly of section .text:
> ?[ ? ? ?]*[a-f0-9]+: ? ?0f 01 da ? ? ? ? ? ? ? ?vmload
> ?[ ? ? ?]*[a-f0-9]+: ? ?f3 0f bd d9 ? ? ? ? ? ? lzcnt ?%ecx,%ebx
> ?[ ? ? ?]*[a-f0-9]+: ? ?0f a7 c0 ? ? ? ? ? ? ? ?xstore-rng
> +[ ? ? ?]*[a-f0-9]+: ? ?c4 e2 60 f3 c9 ? ? ? ? ?blsr ? %ecx,%ebx
> ?#pass

Yes.  Thanks for the fix.
-- 
Quentin