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Re: [PATCH] MIPS: 32-bit microMIPS DSP ASE support
- From: Alan Modra <amodra at gmail dot com>
- To: "Maciej W. Rozycki" <macro at codesourcery dot com>
- Cc: Richard Sandiford <rdsandiford at googlemail dot com>, binutils at sourceware dot org, Catherine Moore <clm at codesourcery dot com>, Chao-ying Fu <fu at mips dot com>
- Date: Wed, 1 Aug 2012 10:12:16 +0930
- Subject: Re: [PATCH] MIPS: 32-bit microMIPS DSP ASE support
- References: <alpine.DEB.1.10.1110252323030.28657@tp.orcam.me.uk> <87fwhdrzn3.fsf@firetop.home> <alpine.DEB.1.10.1207310330430.19403@tp.orcam.me.uk>
In future, please compile your code with both 32-bit and 64-bit
compilers before committing. Your ChangeLog entry was wrong too.
Fixed along with this other housekeeping.
* h8300-dis.c: Fix printf arg warnings.
* i960-dis.c: Likewise.
* mips-dis.c: Likewise.
* pdp11-dis.c: Likewise.
* sh-dis.c: Likewise.
* v850-dis.c: Likewise.
* configure.in: Formatting.
* configure: Regenerate.
* rl78-decode.c: Regenerate.
* po/POTFILES.in: Regenerate.
Index: opcodes/configure.in
===================================================================
RCS file: /cvs/src/src/opcodes/configure.in,v
retrieving revision 1.107
diff -u -p -r1.107 configure.in
--- opcodes/configure.in 27 Jul 2012 16:30:57 -0000 1.107
+++ opcodes/configure.in 1 Aug 2012 00:24:32 -0000
@@ -253,14 +253,14 @@ if test x${all_targets} = xfalse ; then
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;;
- bfd_epiphany_arch) ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;;
+ bfd_epiphany_arch) ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;;
bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;;
bfd_lm32_arch) ta="$ta lm32-asm.lo lm32-desc.lo lm32-dis.lo lm32-ibld.lo lm32-opc.lo lm32-opinst.lo" using_cgen=yes ;;
bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;;
bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;;
bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
- bfd_m9s12x_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
+ bfd_m9s12x_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m9s12xg_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;;
bfd_m88k_arch) ta="$ta m88k-dis.lo" ;;
Index: opcodes/h8300-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/h8300-dis.c,v
retrieving revision 1.24
diff -u -p -r1.24 h8300-dis.c
--- opcodes/h8300-dis.c 27 Jun 2010 04:07:55 -0000 1.24
+++ opcodes/h8300-dis.c 1 Aug 2012 00:24:32 -0000
@@ -298,7 +298,7 @@ print_one_arg (disassemble_info *info,
outfn (stream, "@(0x%x:%d,%s.l)", cst, cstlen, lregnames[rdisp_n]);
else if (x & CTRL)
- outfn (stream, cregnames[rn]);
+ outfn (stream, "%s", cregnames[rn]);
else if ((x & MODE) == CCR)
outfn (stream, "ccr");
Index: opcodes/i960-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/i960-dis.c,v
retrieving revision 1.10
diff -u -p -r1.10 i960-dis.c
--- opcodes/i960-dis.c 11 Dec 2009 13:42:17 -0000 1.10
+++ opcodes/i960-dis.c 1 Aug 2012 00:24:34 -0000
@@ -204,7 +204,7 @@ ctrl (bfd_vma memaddr, unsigned long wor
return;
}
- (*info->fprintf_func) (stream, ctrl_tab[i].name);
+ (*info->fprintf_func) (stream, "%s", ctrl_tab[i].name);
if (word1 & 2)
/* Predicts branch not taken. */
(*info->fprintf_func) (stream, ".f");
@@ -276,7 +276,7 @@ cobr (bfd_vma memaddr, unsigned long wor
return;
}
- (*info->fprintf_func) (stream, cobr_tab[i].name);
+ (*info->fprintf_func) (stream, "%s", cobr_tab[i].name);
/* Predicts branch not taken. */
if (word1 & 2)
@@ -291,7 +291,7 @@ cobr (bfd_vma memaddr, unsigned long wor
/* M1 is 1 */
(*info->fprintf_func) (stream, "%d", src1);
else
- (*info->fprintf_func) (stream, reg_names[src1]);
+ (*info->fprintf_func) (stream, "%s", reg_names[src1]);
if (cobr_tab[i].numops > 1)
{
@@ -717,7 +717,7 @@ reg (unsigned long word1)
fp = 0;
}
- (*info->fprintf_func) (stream, mnemp);
+ (*info->fprintf_func) (stream, "%s", mnemp);
s1 = (word1 >> 5) & 1;
s2 = (word1 >> 6) & 1;
@@ -853,7 +853,7 @@ regop (int mode, int spec, int fp_reg, i
else
{
/* Non-FP register. */
- (*info->fprintf_func) (stream, reg_names[fp_reg]);
+ (*info->fprintf_func) (stream, "%s", reg_names[fp_reg]);
}
}
else
@@ -868,7 +868,7 @@ regop (int mode, int spec, int fp_reg, i
{
/* Register. */
if (spec == 0)
- (*info->fprintf_func) (stream, reg_names[fp_reg]);
+ (*info->fprintf_func) (stream, "%s", reg_names[fp_reg]);
else
(*info->fprintf_func) (stream, "sf%d", fp_reg);
}
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.93
diff -u -p -r1.93 mips-dis.c
--- opcodes/mips-dis.c 31 Jul 2012 21:38:54 -0000 1.93
+++ opcodes/mips-dis.c 1 Aug 2012 00:24:36 -0000
@@ -2412,31 +2412,31 @@ print_insn_micromips (bfd_vma memaddr, s
break;
case '2':
- infprintf (is, "0x%lx", GET_OP (insn, BP));
+ infprintf (is, "0x%x", GET_OP (insn, BP));
break;
case '3':
- infprintf (is, "0x%lx", GET_OP (insn, SA3));
+ infprintf (is, "0x%x", GET_OP (insn, SA3));
break;
case '4':
- infprintf (is, "0x%lx", GET_OP (insn, SA4));
+ infprintf (is, "0x%x", GET_OP (insn, SA4));
break;
case '5':
- infprintf (is, "0x%lx", GET_OP (insn, IMM8));
+ infprintf (is, "0x%x", GET_OP (insn, IMM8));
break;
case '6':
- infprintf (is, "0x%lx", GET_OP (insn, RS));
+ infprintf (is, "0x%x", GET_OP (insn, RS));
break;
case '7':
- infprintf (is, "$ac%ld", GET_OP (insn, DSPACC));
+ infprintf (is, "$ac%d", GET_OP (insn, DSPACC));
break;
case '8':
- infprintf (is, "0x%lx", GET_OP (insn, WRDSP));
+ infprintf (is, "0x%x", GET_OP (insn, WRDSP));
break;
case '0': /* DSP 6-bit signed immediate in bit 16. */
@@ -2453,7 +2453,7 @@ print_insn_micromips (bfd_vma memaddr, s
break;
case '^':
- infprintf (is, "0x%lx", GET_OP (insn, RD));
+ infprintf (is, "0x%x", GET_OP (insn, RD));
break;
case '|':
Index: opcodes/pdp11-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/pdp11-dis.c,v
retrieving revision 1.10
diff -u -p -r1.10 pdp11-dis.c
--- opcodes/pdp11-dis.c 5 Jul 2007 09:49:02 -0000 1.10
+++ opcodes/pdp11-dis.c 1 Aug 2012 00:24:36 -0000
@@ -214,15 +214,15 @@ print_insn_pdp11 (bfd_vma memaddr, disas
switch (OP.type)
{
case PDP11_OPCODE_NO_OPS:
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
goto done;
case PDP11_OPCODE_REG:
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
print_reg (dst, info);
goto done;
case PDP11_OPCODE_OP:
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
if (strcmp (OP.name, "jmp") == 0)
dst |= JUMP;
@@ -230,7 +230,7 @@ print_insn_pdp11 (bfd_vma memaddr, disas
return -1;
goto done;
case PDP11_OPCODE_FOP:
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
if (strcmp (OP.name, "jmp") == 0)
dst |= JUMP;
@@ -238,7 +238,7 @@ print_insn_pdp11 (bfd_vma memaddr, disas
return -1;
goto done;
case PDP11_OPCODE_REG_OP:
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
print_reg (src, info);
FPRINTF (F, OPERAND_SEPARATOR);
@@ -248,7 +248,7 @@ print_insn_pdp11 (bfd_vma memaddr, disas
return -1;
goto done;
case PDP11_OPCODE_REG_OP_REV:
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
if (print_operand (&memaddr, dst, info) < 0)
return -1;
@@ -258,7 +258,7 @@ print_insn_pdp11 (bfd_vma memaddr, disas
case PDP11_OPCODE_AC_FOP:
{
int ac = (opcode & 0xe0) >> 6;
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
print_freg (ac, info);
FPRINTF (F, OPERAND_SEPARATOR);
@@ -269,7 +269,7 @@ print_insn_pdp11 (bfd_vma memaddr, disas
case PDP11_OPCODE_FOP_AC:
{
int ac = (opcode & 0xe0) >> 6;
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
if (print_foperand (&memaddr, dst, info) < 0)
return -1;
@@ -280,7 +280,7 @@ print_insn_pdp11 (bfd_vma memaddr, disas
case PDP11_OPCODE_AC_OP:
{
int ac = (opcode & 0xe0) >> 6;
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
print_freg (ac, info);
FPRINTF (F, OPERAND_SEPARATOR);
@@ -291,7 +291,7 @@ print_insn_pdp11 (bfd_vma memaddr, disas
case PDP11_OPCODE_OP_AC:
{
int ac = (opcode & 0xe0) >> 6;
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
if (print_operand (&memaddr, dst, info) < 0)
return -1;
@@ -300,7 +300,7 @@ print_insn_pdp11 (bfd_vma memaddr, disas
goto done;
}
case PDP11_OPCODE_OP_OP:
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
if (print_operand (&memaddr, src, info) < 0)
return -1;
@@ -312,7 +312,7 @@ print_insn_pdp11 (bfd_vma memaddr, disas
{
int displ = (opcode & 0xff) << 8;
bfd_vma address = memaddr + (sign_extend (displ) >> 7);
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
(*info->print_address_func) (address, info);
goto done;
@@ -322,7 +322,7 @@ print_insn_pdp11 (bfd_vma memaddr, disas
int displ = (opcode & 0x3f) << 10;
bfd_vma address = memaddr - (displ >> 9);
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
print_reg (src, info);
FPRINTF (F, OPERAND_SEPARATOR);
@@ -332,7 +332,7 @@ print_insn_pdp11 (bfd_vma memaddr, disas
case PDP11_OPCODE_IMM8:
{
int code = opcode & 0xff;
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
FPRINTF (F, "%o", code);
goto done;
@@ -340,7 +340,7 @@ print_insn_pdp11 (bfd_vma memaddr, disas
case PDP11_OPCODE_IMM6:
{
int code = opcode & 0x3f;
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
FPRINTF (F, "%o", code);
goto done;
@@ -348,7 +348,7 @@ print_insn_pdp11 (bfd_vma memaddr, disas
case PDP11_OPCODE_IMM3:
{
int code = opcode & 7;
- FPRINTF (F, OP.name);
+ FPRINTF (F, "%s", OP.name);
FPRINTF (F, AFTER_INSTRUCTION);
FPRINTF (F, "%o", code);
goto done;
Index: opcodes/sh-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/sh-dis.c,v
retrieving revision 1.29
diff -u -p -r1.29 sh-dis.c
--- opcodes/sh-dis.c 17 May 2012 15:13:25 -0000 1.29
+++ opcodes/sh-dis.c 1 Aug 2012 00:24:37 -0000
@@ -356,10 +356,10 @@ print_insn_ppi (int field_b, struct disa
print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
break;
case DSP_REG_X:
- fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]);
+ fprintf_fn (stream, "%s", sx_tab[(field_b >> 6) & 3]);
break;
case DSP_REG_Y:
- fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]);
+ fprintf_fn (stream, "%s", sy_tab[(field_b >> 4) & 3]);
break;
case A_MACH:
fprintf_fn (stream, "mach");
Index: opcodes/v850-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/v850-dis.c,v
retrieving revision 1.14
diff -u -p -r1.14 v850-dis.c
--- opcodes/v850-dis.c 17 May 2012 15:13:26 -0000 1.14
+++ opcodes/v850-dis.c 1 Aug 2012 00:24:37 -0000
@@ -406,7 +406,7 @@ disassemble (bfd_vma memaddr, struct dis
else
shown_one = 1;
- info->fprintf_func (info->stream, v850_reg_names[first]);
+ info->fprintf_func (info->stream, "%s", v850_reg_names[first]);
for (bit++; bit < 32; bit++)
if ((mask & (1 << bit)) == 0)
--
Alan Modra
Australia Development Lab, IBM