Re: [PATCH, v2]: AMD btver1 and btver2 enablement

["H.J. Lu" <hjl dot tools at gmail dot com>]

On Thu, Aug 16, 2012 at 10:56 AM, Eggone, NagaJyothi
<NagaJyothi.Eggone@amd.com> wrote:
>
>
>> -----Original Message-----
>> From: H.J. Lu [mailto:hjl.tools@gmail.com]
>> Sent: Thursday, August 16, 2012 8:17 PM
>> To: Eggone, NagaJyothi
>> Cc: binutils@sourceware.org
>> Subject: Re: [PATCH, v2]: AMD btver1 and btver2 enablement
>>
>> On Mon, Aug 13, 2012 at 11:33 PM, Eggone, NagaJyothi
>> <NagaJyothi.Eggone@amd.com> wrote:
>> > Hello,
>> >
>> > I did not receive any reviews for the patch I submitted last week.
>> > I made some changes in the patch format and test files and am
>> submitting again.
>> > Please review and if found OK, please commit the patch on my behalf.
>> >
>> > NOTE: I have omitted the diffs in the generated files opcodes/i386-
>> init.h and opcodes/i386-tbl.h in the patch.
>> > So please use --enable-maintainer-mode to test the patch.
>> >
>> > Thanks,
>> > Nagajyothi
>> >
>> > ---------------------------------------------------------------------
>> -------------
>> > From: Eggone, NagaJyothi
>> > Sent: Thursday, August 09, 2012 2:35 PM
>> > To: binutils@sourceware.org
>> > Cc: Eggone, NagaJyothi
>> > Subject: [PATCH]:AMD btver1 and btver2 enablement
>> >
>> > Hello Maintainers,
>> >
>> > I have added the basic support for AMD's low power btver1 and btver2
>> cores.
>> > I have added the cpu_arch entries for btver1 and btver2, and defined
>> respective CPU_BTVER*_FLAGS.
>> > As part of btver1 enablement, 3dnow instructions prefetch and
>> prefetchw are also extended.
>> >
>> > I have tested on x86_64-unknown-linux-gnu. If it is OK for trunk,
>> please commit on my behalf.
>> >
>> > NOTE: I have omitted the large diffs in the generated files
>> opcodes/i386-init.h and opcodes/i386-tbl.h in the patch.
>> > So please use --enable-maintainer-mode to test the patch.
>> >
>> > Thanks,
>> > Nagajyothi
>>
>> Do you really need Cpu3dnowPrfch? Where will it be used?
>
> The 3dnow 'prefetch' and 'prefetchw' instructions are available both on the btver1 and btver2 cores. I could not have enabled both these instructions for these cores without adding a cpu flag bit (this corresponds to the cpuid ECX bit 8 on AMD processors).

Please drop Cpu3dnowPrfch and add CpuPRFCHW to
prefetch.

>>
>> Also, please reformat your ChangeLog entries to follow
>> existing ones.
>
> Please find attached the reformatted ChangeLog entries.
>

gas/testsuite changes should be in gas/testsuite/ChangeLog.

Thanks.

-- 
H.J.