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[Patch, AArch64] Update the system register table
- From: Yufeng Zhang <Yufeng dot Zhang at arm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: Richard Earnshaw <Richard dot Earnshaw at arm dot com>
- Date: Mon, 15 Oct 2012 14:58:45 +0100
- Subject: [Patch, AArch64] Update the system register table
Hi,
This patch adds the missing system registers "rmr_el[1-3]" to the table
and removes "daifset" and "daifclr" which have already been defined in
the table of "aarch64_pstatefields".
Is it OK to commit?
Thanks,
Yufeng
2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and
rmr_el3;
remove daifset and daifclr.
2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/sysreg-1.s: Add tests of rmr_el1, rmr_el2 and
rmr_el3.
* gas/aarch64/sysreg-1.d: Update.
* gas/aarch64/illegal.s: Add tests of daifset and daifclr.
* gas/aarch64/illegal.d: Update.diff --git a/gas/testsuite/gas/aarch64/illegal.l b/gas/testsuite/gas/aarch64/illegal.l
index 74386ff..6c741cf 100644
--- a/gas/testsuite/gas/aarch64/illegal.l
+++ b/gas/testsuite/gas/aarch64/illegal.l
@@ -547,3 +547,5 @@
[^:]*:535: Error: .*`orr x0. x0,#0xff,lsl#1'
[^:]*:536: Error: .*`orr x0,x0,#0xff lsl#1'
[^:]*:538: Error: .*`mov x0,##5'
+[^:]*:540: Error: .*`msr daifset,x0'
+[^:]*:541: Error: .*`msr daifclr,x0'
diff --git a/gas/testsuite/gas/aarch64/illegal.s b/gas/testsuite/gas/aarch64/illegal.s
index ed31ee1..9a12463 100644
--- a/gas/testsuite/gas/aarch64/illegal.s
+++ b/gas/testsuite/gas/aarch64/illegal.s
@@ -536,3 +536,6 @@
orr x0, x0, #0xff lsl #1
mov x0, ##5
+
+ msr daifset, x0
+ msr daifclr, x0
diff --git a/gas/testsuite/gas/aarch64/sysreg-1.d b/gas/testsuite/gas/aarch64/sysreg-1.d
index 684bf0b..75f75b7 100644
--- a/gas/testsuite/gas/aarch64/sysreg-1.d
+++ b/gas/testsuite/gas/aarch64/sysreg-1.d
@@ -4271,3 +4271,9 @@ Disassembly of section \.text:
429c: d513040f msr dbgdtr_el0, x15
42a0: d533040f mrs x15, dbgdtr_el0
42a4: d533050f mrs x15, dbgdtrrx_el0
+ 42a8: d518c04f msr rmr_el1, x15
+ 42ac: d538c04f mrs x15, rmr_el1
+ 42b0: d51cc04f msr rmr_el2, x15
+ 42b4: d53cc04f mrs x15, rmr_el2
+ 42b8: d51ec04f msr rmr_el3, x15
+ 42bc: d53ec04f mrs x15, rmr_el3
diff --git a/gas/testsuite/gas/aarch64/sysreg-1.s b/gas/testsuite/gas/aarch64/sysreg-1.s
index eb8649b..a2fcef4 100644
--- a/gas/testsuite/gas/aarch64/sysreg-1.s
+++ b/gas/testsuite/gas/aarch64/sysreg-1.s
@@ -158,3 +158,7 @@
rw_sys_reg sys_reg=dbgdtr_el0 xreg=x15 r=1 w=1
rw_sys_reg sys_reg=dbgdtrrx_el0 xreg=x15 r=1 w=0
+
+ rw_sys_reg sys_reg=rmr_el1 xreg=x15 r=1 w=1
+ rw_sys_reg sys_reg=rmr_el2 xreg=x15 r=1 w=1
+ rw_sys_reg sys_reg=rmr_el3 xreg=x15 r=1 w=1
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 68572f8..2f134df 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2771,6 +2771,9 @@ const struct aarch64_name_value_pair aarch64_sys_regs [] =
{ "rvbar_el1", CPENC(3,0,C12,C0,1) }, /* RO */
{ "rvbar_el2", CPENC(3,4,C12,C0,1) }, /* RO */
{ "rvbar_el3", CPENC(3,6,C12,C0,1) }, /* RO */
+ { "rmr_el1", CPENC(3,0,C12,C0,2) },
+ { "rmr_el2", CPENC(3,4,C12,C0,2) },
+ { "rmr_el3", CPENC(3,6,C12,C0,2) },
{ "isr_el1", CPENC(3,0,C12,C1,0) }, /* RO */
{ "contextidr_el1", CPENC(3,0,C13,C0,1) },
{ "tpidr_el0", CPENC(3,3,C13,C0,2) },
@@ -2962,10 +2965,6 @@ const struct aarch64_name_value_pair aarch64_sys_regs [] =
{ "pmevtyper29_el0", CPENC(3,3,C14,C15,5) },
{ "pmevtyper30_el0", CPENC(3,3,C14,C15,6) },
{ "pmccfiltr_el0", CPENC(3,3,C14,C15,7) },
-
- { "daifset", CPENC(0,3,C4,C0,6) },
- { "daifclr", CPENC(0,3,C4,C0,7) },
-
{ 0, CPENC(0,0,0,0,0) },
};