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Binutils: [Patch, microblaze, gas, opcodes] Add support for slr and shr registers
- From: David Holsgrove <david dot holsgrove at xilinx dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: John Williams <jwilliams at xilinx dot com>, Michael Eager <eager at eagerm dot com>, Vinod Kathail <vinodk at xilinx dot com>, Tom Shui <tshui at xilinx dot com>, Vidhumouli Hunsigida <vidhum at xilinx dot com>, Nagaraju Mekala <nmekala at xilinx dot com>, "Edgar E. Iglesias" <edgar dot iglesias at gmail dot com>
- Date: Thu, 8 Nov 2012 12:48:04 +0000
- Subject: Binutils: [Patch, microblaze, gas, opcodes] Add support for slr and shr registers
Add stack high register and stack low register for MicroBlaze
hardware assisted stack protection, stores stack low / stack high limits
for detecting stack overflow / underflow
Added to gas/testsuite/microblaze/gas/allinsns to check awareness of
registers
binutils/opcodes/Changelog
2012-11-08 Edgar E. Iglesias <edgar.iglesias@gmail.com>
* microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK,
REG_SHR and REG_SLR
* microblaze-dis.c (get_field_special): Handle REG_SLR_MASK
and REG_SHR_MASK
binutils/gas/Changelog
2012-11-08 Edgar E. Iglesias <edgar.iglesias@gmail.com>
* config/tc-microblaze.c (parse_reg): Parse REG_SLR, REG_SHR
binutils/gas/testsuite/Changelog
2012-11-08 David Holsgrove <david.holsgrove@xilinx.com>
* gas/microblaze/allinsn.s: Test use of SHR, SLR
* gas/microblaze/allinsn.d: Likewise
From 6a7189b68766022407d527b76ad7ea127d527ff5 Mon Sep 17 00:00:00 2001
From: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Date: Fri, 4 Nov 2011 00:07:54 +0100
Subject: [PATCH] opcodes/ * config/tc-microblaze.c: Add support for slr and shr registers
Add stack high register and stack low register for MicroBlaze
hardware assisted stack protection, stores stack low / stack high limits
for detecting stack overflow / underflow
Added to gas/testsuite/microblaze/gas/allinsns to check awareness of
registers
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
---
gas/config/tc-microblaze.c | 20 ++++++++++++++++++++
gas/testsuite/gas/microblaze/allinsn.d | 10 ++++++++++
gas/testsuite/gas/microblaze/allinsn.s | 10 ++++++++++
opcodes/microblaze-dis.c | 6 ++++++
opcodes/microblaze-opcm.h | 4 ++++
5 files changed, 50 insertions(+), 0 deletions(-)
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
index b71383b..5a427a0 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -531,6 +531,17 @@ parse_reg (char * s, unsigned * reg)
}
return s;
}
+ /* Stack protection registers. */
+ else if (strncasecmp (s, "rshr", 4) == 0)
+ {
+ *reg = REG_SHR;
+ return s + 4;
+ }
+ else if (strncasecmp (s, "rslr", 4) == 0)
+ {
+ *reg = REG_SLR;
+ return s + 4;
+ }
else
{
if (TOLOWER (s[0]) == 'r')
@@ -760,6 +771,7 @@ check_spl_reg (unsigned * reg)
|| (*reg == REG_PID) || (*reg == REG_ZPR)
|| (*reg == REG_TLBX) || (*reg == REG_TLBLO)
|| (*reg == REG_TLBHI) || (*reg == REG_TLBSX)
+ || (*reg == REG_SHR) || (*reg == REG_SLR)
|| (*reg >= REG_PVR+MIN_PVR_REGNUM && *reg <= REG_PVR+MAX_PVR_REGNUM))
return TRUE;
@@ -1280,6 +1292,10 @@ md_assemble (char * str)
immed = opcode->immval_mask | REG_TLBLO_MASK;
else if (reg2 == REG_TLBHI)
immed = opcode->immval_mask | REG_TLBHI_MASK;
+ else if (reg2 == REG_SHR)
+ immed = opcode->immval_mask | REG_SHR_MASK;
+ else if (reg2 == REG_SLR)
+ immed = opcode->immval_mask | REG_SLR_MASK;
else if (reg2 >= (REG_PVR+MIN_PVR_REGNUM) && reg2 <= (REG_PVR+MAX_PVR_REGNUM))
immed = opcode->immval_mask | REG_PVR_MASK | reg2;
else
@@ -1331,6 +1347,10 @@ md_assemble (char * str)
immed = opcode->immval_mask | REG_TLBHI_MASK;
else if (reg1 == REG_TLBSX)
immed = opcode->immval_mask | REG_TLBSX_MASK;
+ else if (reg1 == REG_SHR)
+ immed = opcode->immval_mask | REG_SHR_MASK;
+ else if (reg1 == REG_SLR)
+ immed = opcode->immval_mask | REG_SLR_MASK;
else
as_fatal (_("invalid value for special purpose register"));
inst |= (reg2 << RA_LOW) & RA_MASK;
diff --git a/gas/testsuite/gas/microblaze/allinsn.d b/gas/testsuite/gas/microblaze/allinsn.d
index ec14020..4a03340 100644
--- a/gas/testsuite/gas/microblaze/allinsn.d
+++ b/gas/testsuite/gas/microblaze/allinsn.d
@@ -31,3 +31,13 @@ Disassembly of section .text:
00000020 <sleep>:
20: ba020004 sleep
+
+00000024 <regslr>:
+ 24: b0000000 imm 0
+ 28: 31600000 addik r11, r0, 0
+ 2c: 940bc800 mts rslr, r11
+
+00000030 <regshr>:
+ 30: b0000000 imm 0
+ 34: 31600000 addik r11, r0, 0
+ 38: 940bc802 mts rshr, r11
diff --git a/gas/testsuite/gas/microblaze/allinsn.s b/gas/testsuite/gas/microblaze/allinsn.s
index 582da17..437444f 100644
--- a/gas/testsuite/gas/microblaze/allinsn.s
+++ b/gas/testsuite/gas/microblaze/allinsn.s
@@ -36,4 +36,14 @@ mbar:
.global sleep
sleep:
sleep
+ .text
+ .global regslr
+regslr:
+ la r11,r0,r0
+ mts rslr,r11
+ .text
+ .global regshr
+regshr:
+ la r11,r0,r0
+ mts rshr,r11
diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
index e204e36..7e3a546 100644
--- a/opcodes/microblaze-dis.c
+++ b/opcodes/microblaze-dis.c
@@ -139,6 +139,12 @@ get_field_special (long instr, struct op_code_struct * op)
case REG_TLBSX_MASK :
strcpy (spr, "tlbsx");
break;
+ case REG_SHR_MASK :
+ strcpy (spr, "shr");
+ break;
+ case REG_SLR_MASK :
+ strcpy (spr, "slr");
+ break;
default :
if (((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000)
== REG_PVR_MASK)
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
index 7b8d20b..1f5d85a 100644
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -78,6 +78,8 @@ enum microblaze_instr_type
#define REG_BTR_MASK 0x800b
#define REG_EDR_MASK 0x800d
#define REG_PVR_MASK 0xa000
+#define REG_SLR_MASK 0x8800
+#define REG_SHR_MASK 0x8802
#define REG_PID_MASK 0x9000
#define REG_ZPR_MASK 0x9001
@@ -99,6 +101,8 @@ enum microblaze_instr_type
#define REG_FSR 39 /* FPU Status reg. */
#define REG_BTR 43 /* Branch Target reg. */
#define REG_EDR 45 /* Exception reg. */
+#define REG_SHR 50 /* Stack High reg. */
+#define REG_SLR 51 /* Stack Low reg. */
#define REG_PVR 40960 /* Program Verification reg. */
#define REG_PID 36864 /* MMU: Process ID reg. */
--
1.7.0.4